SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 58.33 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_sram_ctrl_regs_reg_block.scr_key_rotated.success | 0.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_sram_ctrl_regs_reg_block.readback.en | 33.33 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_sram_ctrl_regs_reg_block.exec.en | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_hw_debug_en_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
0.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 6 | 0 | 0.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 6 | 0 | 0.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
33.33 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 4 | 2 | 33.33 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 4 | 2 | 33.33 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 6 | 0 | 0.00 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
others[0] | 0 | 1 | 1 | |
others[1] | 0 | 1 | 1 | |
others[2] | 0 | 1 | 1 | |
others[3] | 0 | 1 | 1 | |
false | 0 | 1 | 1 | |
true | 0 | 1 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 4 | 2 | 33.33 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
others[0] | 0 | 1 | 1 | |
others[1] | 0 | 1 | 1 | |
others[2] | 0 | 1 | 1 | |
others[3] | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
false | 165 | 1 | T10 | 1 | T12 | 1 | T13 | 1 | ||||
true | 166 | 1 | T2 | 1 | T26 | 1 | T27 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 94 | 1 | T6 | 3 | T18 | 1 | T129 | 1 | ||||
others[1] | 125 | 1 | T6 | 7 | T22 | 2 | T18 | 2 | ||||
others[2] | 125 | 1 | T6 | 3 | T22 | 1 | T18 | 2 | ||||
others[3] | 185 | 1 | T6 | 2 | T22 | 1 | T18 | 3 | ||||
false | 996 | 1 | T3 | 4 | T6 | 28 | T22 | 8 | ||||
true | 973 | 1 | T3 | 1 | T6 | 25 | T22 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 121 | 1 | T6 | 3 | T18 | 1 | T129 | 1 | ||||
others[1] | 779 | 1 | T3 | 2 | T6 | 22 | T22 | 4 | ||||
others[2] | 5742 | 1 | T1 | 1 | T2 | 1 | T3 | 55 | ||||
others[3] | 176 | 1 | T6 | 3 | T22 | 2 | T18 | 3 | ||||
false | 42 | 1 | T6 | 1 | T22 | 2 | T28 | 1 | ||||
true | 31 | 1 | T6 | 3 | T76 | 1 | T130 | 1 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |