Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	833332	1			T3	510		T5	1		T6	570
auto[1]	10241075	1			T3	3678		T4	25		T5	3
auto[2]	679243	1			T3	258		T5	3		T6	359
auto[3]	10095353	1			T3	3553		T4	19		T5	1

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14195126	1			T3	5627		T4	29		T5	4
auto[1]	2079990	1			T3	864		T4	7		T5	2
auto[2]	2089081	1			T3	1326		T4	7		T5	2
auto[3]	3484806	1			T3	182		T4	1		T11	1578

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8433958

1

T3

7990

T4

44

T5

8

auto[1]

13415045

1

T3

9

T11

201995

T6

15

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	291479	1			T3	424		T5	1		T6	481
auto[0]	auto[0]	auto[1]	29839	1			T3	34		T6	44		T22	103
auto[0]	auto[0]	auto[2]	29925	1			T3	46		T6	42		T22	108
auto[0]	auto[0]	auto[3]	7622	1			T3	6		T6	2		T22	10
auto[0]	auto[1]	auto[0]	3191816	1			T3	2757		T4	16		T5	1
auto[0]	auto[1]	auto[1]	331480	1			T3	582		T4	4		T5	1
auto[0]	auto[1]	auto[2]	319733	1			T3	265		T4	4		T5	1
auto[0]	auto[1]	auto[3]	66669	1			T3	70		T4	1		T6	72
auto[0]	auto[2]	auto[0]	245597	1			T5	2		T6	1		T22	1024
auto[0]	auto[2]	auto[1]	25011	1			T22	105		T41	32		T18	503
auto[0]	auto[2]	auto[2]	27639	1			T3	235		T5	1		T6	342
auto[0]	auto[2]	auto[3]	6124	1			T3	23		T6	16		T22	10
auto[0]	auto[3]	auto[0]	3148376	1			T3	2440		T4	13		T6	3368
auto[0]	auto[3]	auto[1]	315575	1			T3	246		T4	3		T5	1
auto[0]	auto[3]	auto[2]	329470	1			T3	779		T4	3		T6	981
auto[0]	auto[3]	auto[3]	67603	1			T3	83		T6	93		T24	136
auto[1]	auto[0]	auto[0]	15891	1			T6	1		T22	2		T18	8
auto[1]	auto[0]	auto[1]	70997	1			T129	1		T99	624		T132	1
auto[1]	auto[0]	auto[2]	71068	1			T99	619		T103	3719		T131	1
auto[1]	auto[0]	auto[3]	316511	1			T18	1		T99	2724		T103	16739
auto[1]	auto[1]	auto[0]	3646394	1			T3	3		T11	83478		T6	5
auto[1]	auto[1]	auto[1]	649565	1			T3	1		T11	8183		T6	2
auto[1]	auto[1]	auto[2]	620802	1			T11	8273		T24	1		T53	9040
auto[1]	auto[1]	auto[3]	1414616	1			T11	789		T53	820		T25	359
auto[1]	auto[2]	auto[0]	12257	1			T18	7		T132	5		T103	828
auto[1]	auto[2]	auto[1]	53997	1			T18	1		T132	1		T103	3463
auto[1]	auto[2]	auto[2]	55876	1			T129	1		T99	540		T103	3126
auto[1]	auto[2]	auto[3]	252742	1			T41	1		T18	1		T99	2512
auto[1]	auto[3]	auto[0]	3643316	1			T3	3		T11	84023		T6	4
auto[1]	auto[3]	auto[1]	603526	1			T3	1		T11	8254		T6	1
auto[1]	auto[3]	auto[2]	634568	1			T3	1		T11	8206		T6	2
auto[1]	auto[3]	auto[3]	1352919	1			T11	789		T53	815		T25	385