Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	348584182	218843	0	0
ctrl_regwen_rd_A	348584182	7174	0	0
exec_rd_A	348584182	6502	0	0
exec_regwen_rd_A	348584182	6672	0	0
readback_rd_A	348584182	4286	0	0
readback_regwen_rd_A	348584182	3698	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348584182	218843	0	0
T12	1233	0	0	0
T26	26227	1266	0	0
T27	50542	2649	0	0
T28	0	4496	0	0
T38	0	1659	0	0
T41	40584	0	0	0
T45	261014	0	0	0
T47	0	4851	0	0
T49	0	4565	0	0
T52	0	8366	0	0
T56	0	6210	0	0
T57	0	5656	0	0
T60	241597	0	0	0
T61	275449	0	0	0
T62	12211	0	0	0
T63	29613	0	0	0
T64	8150	0	0	0
T73	0	3133	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348584182	7174	0	0
T12	1233	0	0	0
T26	26227	89	0	0
T27	50542	0	0	0
T41	40584	0	0	0
T45	261014	0	0	0
T47	0	425	0	0
T48	0	180	0	0
T49	0	226	0	0
T60	241597	0	0	0
T61	275449	0	0	0
T62	12211	0	0	0
T63	29613	0	0	0
T64	8150	0	0	0
T107	0	289	0	0
T108	0	259	0	0
T109	0	291	0	0
T110	0	460	0	0
T111	0	558	0	0
T112	0	167	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348584182	6502	0	0
T12	1233	0	0	0
T26	26227	56	0	0
T27	50542	0	0	0
T41	40584	0	0	0
T45	261014	0	0	0
T47	0	308	0	0
T48	0	186	0	0
T49	0	175	0	0
T60	241597	0	0	0
T61	275449	0	0	0
T62	12211	0	0	0
T63	29613	0	0	0
T64	8150	0	0	0
T107	0	273	0	0
T108	0	216	0	0
T109	0	198	0	0
T110	0	415	0	0
T111	0	501	0	0
T112	0	178	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348584182	6672	0	0
T12	1233	0	0	0
T26	26227	90	0	0
T27	50542	0	0	0
T41	40584	0	0	0
T45	261014	0	0	0
T47	0	388	0	0
T48	0	182	0	0
T49	0	142	0	0
T60	241597	0	0	0
T61	275449	0	0	0
T62	12211	0	0	0
T63	29613	0	0	0
T64	8150	0	0	0
T107	0	320	0	0
T108	0	278	0	0
T109	0	226	0	0
T110	0	434	0	0
T111	0	419	0	0
T112	0	198	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348584182	4286	0	0
T12	1233	0	0	0
T26	26227	107	0	0
T27	50542	0	0	0
T41	40584	0	0	0
T45	261014	0	0	0
T47	0	330	0	0
T48	0	240	0	0
T49	0	154	0	0
T60	241597	0	0	0
T61	275449	0	0	0
T62	12211	0	0	0
T63	29613	0	0	0
T64	8150	0	0	0
T107	0	225	0	0
T108	0	233	0	0
T109	0	198	0	0
T110	0	348	0	0
T111	0	486	0	0
T112	0	144	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348584182	3698	0	0
T12	1233	0	0	0
T26	26227	75	0	0
T27	50542	0	0	0
T41	40584	0	0	0
T45	261014	0	0	0
T47	0	307	0	0
T48	0	152	0	0
T49	0	105	0	0
T60	241597	0	0	0
T61	275449	0	0	0
T62	12211	0	0	0
T63	29613	0	0	0
T64	8150	0	0	0
T107	0	232	0	0
T108	0	180	0	0
T109	0	204	0	0
T110	0	356	0	0
T111	0	423	0	0
T112	0	133	0	0