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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.95 99.16 94.27 99.72 100.00 95.95 99.12 97.44


Total test records in report: 1031
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T794 /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.656631007 Jul 05 05:19:14 PM PDT 24 Jul 05 05:26:00 PM PDT 24 11154570477 ps
T795 /workspace/coverage/default/35.sram_ctrl_max_throughput.3256246156 Jul 05 05:19:31 PM PDT 24 Jul 05 05:19:41 PM PDT 24 868975571 ps
T796 /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.4142568969 Jul 05 05:17:59 PM PDT 24 Jul 05 05:19:58 PM PDT 24 2023771281 ps
T797 /workspace/coverage/default/16.sram_ctrl_mem_partial_access.4268493489 Jul 05 05:17:42 PM PDT 24 Jul 05 05:17:46 PM PDT 24 103732090 ps
T798 /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.1679359855 Jul 05 05:17:14 PM PDT 24 Jul 05 05:17:21 PM PDT 24 217595649 ps
T799 /workspace/coverage/default/39.sram_ctrl_max_throughput.3441567433 Jul 05 05:20:05 PM PDT 24 Jul 05 05:21:45 PM PDT 24 136558280 ps
T800 /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.3780823337 Jul 05 05:17:28 PM PDT 24 Jul 05 05:24:14 PM PDT 24 35622102471 ps
T801 /workspace/coverage/default/42.sram_ctrl_access_during_key_req.4198357947 Jul 05 05:20:31 PM PDT 24 Jul 05 05:30:53 PM PDT 24 4756897402 ps
T802 /workspace/coverage/default/35.sram_ctrl_multiple_keys.1693593737 Jul 05 05:19:32 PM PDT 24 Jul 05 05:36:02 PM PDT 24 9282129868 ps
T803 /workspace/coverage/default/36.sram_ctrl_multiple_keys.3817141376 Jul 05 05:19:44 PM PDT 24 Jul 05 05:35:06 PM PDT 24 10301432480 ps
T804 /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.1173247246 Jul 05 05:19:39 PM PDT 24 Jul 05 05:24:53 PM PDT 24 3847550106 ps
T805 /workspace/coverage/default/16.sram_ctrl_access_during_key_req.25166891 Jul 05 05:17:40 PM PDT 24 Jul 05 05:32:41 PM PDT 24 2871435936 ps
T806 /workspace/coverage/default/19.sram_ctrl_stress_pipeline.3635397794 Jul 05 05:17:57 PM PDT 24 Jul 05 05:21:30 PM PDT 24 2220293173 ps
T807 /workspace/coverage/default/25.sram_ctrl_stress_all.88881278 Jul 05 05:18:30 PM PDT 24 Jul 05 06:15:48 PM PDT 24 156454971268 ps
T808 /workspace/coverage/default/43.sram_ctrl_bijection.2387909997 Jul 05 05:20:38 PM PDT 24 Jul 05 05:21:12 PM PDT 24 1056694114 ps
T809 /workspace/coverage/default/43.sram_ctrl_max_throughput.537142902 Jul 05 05:20:44 PM PDT 24 Jul 05 05:21:09 PM PDT 24 86378331 ps
T810 /workspace/coverage/default/28.sram_ctrl_bijection.1652200395 Jul 05 05:18:50 PM PDT 24 Jul 05 05:19:56 PM PDT 24 4337579313 ps
T811 /workspace/coverage/default/37.sram_ctrl_stress_pipeline.1800554395 Jul 05 05:19:43 PM PDT 24 Jul 05 05:25:16 PM PDT 24 3375537407 ps
T812 /workspace/coverage/default/48.sram_ctrl_executable.2386917014 Jul 05 05:21:31 PM PDT 24 Jul 05 05:34:02 PM PDT 24 5973996747 ps
T813 /workspace/coverage/default/13.sram_ctrl_partial_access.650263763 Jul 05 05:17:41 PM PDT 24 Jul 05 05:17:49 PM PDT 24 194352787 ps
T814 /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.2954437651 Jul 05 05:21:07 PM PDT 24 Jul 05 05:26:16 PM PDT 24 21609370655 ps
T815 /workspace/coverage/default/17.sram_ctrl_stress_all.594124601 Jul 05 05:17:50 PM PDT 24 Jul 05 05:30:28 PM PDT 24 29418254770 ps
T816 /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.1473043623 Jul 05 05:18:31 PM PDT 24 Jul 05 05:20:25 PM PDT 24 656585126 ps
T104 /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.796646683 Jul 05 05:17:11 PM PDT 24 Jul 05 05:18:03 PM PDT 24 2799214807 ps
T817 /workspace/coverage/default/38.sram_ctrl_mem_partial_access.1210057652 Jul 05 05:20:08 PM PDT 24 Jul 05 05:20:12 PM PDT 24 116151067 ps
T818 /workspace/coverage/default/6.sram_ctrl_mem_partial_access.2493000843 Jul 05 05:17:23 PM PDT 24 Jul 05 05:17:28 PM PDT 24 212963891 ps
T819 /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.2058331990 Jul 05 05:17:13 PM PDT 24 Jul 05 05:21:57 PM PDT 24 17659116148 ps
T820 /workspace/coverage/default/32.sram_ctrl_alert_test.146159074 Jul 05 05:19:19 PM PDT 24 Jul 05 05:19:20 PM PDT 24 23150730 ps
T821 /workspace/coverage/default/7.sram_ctrl_ram_cfg.2807179553 Jul 05 05:17:21 PM PDT 24 Jul 05 05:17:23 PM PDT 24 28906123 ps
T822 /workspace/coverage/default/32.sram_ctrl_access_during_key_req.3061790589 Jul 05 05:19:13 PM PDT 24 Jul 05 05:41:12 PM PDT 24 3999959240 ps
T823 /workspace/coverage/default/31.sram_ctrl_mem_walk.616231587 Jul 05 05:19:04 PM PDT 24 Jul 05 05:19:11 PM PDT 24 3680941589 ps
T824 /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.275335584 Jul 05 05:17:42 PM PDT 24 Jul 05 05:19:03 PM PDT 24 7723663624 ps
T825 /workspace/coverage/default/32.sram_ctrl_stress_all.531183037 Jul 05 05:19:19 PM PDT 24 Jul 05 05:48:23 PM PDT 24 6923026304 ps
T826 /workspace/coverage/default/48.sram_ctrl_mem_partial_access.4178632829 Jul 05 05:21:34 PM PDT 24 Jul 05 05:21:39 PM PDT 24 101407281 ps
T827 /workspace/coverage/default/29.sram_ctrl_executable.3623710640 Jul 05 05:18:54 PM PDT 24 Jul 05 05:25:50 PM PDT 24 1247502146 ps
T828 /workspace/coverage/default/6.sram_ctrl_regwen.873483760 Jul 05 05:17:13 PM PDT 24 Jul 05 05:18:51 PM PDT 24 3237779478 ps
T829 /workspace/coverage/default/22.sram_ctrl_access_during_key_req.511186317 Jul 05 05:18:15 PM PDT 24 Jul 05 05:47:01 PM PDT 24 8700302590 ps
T830 /workspace/coverage/default/5.sram_ctrl_mem_walk.1404211611 Jul 05 05:17:21 PM PDT 24 Jul 05 05:17:34 PM PDT 24 663152773 ps
T831 /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.3734302909 Jul 05 05:17:37 PM PDT 24 Jul 05 05:24:52 PM PDT 24 35450869242 ps
T832 /workspace/coverage/default/28.sram_ctrl_stress_all.256622984 Jul 05 05:18:46 PM PDT 24 Jul 05 05:52:39 PM PDT 24 127358284982 ps
T833 /workspace/coverage/default/33.sram_ctrl_stress_pipeline.4290157104 Jul 05 05:19:23 PM PDT 24 Jul 05 05:22:23 PM PDT 24 1881604562 ps
T834 /workspace/coverage/default/9.sram_ctrl_max_throughput.3688744564 Jul 05 05:17:30 PM PDT 24 Jul 05 05:17:34 PM PDT 24 43893566 ps
T835 /workspace/coverage/default/49.sram_ctrl_alert_test.536030877 Jul 05 05:21:44 PM PDT 24 Jul 05 05:21:45 PM PDT 24 20416372 ps
T836 /workspace/coverage/default/3.sram_ctrl_alert_test.4252943764 Jul 05 05:17:07 PM PDT 24 Jul 05 05:17:09 PM PDT 24 35024450 ps
T837 /workspace/coverage/default/48.sram_ctrl_multiple_keys.3321859467 Jul 05 05:21:30 PM PDT 24 Jul 05 05:44:21 PM PDT 24 85558532846 ps
T838 /workspace/coverage/default/14.sram_ctrl_smoke.415642890 Jul 05 05:17:36 PM PDT 24 Jul 05 05:19:07 PM PDT 24 622084759 ps
T839 /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.4006816663 Jul 05 05:17:46 PM PDT 24 Jul 05 05:18:44 PM PDT 24 118948898 ps
T840 /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.104135800 Jul 05 05:18:19 PM PDT 24 Jul 05 05:18:21 PM PDT 24 66945463 ps
T841 /workspace/coverage/default/1.sram_ctrl_alert_test.3483088452 Jul 05 05:17:06 PM PDT 24 Jul 05 05:17:09 PM PDT 24 17018000 ps
T842 /workspace/coverage/default/24.sram_ctrl_access_during_key_req.1440789135 Jul 05 05:18:23 PM PDT 24 Jul 05 05:22:59 PM PDT 24 1390545151 ps
T843 /workspace/coverage/default/24.sram_ctrl_mem_partial_access.3811092943 Jul 05 05:18:25 PM PDT 24 Jul 05 05:18:30 PM PDT 24 181106482 ps
T844 /workspace/coverage/default/7.sram_ctrl_multiple_keys.958723462 Jul 05 05:17:32 PM PDT 24 Jul 05 05:38:48 PM PDT 24 72292070308 ps
T845 /workspace/coverage/default/7.sram_ctrl_stress_all.3088420212 Jul 05 05:17:31 PM PDT 24 Jul 05 05:33:36 PM PDT 24 4652021761 ps
T846 /workspace/coverage/default/39.sram_ctrl_ram_cfg.1215384117 Jul 05 05:20:11 PM PDT 24 Jul 05 05:20:13 PM PDT 24 41581858 ps
T847 /workspace/coverage/default/3.sram_ctrl_access_during_key_req.2083099465 Jul 05 05:17:06 PM PDT 24 Jul 05 05:33:35 PM PDT 24 18140911335 ps
T848 /workspace/coverage/default/31.sram_ctrl_regwen.681199951 Jul 05 05:19:05 PM PDT 24 Jul 05 05:26:42 PM PDT 24 4682762622 ps
T849 /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.964401260 Jul 05 05:16:56 PM PDT 24 Jul 05 05:18:22 PM PDT 24 1217082830 ps
T850 /workspace/coverage/default/6.sram_ctrl_mem_walk.3714863134 Jul 05 05:17:19 PM PDT 24 Jul 05 05:17:25 PM PDT 24 74816256 ps
T851 /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.1800420398 Jul 05 05:17:36 PM PDT 24 Jul 05 05:23:06 PM PDT 24 13755215412 ps
T852 /workspace/coverage/default/12.sram_ctrl_bijection.2890738959 Jul 05 05:17:41 PM PDT 24 Jul 05 05:18:51 PM PDT 24 9044650534 ps
T853 /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.1034876865 Jul 05 05:17:43 PM PDT 24 Jul 05 05:18:04 PM PDT 24 2790004987 ps
T854 /workspace/coverage/default/43.sram_ctrl_ram_cfg.1802636037 Jul 05 05:20:45 PM PDT 24 Jul 05 05:20:46 PM PDT 24 29811882 ps
T855 /workspace/coverage/default/41.sram_ctrl_smoke.1973958130 Jul 05 05:20:18 PM PDT 24 Jul 05 05:22:30 PM PDT 24 247002131 ps
T856 /workspace/coverage/default/45.sram_ctrl_bijection.1759601189 Jul 05 05:20:58 PM PDT 24 Jul 05 05:22:08 PM PDT 24 1094904129 ps
T857 /workspace/coverage/default/23.sram_ctrl_mem_walk.2968326014 Jul 05 05:18:17 PM PDT 24 Jul 05 05:18:29 PM PDT 24 177479460 ps
T858 /workspace/coverage/default/5.sram_ctrl_regwen.3472698546 Jul 05 05:17:17 PM PDT 24 Jul 05 05:31:08 PM PDT 24 13650674874 ps
T859 /workspace/coverage/default/17.sram_ctrl_access_during_key_req.2728101033 Jul 05 05:17:50 PM PDT 24 Jul 05 05:42:16 PM PDT 24 5478432300 ps
T860 /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.3523860841 Jul 05 05:20:18 PM PDT 24 Jul 05 05:24:24 PM PDT 24 9907193923 ps
T861 /workspace/coverage/default/31.sram_ctrl_executable.789052755 Jul 05 05:19:18 PM PDT 24 Jul 05 05:27:48 PM PDT 24 8462229094 ps
T862 /workspace/coverage/default/43.sram_ctrl_alert_test.3232283345 Jul 05 05:20:45 PM PDT 24 Jul 05 05:20:46 PM PDT 24 34173426 ps
T863 /workspace/coverage/default/33.sram_ctrl_stress_all.724994477 Jul 05 05:19:25 PM PDT 24 Jul 05 06:09:36 PM PDT 24 10745743958 ps
T864 /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.1744844324 Jul 05 05:18:24 PM PDT 24 Jul 05 05:21:50 PM PDT 24 34667256515 ps
T865 /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.545919262 Jul 05 05:19:32 PM PDT 24 Jul 05 05:19:55 PM PDT 24 119204267 ps
T866 /workspace/coverage/default/46.sram_ctrl_multiple_keys.4045054683 Jul 05 05:21:06 PM PDT 24 Jul 05 05:38:36 PM PDT 24 8258433905 ps
T867 /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.3523153102 Jul 05 05:21:28 PM PDT 24 Jul 05 05:30:30 PM PDT 24 224683960208 ps
T868 /workspace/coverage/default/22.sram_ctrl_lc_escalation.409071063 Jul 05 05:18:16 PM PDT 24 Jul 05 05:18:26 PM PDT 24 3109240524 ps
T869 /workspace/coverage/default/33.sram_ctrl_smoke.2322652820 Jul 05 05:19:24 PM PDT 24 Jul 05 05:19:37 PM PDT 24 1194794816 ps
T870 /workspace/coverage/default/47.sram_ctrl_alert_test.3696938730 Jul 05 05:21:28 PM PDT 24 Jul 05 05:21:30 PM PDT 24 22928399 ps
T871 /workspace/coverage/default/28.sram_ctrl_max_throughput.2685284042 Jul 05 05:18:44 PM PDT 24 Jul 05 05:18:53 PM PDT 24 417222523 ps
T872 /workspace/coverage/default/0.sram_ctrl_partial_access.1698754647 Jul 05 05:16:57 PM PDT 24 Jul 05 05:17:38 PM PDT 24 1675500516 ps
T873 /workspace/coverage/default/21.sram_ctrl_multiple_keys.2028851621 Jul 05 05:18:09 PM PDT 24 Jul 05 05:21:51 PM PDT 24 8688861749 ps
T874 /workspace/coverage/default/2.sram_ctrl_smoke.850310849 Jul 05 05:17:13 PM PDT 24 Jul 05 05:18:37 PM PDT 24 2011265009 ps
T875 /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.1492350590 Jul 05 05:17:44 PM PDT 24 Jul 05 05:22:00 PM PDT 24 18854537460 ps
T876 /workspace/coverage/default/16.sram_ctrl_ram_cfg.2098419666 Jul 05 05:17:57 PM PDT 24 Jul 05 05:17:59 PM PDT 24 88087416 ps
T877 /workspace/coverage/default/38.sram_ctrl_regwen.1807785213 Jul 05 05:19:58 PM PDT 24 Jul 05 05:22:57 PM PDT 24 14107366893 ps
T878 /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.3170854980 Jul 05 05:20:41 PM PDT 24 Jul 05 05:24:45 PM PDT 24 3358340089 ps
T879 /workspace/coverage/default/14.sram_ctrl_ram_cfg.852589833 Jul 05 05:17:35 PM PDT 24 Jul 05 05:17:38 PM PDT 24 82900658 ps
T880 /workspace/coverage/default/27.sram_ctrl_max_throughput.271895861 Jul 05 05:18:39 PM PDT 24 Jul 05 05:19:12 PM PDT 24 388023199 ps
T881 /workspace/coverage/default/26.sram_ctrl_lc_escalation.2828462859 Jul 05 05:18:46 PM PDT 24 Jul 05 05:18:51 PM PDT 24 1201422542 ps
T882 /workspace/coverage/default/36.sram_ctrl_mem_walk.228288607 Jul 05 05:19:46 PM PDT 24 Jul 05 05:19:52 PM PDT 24 808486958 ps
T883 /workspace/coverage/default/13.sram_ctrl_regwen.1568919795 Jul 05 05:17:37 PM PDT 24 Jul 05 05:32:56 PM PDT 24 5558039740 ps
T884 /workspace/coverage/default/34.sram_ctrl_access_during_key_req.275281906 Jul 05 05:19:25 PM PDT 24 Jul 05 05:32:32 PM PDT 24 10352983682 ps
T885 /workspace/coverage/default/10.sram_ctrl_stress_pipeline.200329775 Jul 05 05:17:25 PM PDT 24 Jul 05 05:23:13 PM PDT 24 31100457993 ps
T886 /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.3946183882 Jul 05 05:17:40 PM PDT 24 Jul 05 05:23:50 PM PDT 24 11718197629 ps
T887 /workspace/coverage/default/49.sram_ctrl_stress_all.118331464 Jul 05 05:21:45 PM PDT 24 Jul 05 06:31:05 PM PDT 24 41802849198 ps
T888 /workspace/coverage/default/29.sram_ctrl_max_throughput.52009652 Jul 05 05:18:52 PM PDT 24 Jul 05 05:19:23 PM PDT 24 90366793 ps
T889 /workspace/coverage/default/24.sram_ctrl_max_throughput.2949539592 Jul 05 05:18:22 PM PDT 24 Jul 05 05:20:48 PM PDT 24 140908289 ps
T890 /workspace/coverage/default/42.sram_ctrl_multiple_keys.355807259 Jul 05 05:20:30 PM PDT 24 Jul 05 05:32:13 PM PDT 24 26066737730 ps
T891 /workspace/coverage/default/43.sram_ctrl_partial_access.115586977 Jul 05 05:20:40 PM PDT 24 Jul 05 05:20:46 PM PDT 24 133431221 ps
T892 /workspace/coverage/default/49.sram_ctrl_access_during_key_req.277619590 Jul 05 05:21:44 PM PDT 24 Jul 05 05:30:08 PM PDT 24 2601824069 ps
T893 /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.952805465 Jul 05 05:20:02 PM PDT 24 Jul 05 05:25:04 PM PDT 24 11310556388 ps
T894 /workspace/coverage/default/22.sram_ctrl_executable.3245915812 Jul 05 05:18:24 PM PDT 24 Jul 05 05:26:54 PM PDT 24 7497990335 ps
T895 /workspace/coverage/default/13.sram_ctrl_mem_partial_access.354460448 Jul 05 05:17:40 PM PDT 24 Jul 05 05:17:44 PM PDT 24 402911539 ps
T896 /workspace/coverage/default/5.sram_ctrl_smoke.1090319657 Jul 05 05:17:13 PM PDT 24 Jul 05 05:17:16 PM PDT 24 76764862 ps
T897 /workspace/coverage/default/4.sram_ctrl_bijection.3429147975 Jul 05 05:17:09 PM PDT 24 Jul 05 05:17:51 PM PDT 24 2495560845 ps
T898 /workspace/coverage/default/41.sram_ctrl_partial_access.321399891 Jul 05 05:20:25 PM PDT 24 Jul 05 05:20:43 PM PDT 24 650637626 ps
T899 /workspace/coverage/default/43.sram_ctrl_lc_escalation.4263456367 Jul 05 05:20:44 PM PDT 24 Jul 05 05:20:49 PM PDT 24 1406759799 ps
T900 /workspace/coverage/default/8.sram_ctrl_ram_cfg.1019812490 Jul 05 05:17:34 PM PDT 24 Jul 05 05:17:36 PM PDT 24 97993270 ps
T901 /workspace/coverage/default/29.sram_ctrl_mem_partial_access.1257760426 Jul 05 05:18:59 PM PDT 24 Jul 05 05:19:05 PM PDT 24 359328113 ps
T902 /workspace/coverage/default/22.sram_ctrl_partial_access.945706265 Jul 05 05:18:16 PM PDT 24 Jul 05 05:18:18 PM PDT 24 41097763 ps
T903 /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.2670025856 Jul 05 05:20:53 PM PDT 24 Jul 05 05:20:55 PM PDT 24 43190642 ps
T904 /workspace/coverage/default/25.sram_ctrl_mem_partial_access.1698239702 Jul 05 05:18:32 PM PDT 24 Jul 05 05:18:39 PM PDT 24 326182038 ps
T905 /workspace/coverage/default/45.sram_ctrl_smoke.2562075399 Jul 05 05:20:59 PM PDT 24 Jul 05 05:21:56 PM PDT 24 423042317 ps
T906 /workspace/coverage/default/11.sram_ctrl_partial_access.2760571183 Jul 05 05:17:29 PM PDT 24 Jul 05 05:17:39 PM PDT 24 268747014 ps
T907 /workspace/coverage/default/47.sram_ctrl_bijection.1826011603 Jul 05 05:21:21 PM PDT 24 Jul 05 05:21:38 PM PDT 24 900787628 ps
T908 /workspace/coverage/default/45.sram_ctrl_ram_cfg.1525860595 Jul 05 05:21:05 PM PDT 24 Jul 05 05:21:06 PM PDT 24 27284177 ps
T909 /workspace/coverage/default/8.sram_ctrl_stress_all.2229123212 Jul 05 05:17:29 PM PDT 24 Jul 05 05:58:57 PM PDT 24 9024793026 ps
T910 /workspace/coverage/default/11.sram_ctrl_regwen.2836963202 Jul 05 05:17:29 PM PDT 24 Jul 05 05:44:59 PM PDT 24 4124254908 ps
T911 /workspace/coverage/default/4.sram_ctrl_smoke.76028420 Jul 05 05:17:08 PM PDT 24 Jul 05 05:17:18 PM PDT 24 1116263471 ps
T912 /workspace/coverage/default/5.sram_ctrl_alert_test.3164764879 Jul 05 05:17:32 PM PDT 24 Jul 05 05:17:34 PM PDT 24 25450654 ps
T913 /workspace/coverage/default/36.sram_ctrl_stress_all.926957518 Jul 05 05:19:43 PM PDT 24 Jul 05 05:38:58 PM PDT 24 27750811929 ps
T914 /workspace/coverage/default/17.sram_ctrl_ram_cfg.1780467659 Jul 05 05:17:47 PM PDT 24 Jul 05 05:17:49 PM PDT 24 76802702 ps
T915 /workspace/coverage/default/26.sram_ctrl_alert_test.1148539521 Jul 05 05:18:40 PM PDT 24 Jul 05 05:18:42 PM PDT 24 43577155 ps
T916 /workspace/coverage/default/29.sram_ctrl_alert_test.378176814 Jul 05 05:18:59 PM PDT 24 Jul 05 05:19:01 PM PDT 24 19141843 ps
T917 /workspace/coverage/default/33.sram_ctrl_mem_walk.3795118648 Jul 05 05:19:25 PM PDT 24 Jul 05 05:19:31 PM PDT 24 99965567 ps
T918 /workspace/coverage/default/32.sram_ctrl_stress_pipeline.118498649 Jul 05 05:19:11 PM PDT 24 Jul 05 05:22:57 PM PDT 24 9360883285 ps
T919 /workspace/coverage/default/45.sram_ctrl_access_during_key_req.2391120721 Jul 05 05:21:07 PM PDT 24 Jul 05 05:40:44 PM PDT 24 26460376966 ps
T920 /workspace/coverage/default/8.sram_ctrl_stress_pipeline.4255808435 Jul 05 05:17:22 PM PDT 24 Jul 05 05:21:46 PM PDT 24 2639176308 ps
T921 /workspace/coverage/default/48.sram_ctrl_stress_pipeline.2328809600 Jul 05 05:21:25 PM PDT 24 Jul 05 05:25:26 PM PDT 24 2432238298 ps
T922 /workspace/coverage/default/21.sram_ctrl_regwen.2285285614 Jul 05 05:18:10 PM PDT 24 Jul 05 05:35:39 PM PDT 24 7271023060 ps
T923 /workspace/coverage/default/40.sram_ctrl_stress_all.1417629760 Jul 05 05:20:19 PM PDT 24 Jul 05 07:04:52 PM PDT 24 15135864599 ps
T924 /workspace/coverage/default/19.sram_ctrl_max_throughput.2783294785 Jul 05 05:17:55 PM PDT 24 Jul 05 05:18:28 PM PDT 24 167926189 ps
T925 /workspace/coverage/default/33.sram_ctrl_alert_test.2214373353 Jul 05 05:19:23 PM PDT 24 Jul 05 05:19:24 PM PDT 24 14308144 ps
T926 /workspace/coverage/default/34.sram_ctrl_regwen.3181064414 Jul 05 05:19:27 PM PDT 24 Jul 05 05:35:49 PM PDT 24 1605423781 ps
T927 /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.1871890198 Jul 05 05:18:58 PM PDT 24 Jul 05 05:23:45 PM PDT 24 21846715654 ps
T928 /workspace/coverage/default/31.sram_ctrl_bijection.685424223 Jul 05 05:19:08 PM PDT 24 Jul 05 05:20:23 PM PDT 24 3863538590 ps
T929 /workspace/coverage/default/8.sram_ctrl_max_throughput.712239142 Jul 05 05:18:05 PM PDT 24 Jul 05 05:18:20 PM PDT 24 71754510 ps
T930 /workspace/coverage/default/46.sram_ctrl_max_throughput.4072830502 Jul 05 05:21:14 PM PDT 24 Jul 05 05:21:16 PM PDT 24 68345791 ps
T931 /workspace/coverage/default/39.sram_ctrl_partial_access.1600288955 Jul 05 05:20:06 PM PDT 24 Jul 05 05:20:11 PM PDT 24 702359705 ps
T932 /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.2576415196 Jul 05 05:18:51 PM PDT 24 Jul 05 05:30:06 PM PDT 24 539595639288 ps
T933 /workspace/coverage/default/33.sram_ctrl_lc_escalation.1393402334 Jul 05 05:19:18 PM PDT 24 Jul 05 05:19:25 PM PDT 24 430864678 ps
T934 /workspace/coverage/default/19.sram_ctrl_access_during_key_req.4137431507 Jul 05 05:17:58 PM PDT 24 Jul 05 05:22:01 PM PDT 24 5896786423 ps
T935 /workspace/coverage/default/0.sram_ctrl_mem_partial_access.4223687188 Jul 05 05:17:02 PM PDT 24 Jul 05 05:17:10 PM PDT 24 170384621 ps
T936 /workspace/coverage/default/17.sram_ctrl_stress_pipeline.3586980958 Jul 05 05:17:43 PM PDT 24 Jul 05 05:23:00 PM PDT 24 12546553970 ps
T937 /workspace/coverage/default/15.sram_ctrl_executable.727086157 Jul 05 05:17:49 PM PDT 24 Jul 05 05:30:11 PM PDT 24 12684888051 ps
T938 /workspace/coverage/default/25.sram_ctrl_partial_access.2906561654 Jul 05 05:18:31 PM PDT 24 Jul 05 05:18:51 PM PDT 24 1416580998 ps
T939 /workspace/coverage/default/37.sram_ctrl_lc_escalation.3884402052 Jul 05 05:19:45 PM PDT 24 Jul 05 05:19:54 PM PDT 24 605913178 ps
T940 /workspace/coverage/default/16.sram_ctrl_executable.3571080506 Jul 05 05:17:57 PM PDT 24 Jul 05 05:29:59 PM PDT 24 14510002444 ps
T941 /workspace/coverage/default/5.sram_ctrl_stress_all.3519643597 Jul 05 05:17:18 PM PDT 24 Jul 05 06:02:32 PM PDT 24 33478830954 ps
T54 /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.973890000 Jul 05 04:28:49 PM PDT 24 Jul 05 04:28:59 PM PDT 24 28434297 ps
T51 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1070360879 Jul 05 04:28:12 PM PDT 24 Jul 05 04:28:26 PM PDT 24 108289735 ps
T52 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1299225647 Jul 05 04:28:20 PM PDT 24 Jul 05 04:28:41 PM PDT 24 388248324 ps
T62 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2247582960 Jul 05 04:28:01 PM PDT 24 Jul 05 04:28:08 PM PDT 24 48125172 ps
T63 /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3039674940 Jul 05 04:28:05 PM PDT 24 Jul 05 04:28:16 PM PDT 24 1589628786 ps
T64 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3285754087 Jul 05 04:28:06 PM PDT 24 Jul 05 04:28:16 PM PDT 24 15353016 ps
T942 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3687364812 Jul 05 04:28:09 PM PDT 24 Jul 05 04:28:24 PM PDT 24 430939408 ps
T90 /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3601799541 Jul 05 04:28:11 PM PDT 24 Jul 05 04:28:25 PM PDT 24 18457317 ps
T943 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3103201192 Jul 05 04:28:16 PM PDT 24 Jul 05 04:28:30 PM PDT 24 117244629 ps
T65 /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2093080115 Jul 05 04:28:11 PM PDT 24 Jul 05 04:28:25 PM PDT 24 245809309 ps
T66 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.463442089 Jul 05 04:28:06 PM PDT 24 Jul 05 04:28:16 PM PDT 24 118353157 ps
T67 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.585971271 Jul 05 04:28:08 PM PDT 24 Jul 05 04:28:19 PM PDT 24 67157344 ps
T68 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2022555700 Jul 05 04:28:16 PM PDT 24 Jul 05 04:28:29 PM PDT 24 38302957 ps
T944 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2645901513 Jul 05 04:28:09 PM PDT 24 Jul 05 04:28:22 PM PDT 24 26799835 ps
T945 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1279950665 Jul 05 04:29:14 PM PDT 24 Jul 05 04:29:24 PM PDT 24 127662149 ps
T91 /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3351439040 Jul 05 04:28:28 PM PDT 24 Jul 05 04:28:42 PM PDT 24 30315156 ps
T69 /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.945637908 Jul 05 04:28:04 PM PDT 24 Jul 05 04:28:13 PM PDT 24 223856681 ps
T70 /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2782729005 Jul 05 04:28:19 PM PDT 24 Jul 05 04:28:32 PM PDT 24 16368073 ps
T71 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3994842611 Jul 05 04:28:12 PM PDT 24 Jul 05 04:28:26 PM PDT 24 99293504 ps
T946 /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1610338067 Jul 05 04:29:19 PM PDT 24 Jul 05 04:29:29 PM PDT 24 231500779 ps
T947 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3196732858 Jul 05 04:27:58 PM PDT 24 Jul 05 04:28:05 PM PDT 24 161180510 ps
T74 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2555478796 Jul 05 04:28:02 PM PDT 24 Jul 05 04:28:10 PM PDT 24 48637943 ps
T948 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.4194162049 Jul 05 04:28:05 PM PDT 24 Jul 05 04:28:14 PM PDT 24 24020651 ps
T949 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.4184135212 Jul 05 04:28:05 PM PDT 24 Jul 05 04:28:14 PM PDT 24 40997137 ps
T53 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3583293635 Jul 05 04:28:19 PM PDT 24 Jul 05 04:28:33 PM PDT 24 184992756 ps
T950 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1073176365 Jul 05 04:28:24 PM PDT 24 Jul 05 04:28:42 PM PDT 24 254828740 ps
T75 /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1531857019 Jul 05 04:28:15 PM PDT 24 Jul 05 04:28:31 PM PDT 24 4954772475 ps
T951 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2215376318 Jul 05 04:27:55 PM PDT 24 Jul 05 04:28:00 PM PDT 24 13843671 ps
T76 /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2656324049 Jul 05 04:28:12 PM PDT 24 Jul 05 04:28:28 PM PDT 24 1553431692 ps
T952 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.577587583 Jul 05 04:29:34 PM PDT 24 Jul 05 04:29:40 PM PDT 24 38314836 ps
T953 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1924654358 Jul 05 04:28:05 PM PDT 24 Jul 05 04:28:15 PM PDT 24 30108448 ps
T117 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.978110680 Jul 05 04:29:15 PM PDT 24 Jul 05 04:29:26 PM PDT 24 230465358 ps
T954 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.827974601 Jul 05 04:28:20 PM PDT 24 Jul 05 04:28:34 PM PDT 24 26535854 ps
T955 /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.4225968938 Jul 05 04:27:59 PM PDT 24 Jul 05 04:28:04 PM PDT 24 31587613 ps
T956 /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3567713169 Jul 05 04:27:59 PM PDT 24 Jul 05 04:28:06 PM PDT 24 19844080 ps
T77 /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2421455499 Jul 05 04:28:04 PM PDT 24 Jul 05 04:28:13 PM PDT 24 327920161 ps
T957 /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1148721573 Jul 05 04:28:19 PM PDT 24 Jul 05 04:28:32 PM PDT 24 26652357 ps
T958 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1537506784 Jul 05 04:27:46 PM PDT 24 Jul 05 04:27:53 PM PDT 24 33842757 ps
T959 /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2014251831 Jul 05 04:28:06 PM PDT 24 Jul 05 04:28:17 PM PDT 24 278933477 ps
T112 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2782992436 Jul 05 04:27:57 PM PDT 24 Jul 05 04:28:10 PM PDT 24 296278178 ps
T960 /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.135162076 Jul 05 04:28:19 PM PDT 24 Jul 05 04:28:35 PM PDT 24 233063990 ps
T961 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3570926932 Jul 05 04:27:56 PM PDT 24 Jul 05 04:28:02 PM PDT 24 40081921 ps
T962 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3309267193 Jul 05 04:28:26 PM PDT 24 Jul 05 04:28:40 PM PDT 24 46666373 ps
T963 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1094164911 Jul 05 04:28:02 PM PDT 24 Jul 05 04:28:12 PM PDT 24 338864308 ps
T964 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3786822944 Jul 05 04:28:11 PM PDT 24 Jul 05 04:28:24 PM PDT 24 79288626 ps
T965 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3293211138 Jul 05 04:28:09 PM PDT 24 Jul 05 04:28:20 PM PDT 24 41927396 ps
T116 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1792799987 Jul 05 04:29:22 PM PDT 24 Jul 05 04:29:32 PM PDT 24 151017361 ps
T966 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3686931257 Jul 05 04:28:19 PM PDT 24 Jul 05 04:28:33 PM PDT 24 12750879 ps
T84 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2635821238 Jul 05 04:27:58 PM PDT 24 Jul 05 04:28:04 PM PDT 24 66194432 ps
T967 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3435749865 Jul 05 04:28:13 PM PDT 24 Jul 05 04:28:30 PM PDT 24 48949757 ps
T113 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3142147428 Jul 05 04:28:21 PM PDT 24 Jul 05 04:28:36 PM PDT 24 175969915 ps
T968 /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3458127619 Jul 05 04:28:04 PM PDT 24 Jul 05 04:28:14 PM PDT 24 1706707657 ps
T969 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.882394031 Jul 05 04:28:18 PM PDT 24 Jul 05 04:28:31 PM PDT 24 101995610 ps
T970 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2591814180 Jul 05 04:28:07 PM PDT 24 Jul 05 04:28:17 PM PDT 24 53973440 ps
T122 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3255900672 Jul 05 04:28:06 PM PDT 24 Jul 05 04:28:17 PM PDT 24 165309241 ps
T124 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.352348766 Jul 05 04:28:02 PM PDT 24 Jul 05 04:28:10 PM PDT 24 433848319 ps
T971 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2597304340 Jul 05 04:28:04 PM PDT 24 Jul 05 04:28:12 PM PDT 24 24018027 ps
T972 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1892376695 Jul 05 04:28:05 PM PDT 24 Jul 05 04:28:15 PM PDT 24 30145729 ps
T973 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2760572602 Jul 05 04:28:07 PM PDT 24 Jul 05 04:28:20 PM PDT 24 324086090 ps
T974 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.27414948 Jul 05 04:27:57 PM PDT 24 Jul 05 04:28:04 PM PDT 24 143152373 ps
T975 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3247160140 Jul 05 04:28:29 PM PDT 24 Jul 05 04:28:44 PM PDT 24 127052720 ps
T976 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.4180377386 Jul 05 04:28:16 PM PDT 24 Jul 05 04:28:30 PM PDT 24 109185236 ps
T120 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.582043479 Jul 05 04:29:23 PM PDT 24 Jul 05 04:29:34 PM PDT 24 550719393 ps
T977 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3929476129 Jul 05 04:29:04 PM PDT 24 Jul 05 04:29:13 PM PDT 24 31078102 ps
T978 /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3195423711 Jul 05 04:28:14 PM PDT 24 Jul 05 04:28:28 PM PDT 24 79478081 ps
T979 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.517509988 Jul 05 04:27:55 PM PDT 24 Jul 05 04:28:00 PM PDT 24 35668200 ps
T980 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3674997531 Jul 05 04:27:55 PM PDT 24 Jul 05 04:28:00 PM PDT 24 22161030 ps
T85 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.4290463331 Jul 05 04:28:00 PM PDT 24 Jul 05 04:28:06 PM PDT 24 25050268 ps
T981 /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.122077761 Jul 05 04:27:59 PM PDT 24 Jul 05 04:28:08 PM PDT 24 1454921324 ps
T982 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2918402254 Jul 05 04:28:13 PM PDT 24 Jul 05 04:28:28 PM PDT 24 26161784 ps
T86 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3995549988 Jul 05 04:28:19 PM PDT 24 Jul 05 04:28:32 PM PDT 24 19662702 ps
T125 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3351288497 Jul 05 04:28:18 PM PDT 24 Jul 05 04:28:32 PM PDT 24 257553067 ps
T983 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.4004989880 Jul 05 04:28:01 PM PDT 24 Jul 05 04:28:09 PM PDT 24 27505475 ps
T984 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3971049464 Jul 05 04:28:05 PM PDT 24 Jul 05 04:28:13 PM PDT 24 46168738 ps
T985 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.545054656 Jul 05 04:27:59 PM PDT 24 Jul 05 04:28:07 PM PDT 24 43598511 ps
T82 /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3898771759 Jul 05 04:28:22 PM PDT 24 Jul 05 04:28:36 PM PDT 24 3977982676 ps
T986 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.344772901 Jul 05 04:28:07 PM PDT 24 Jul 05 04:28:18 PM PDT 24 31468795 ps
T987 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.399624728 Jul 05 04:28:15 PM PDT 24 Jul 05 04:28:30 PM PDT 24 41422793 ps
T988 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2958243198 Jul 05 04:27:59 PM PDT 24 Jul 05 04:28:05 PM PDT 24 89714001 ps
T989 /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3415595771 Jul 05 04:28:00 PM PDT 24 Jul 05 04:28:06 PM PDT 24 29577383 ps
T87 /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2439773722 Jul 05 04:28:17 PM PDT 24 Jul 05 04:28:32 PM PDT 24 221434337 ps
T88 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3616021313 Jul 05 04:28:24 PM PDT 24 Jul 05 04:28:37 PM PDT 24 18756107 ps
T990 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1865611747 Jul 05 04:28:21 PM PDT 24 Jul 05 04:28:35 PM PDT 24 103804244 ps
T89 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.629279571 Jul 05 04:28:12 PM PDT 24 Jul 05 04:28:25 PM PDT 24 20192710 ps
T991 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1161254787 Jul 05 04:28:16 PM PDT 24 Jul 05 04:28:31 PM PDT 24 55735818 ps
T992 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.353892056 Jul 05 04:29:29 PM PDT 24 Jul 05 04:29:39 PM PDT 24 25455464 ps
T993 /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.4086370560 Jul 05 04:28:30 PM PDT 24 Jul 05 04:28:46 PM PDT 24 1194832208 ps
T994 /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.60691241 Jul 05 04:28:05 PM PDT 24 Jul 05 04:28:14 PM PDT 24 26869711 ps
T995 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3224461758 Jul 05 04:28:07 PM PDT 24 Jul 05 04:28:24 PM PDT 24 93054906 ps
T996 /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1279593399 Jul 05 04:28:15 PM PDT 24 Jul 05 04:28:29 PM PDT 24 28698114 ps
T118 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3334198330 Jul 05 04:28:21 PM PDT 24 Jul 05 04:28:37 PM PDT 24 321591454 ps
T997 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2496196270 Jul 05 04:28:12 PM PDT 24 Jul 05 04:28:29 PM PDT 24 210043265 ps
T998 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2459996011 Jul 05 04:28:05 PM PDT 24 Jul 05 04:28:16 PM PDT 24 247978746 ps
T114 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.4292385944 Jul 05 04:28:20 PM PDT 24 Jul 05 04:28:34 PM PDT 24 213638964 ps
T999 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.489709707 Jul 05 04:28:22 PM PDT 24 Jul 05 04:28:37 PM PDT 24 83651760 ps
T1000 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.59418989 Jul 05 04:28:14 PM PDT 24 Jul 05 04:28:28 PM PDT 24 42564757 ps
T83 /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.4103563045 Jul 05 04:27:59 PM PDT 24 Jul 05 04:28:06 PM PDT 24 426658246 ps
T1001 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.454591661 Jul 05 04:28:27 PM PDT 24 Jul 05 04:28:41 PM PDT 24 44443119 ps
T1002 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3857099611 Jul 05 04:28:07 PM PDT 24 Jul 05 04:28:27 PM PDT 24 66476460 ps
T1003 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2844195340 Jul 05 04:28:13 PM PDT 24 Jul 05 04:28:29 PM PDT 24 29055595 ps
T1004 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2532970757 Jul 05 04:28:01 PM PDT 24 Jul 05 04:28:09 PM PDT 24 236512143 ps
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