SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[sram_ctrl_prim_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[sram_ctrl_regs_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[0]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[1] | 67344863 | 0 | T1 | 361 | T3 | 405103 | T5 | 34816 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 67344645 | 1 | T1 | 361 | T3 | 405103 | T5 | 34816 | ||||
values[1] | 24 | 1 | T50 | 2 | T51 | 1 | T52 | 3 | ||||
values[2] | 4 | 1 | T51 | 1 | T119 | 1 | T120 | 1 | ||||
values[3] | 112 | 1 | T50 | 6 | T51 | 10 | T52 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 67344672 | 1 | T1 | 361 | T3 | 405103 | T5 | 34816 | ||||
values[1] | 14 | 1 | T121 | 1 | T122 | 1 | T119 | 1 | ||||
values[2] | 10 | 1 | T51 | 3 | T103 | 1 | T123 | 1 | ||||
values[3] | 94 | 1 | T50 | 4 | T51 | 8 | T52 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 67344553 | 1 | T1 | 361 | T3 | 405103 | T5 | 34816 | ||||
auto[TlIntgErrCmd] | 119 | 1 | T50 | 10 | T51 | 9 | T52 | 6 | ||||
auto[TlIntgErrData] | 92 | 1 | T50 | 6 | T51 | 4 | T52 | 1 | ||||
auto[TlIntgErrBoth] | 99 | 1 | T50 | 4 | T51 | 7 | T52 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[0] | 486977 | 0 | T1 | 73 | T2 | 9 | T3 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 486767 | 1 | T1 | 73 | T2 | 9 | T3 | 6 | ||||
values[1] | 21 | 1 | T51 | 3 | T52 | 1 | T103 | 1 | ||||
values[2] | 2 | 1 | T50 | 1 | T120 | 1 | - | - | ||||
values[3] | 107 | 1 | T50 | 3 | T51 | 6 | T52 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 486766 | 1 | T1 | 73 | T2 | 9 | T3 | 6 | ||||
values[1] | 28 | 1 | T50 | 2 | T52 | 1 | T103 | 1 | ||||
values[2] | 4 | 1 | T52 | 1 | T121 | 2 | T119 | 1 | ||||
values[3] | 109 | 1 | T50 | 7 | T51 | 9 | T52 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 486667 | 1 | T1 | 73 | T2 | 9 | T3 | 6 | ||||
auto[TlIntgErrCmd] | 99 | 1 | T50 | 6 | T51 | 7 | T52 | 2 | ||||
auto[TlIntgErrData] | 100 | 1 | T50 | 7 | T51 | 8 | T52 | 5 | ||||
auto[TlIntgErrBoth] | 111 | 1 | T50 | 7 | T51 | 5 | T52 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |