Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13853907	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

58695687

1

T1

3364

T3

368352

T5

34816

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36154768	1			T1	1873		T3	202762		T5	17408
values[0x0]	16810320	1			T1	837		T3	97350		T5	8785
values[0x1]	19584506	1			T1	976		T3	104991		T5	8623

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6903536	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

65646058

1

T1

3540

T3

386888

T5

34816

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	274429	1			T1	16		T3	1452		T9	2
valid_sources[0x01]	250312	1			T1	16		T3	1509		T9	8
valid_sources[0x02]	260069	1			T1	11		T3	1493		T6	2
valid_sources[0x03]	266436	1			T1	21		T3	1627		T9	2
valid_sources[0x04]	266584	1			T1	14		T3	1667		T4	7
valid_sources[0x05]	246118	1			T1	17		T3	1608		T6	3
valid_sources[0x06]	265840	1			T1	15		T3	1686		T9	4
valid_sources[0x07]	286368	1			T1	10		T3	1715		T6	3
valid_sources[0x08]	320887	1			T1	7		T3	1489		T9	8
valid_sources[0x09]	320632	1			T1	21		T3	1678		T6	2
valid_sources[0x0a]	265861	1			T1	15		T3	1681		T9	1
valid_sources[0x0b]	246805	1			T1	18		T3	1496		T9	7
valid_sources[0x0c]	288916	1			T1	18		T3	1586		T6	1
valid_sources[0x0d]	277951	1			T1	10		T3	1444		T9	5
valid_sources[0x0e]	301078	1			T1	17		T3	1609		T10	4
valid_sources[0x0f]	317296	1			T1	18		T3	1591		T6	2
valid_sources[0x10]	274978	1			T1	19		T3	1650		T9	3
valid_sources[0x11]	286274	1			T1	13		T3	1600		T4	16
valid_sources[0x12]	280661	1			T1	8		T3	1450		T4	20
valid_sources[0x13]	264753	1			T1	17		T3	1641		T11	912
valid_sources[0x14]	314620	1			T1	12		T3	1596		T6	2
valid_sources[0x15]	238848	1			T1	29		T3	1571		T6	3
valid_sources[0x16]	277537	1			T1	13		T3	1595		T9	1
valid_sources[0x17]	277166	1			T1	25		T3	1601		T4	4
valid_sources[0x18]	252207	1			T1	17		T3	1621		T9	8
valid_sources[0x19]	319936	1			T1	14		T3	1610		T6	2
valid_sources[0x1a]	330842	1			T1	16		T3	1583		T6	1
valid_sources[0x1b]	244443	1			T1	13		T3	1693		T6	3
valid_sources[0x1c]	266071	1			T1	14		T3	1686		T6	3
valid_sources[0x1d]	256994	1			T1	14		T3	1558		T6	3
valid_sources[0x1e]	285802	1			T1	14		T3	1476		T6	2
valid_sources[0x1f]	255722	1			T1	15		T3	1572		T6	2
valid_sources[0x20]	259726	1			T1	15		T3	1597		T6	4
valid_sources[0x21]	362018	1			T1	15		T3	1573		T4	33
valid_sources[0x22]	257469	1			T1	8		T3	1613		T4	6
valid_sources[0x23]	296911	1			T1	9		T3	1576		T6	1
valid_sources[0x24]	296179	1			T1	10		T3	1577		T9	8
valid_sources[0x25]	265759	1			T1	12		T3	1494		T6	3
valid_sources[0x26]	310322	1			T1	16		T3	1566		T4	5
valid_sources[0x27]	260206	1			T1	10		T3	1708		T9	2
valid_sources[0x28]	308453	1			T1	11		T3	1531		T6	2
valid_sources[0x29]	287469	1			T1	7		T3	1538		T4	2
valid_sources[0x2a]	262656	1			T1	13		T3	1561		T6	4
valid_sources[0x2b]	256383	1			T1	19		T3	1612		T9	4
valid_sources[0x2c]	294798	1			T1	15		T3	1627		T4	11
valid_sources[0x2d]	331676	1			T1	9		T3	1652		T6	8
valid_sources[0x2e]	262965	1			T1	14		T3	1663		T6	9
valid_sources[0x2f]	295337	1			T1	21		T3	1654		T9	1
valid_sources[0x30]	273763	1			T1	24		T3	1660		T6	4
valid_sources[0x31]	264362	1			T1	19		T3	1532		T6	2
valid_sources[0x32]	333918	1			T1	14		T3	1608		T6	2
valid_sources[0x33]	322238	1			T1	23		T3	1737		T9	1
valid_sources[0x34]	271492	1			T1	12		T3	1470		T6	2
valid_sources[0x35]	270836	1			T1	3		T3	1472		T6	3
valid_sources[0x36]	302389	1			T1	13		T3	1615		T9	7
valid_sources[0x37]	333701	1			T1	13		T3	1502		T9	3
valid_sources[0x38]	262255	1			T1	14		T3	1566		T6	1
valid_sources[0x39]	268126	1			T1	14		T3	1546		T9	6
valid_sources[0x3a]	277016	1			T1	10		T3	1597		T6	1
valid_sources[0x3b]	260211	1			T1	15		T3	1694		T6	3
valid_sources[0x3c]	254782	1			T1	18		T3	1728		T9	1
valid_sources[0x3d]	281426	1			T1	15		T3	1605		T9	6
valid_sources[0x3e]	274896	1			T1	12		T3	1624		T9	1
valid_sources[0x3f]	287447	1			T1	15		T3	1525		T6	14
valid_sources[0x40]	318889	1			T1	15		T3	1624		T6	3
valid_sources[0x41]	304284	1			T1	13		T3	1472		T6	3
valid_sources[0x42]	318657	1			T1	19		T3	1456		T6	1
valid_sources[0x43]	275882	1			T1	19		T3	1593		T10	4
valid_sources[0x44]	293832	1			T1	15		T3	1461		T6	3
valid_sources[0x45]	267903	1			T1	8		T3	1565		T4	4
valid_sources[0x46]	253791	1			T1	7		T3	1577		T6	1
valid_sources[0x47]	265026	1			T1	10		T3	1544		T6	2
valid_sources[0x48]	245835	1			T1	14		T3	1704		T4	36
valid_sources[0x49]	249988	1			T1	13		T3	1444		T9	4
valid_sources[0x4a]	350570	1			T1	12		T3	1473		T9	1
valid_sources[0x4b]	255240	1			T1	16		T3	1593		T6	1
valid_sources[0x4c]	258981	1			T1	15		T3	1566		T9	4
valid_sources[0x4d]	317002	1			T1	8		T3	1519		T6	1
valid_sources[0x4e]	292064	1			T1	17		T3	1635		T6	2
valid_sources[0x4f]	298804	1			T1	22		T3	1612		T6	1
valid_sources[0x50]	288903	1			T1	19		T3	1563		T9	2
valid_sources[0x51]	285570	1			T1	10		T3	1518		T6	3
valid_sources[0x52]	281727	1			T1	13		T3	1511		T9	5
valid_sources[0x53]	254930	1			T1	19		T3	1484		T6	3
valid_sources[0x54]	327739	1			T1	18		T3	1607		T6	1
valid_sources[0x55]	275432	1			T1	17		T3	1474		T6	8
valid_sources[0x56]	260462	1			T1	14		T3	1503		T6	6
valid_sources[0x57]	262510	1			T1	14		T3	1520		T9	4
valid_sources[0x58]	270990	1			T1	11		T3	1574		T6	2
valid_sources[0x59]	305791	1			T1	13		T3	1566		T9	4
valid_sources[0x5a]	294712	1			T1	13		T3	1671		T9	1
valid_sources[0x5b]	277930	1			T1	10		T3	1665		T6	1
valid_sources[0x5c]	299202	1			T1	11		T3	1456		T9	4
valid_sources[0x5d]	259463	1			T1	14		T3	1802		T9	5
valid_sources[0x5e]	238752	1			T1	15		T3	1623		T6	2
valid_sources[0x5f]	260307	1			T1	15		T3	1546		T4	23
valid_sources[0x60]	247729	1			T1	6		T3	1557		T9	3
valid_sources[0x61]	327864	1			T1	17		T3	1600		T6	5
valid_sources[0x62]	307813	1			T1	6		T3	1595		T6	2
valid_sources[0x63]	257223	1			T1	20		T3	1532		T6	2
valid_sources[0x64]	289628	1			T1	8		T3	1466		T6	2
valid_sources[0x65]	241892	1			T1	15		T3	1705		T6	1
valid_sources[0x66]	339373	1			T1	15		T3	1507		T9	3
valid_sources[0x67]	245023	1			T1	20		T3	1579		T9	1
valid_sources[0x68]	296674	1			T1	21		T3	1559		T6	2
valid_sources[0x69]	267788	1			T1	16		T3	1538		T6	2
valid_sources[0x6a]	261701	1			T1	25		T3	1668		T6	5
valid_sources[0x6b]	263819	1			T1	19		T3	1748		T6	1
valid_sources[0x6c]	259679	1			T1	24		T3	1669		T9	9
valid_sources[0x6d]	250360	1			T1	11		T3	1659		T6	3
valid_sources[0x6e]	251533	1			T1	12		T3	1555		T6	1
valid_sources[0x6f]	249659	1			T1	6		T3	1562		T6	7
valid_sources[0x70]	350745	1			T1	21		T3	1671		T6	3
valid_sources[0x71]	261426	1			T1	12		T3	1557		T6	3
valid_sources[0x72]	315189	1			T1	15		T3	1536		T6	1
valid_sources[0x73]	290539	1			T1	13		T3	1555		T6	1
valid_sources[0x74]	281007	1			T1	13		T3	1557		T4	6
valid_sources[0x75]	259813	1			T1	10		T3	1455		T6	3
valid_sources[0x76]	276124	1			T1	22		T3	1576		T9	5
valid_sources[0x77]	279075	1			T1	16		T3	1631		T6	3
valid_sources[0x78]	295334	1			T1	8		T3	1746		T6	2
valid_sources[0x79]	275653	1			T1	14		T3	1702		T6	3
valid_sources[0x7a]	270079	1			T1	11		T3	1722		T6	1
valid_sources[0x7b]	273516	1			T1	20		T3	1500		T9	6
valid_sources[0x7c]	266049	1			T1	16		T3	1592		T9	2
valid_sources[0x7d]	273702	1			T1	17		T3	1501		T4	7
valid_sources[0x7e]	303207	1			T1	10		T3	1536		T9	6
valid_sources[0x7f]	285637	1			T1	20		T3	1693		T6	1
valid_sources[0x80]	323878	1			T1	16		T3	1565		T6	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29233856

1

T1

1722

T3

184329

T5

17408

values[0x0]

all_enables

biggest_size

14729829

1

T1

789

T3

91835

T5

8785

values[0x1]

all_enables

biggest_size

14732002

1

T1

853

T3

92188

T5

8623

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	38747	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

164293

1

T1

26

T2

1

T5

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	57875	1			T1	35		T6	4		T11	17
values[0x0]	69716	1			T1	23		T2	5		T3	4
values[0x1]	75449	1			T1	15		T2	4		T3	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	28788	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

174252

1

T1

35

T2

2

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1176	1			T18	11		T7	1		T56	2
valid_sources[0x01]	619	1			T18	3		T7	1		T22	1
valid_sources[0x02]	492	1			T3	1		T18	12		T7	1
valid_sources[0x03]	760	1			T3	1		T18	11		T7	1
valid_sources[0x04]	560	1			T18	14		T7	1		T42	9
valid_sources[0x05]	991	1			T18	8		T55	1		T56	1
valid_sources[0x06]	552	1			T18	14		T22	2		T23	2
valid_sources[0x07]	996	1			T18	17		T79	1		T42	3
valid_sources[0x08]	1398	1			T18	9		T56	1		T20	2
valid_sources[0x09]	1117	1			T18	4		T7	3		T56	1
valid_sources[0x0a]	739	1			T18	9		T7	1		T22	1
valid_sources[0x0b]	771	1			T18	13		T21	13		T56	1
valid_sources[0x0c]	1200	1			T18	8		T56	1		T42	9
valid_sources[0x0d]	544	1			T18	8		T22	4		T42	8
valid_sources[0x0e]	999	1			T18	9		T7	1		T42	9
valid_sources[0x0f]	713	1			T18	8		T39	8		T55	1
valid_sources[0x10]	1068	1			T12	1		T18	7		T7	1
valid_sources[0x11]	767	1			T18	10		T7	3		T56	1
valid_sources[0x12]	582	1			T18	5		T7	2		T23	1
valid_sources[0x13]	581	1			T3	1		T41	1		T18	4
valid_sources[0x14]	805	1			T18	10		T7	1		T55	1
valid_sources[0x15]	695	1			T18	10		T7	3		T42	10
valid_sources[0x16]	715	1			T18	4		T56	3		T22	106
valid_sources[0x17]	880	1			T18	8		T56	1		T20	4
valid_sources[0x18]	893	1			T18	11		T22	51		T42	8
valid_sources[0x19]	764	1			T11	1		T18	10		T20	2
valid_sources[0x1a]	640	1			T11	7		T18	8		T22	108
valid_sources[0x1b]	825	1			T18	12		T7	4		T22	1
valid_sources[0x1c]	853	1			T18	11		T22	76		T20	2
valid_sources[0x1d]	1272	1			T18	5		T7	2		T42	5
valid_sources[0x1e]	815	1			T18	4		T7	3		T56	1
valid_sources[0x1f]	494	1			T18	6		T55	1		T20	1
valid_sources[0x20]	683	1			T2	4		T6	2		T18	10
valid_sources[0x21]	937	1			T18	7		T7	2		T56	3
valid_sources[0x22]	921	1			T18	8		T90	1		T42	15
valid_sources[0x23]	717	1			T18	8		T7	2		T56	2
valid_sources[0x24]	1208	1			T18	10		T134	1		T20	5
valid_sources[0x25]	626	1			T18	10		T7	1		T56	2
valid_sources[0x26]	1274	1			T18	9		T7	2		T23	1
valid_sources[0x27]	947	1			T11	2		T18	9		T56	2
valid_sources[0x28]	670	1			T18	15		T22	1		T42	6
valid_sources[0x29]	989	1			T18	8		T7	1		T40	1
valid_sources[0x2a]	1320	1			T18	9		T23	1		T42	9
valid_sources[0x2b]	855	1			T18	12		T22	1		T42	6
valid_sources[0x2c]	794	1			T18	11		T23	7		T20	5
valid_sources[0x2d]	669	1			T18	7		T7	1		T40	1
valid_sources[0x2e]	778	1			T18	5		T7	1		T22	1
valid_sources[0x2f]	690	1			T18	11		T7	1		T42	11
valid_sources[0x30]	760	1			T18	12		T7	2		T22	1
valid_sources[0x31]	916	1			T11	5		T18	4		T7	2
valid_sources[0x32]	922	1			T18	15		T56	1		T23	1
valid_sources[0x33]	678	1			T18	10		T56	1		T20	2
valid_sources[0x34]	752	1			T18	15		T55	2		T42	11
valid_sources[0x35]	995	1			T18	13		T22	1		T23	92
valid_sources[0x36]	838	1			T18	10		T20	1		T42	8
valid_sources[0x37]	540	1			T18	8		T22	4		T23	2
valid_sources[0x38]	881	1			T18	10		T7	1		T23	5
valid_sources[0x39]	701	1			T18	9		T7	1		T22	1
valid_sources[0x3a]	622	1			T18	11		T7	2		T22	95
valid_sources[0x3b]	835	1			T18	8		T23	3		T42	8
valid_sources[0x3c]	693	1			T18	6		T7	1		T22	1
valid_sources[0x3d]	932	1			T18	12		T7	1		T23	3
valid_sources[0x3e]	695	1			T41	1		T18	9		T22	1
valid_sources[0x3f]	698	1			T18	8		T7	1		T23	6
valid_sources[0x40]	878	1			T18	11		T7	1		T23	181
valid_sources[0x41]	796	1			T18	7		T7	1		T22	91
valid_sources[0x42]	864	1			T18	13		T7	1		T56	1
valid_sources[0x43]	950	1			T10	3		T41	1		T18	9
valid_sources[0x44]	919	1			T18	15		T7	1		T42	3
valid_sources[0x45]	621	1			T18	7		T7	1		T23	1
valid_sources[0x46]	652	1			T18	10		T56	1		T42	10
valid_sources[0x47]	890	1			T37	7		T18	6		T42	8
valid_sources[0x48]	953	1			T18	18		T13	10		T7	3
valid_sources[0x49]	649	1			T18	10		T23	1		T20	8
valid_sources[0x4a]	692	1			T18	8		T55	1		T56	2
valid_sources[0x4b]	1137	1			T18	10		T7	1		T8	1
valid_sources[0x4c]	706	1			T18	13		T7	2		T22	3
valid_sources[0x4d]	689	1			T18	5		T56	2		T95	2
valid_sources[0x4e]	716	1			T18	6		T7	1		T56	1
valid_sources[0x4f]	894	1			T18	18		T7	1		T55	1
valid_sources[0x50]	970	1			T18	3		T40	1		T56	1
valid_sources[0x51]	556	1			T11	12		T18	10		T23	22
valid_sources[0x52]	784	1			T11	8		T18	8		T7	1
valid_sources[0x53]	872	1			T18	12		T7	1		T42	12
valid_sources[0x54]	749	1			T18	11		T55	1		T20	1
valid_sources[0x55]	893	1			T18	10		T22	1		T42	7
valid_sources[0x56]	914	1			T18	14		T7	1		T23	1
valid_sources[0x57]	571	1			T18	11		T22	1		T42	9
valid_sources[0x58]	1001	1			T18	8		T7	1		T42	9
valid_sources[0x59]	862	1			T11	4		T18	11		T7	1
valid_sources[0x5a]	756	1			T18	10		T7	2		T22	104
valid_sources[0x5b]	1076	1			T9	1		T18	12		T7	1
valid_sources[0x5c]	666	1			T18	8		T7	1		T42	6
valid_sources[0x5d]	546	1			T18	8		T7	1		T22	2
valid_sources[0x5e]	821	1			T41	1		T18	14		T23	74
valid_sources[0x5f]	904	1			T6	1		T18	13		T56	2
valid_sources[0x60]	836	1			T18	17		T7	3		T42	8
valid_sources[0x61]	753	1			T18	12		T56	1		T23	17
valid_sources[0x62]	620	1			T18	10		T7	1		T23	9
valid_sources[0x63]	1413	1			T11	1		T18	8		T7	2
valid_sources[0x64]	549	1			T18	11		T7	2		T20	2
valid_sources[0x65]	655	1			T18	10		T56	1		T23	4
valid_sources[0x66]	721	1			T18	9		T7	1		T42	10
valid_sources[0x67]	559	1			T41	1		T18	13		T55	2
valid_sources[0x68]	1142	1			T18	9		T22	2		T23	1
valid_sources[0x69]	647	1			T18	6		T7	1		T56	2
valid_sources[0x6a]	821	1			T18	8		T7	1		T22	119
valid_sources[0x6b]	434	1			T18	11		T7	1		T40	1
valid_sources[0x6c]	773	1			T18	10		T40	1		T56	1
valid_sources[0x6d]	533	1			T18	8		T55	1		T22	2
valid_sources[0x6e]	1059	1			T18	9		T7	2		T56	1
valid_sources[0x6f]	974	1			T18	6		T8	1		T90	1
valid_sources[0x70]	827	1			T11	3		T18	9		T7	2
valid_sources[0x71]	991	1			T18	17		T39	2		T7	1
valid_sources[0x72]	620	1			T18	14		T20	3		T42	14
valid_sources[0x73]	636	1			T18	5		T7	1		T20	3
valid_sources[0x74]	1002	1			T18	18		T7	3		T42	3
valid_sources[0x75]	695	1			T18	11		T55	2		T42	11
valid_sources[0x76]	629	1			T18	5		T22	6		T20	5
valid_sources[0x77]	708	1			T41	2		T18	7		T56	1
valid_sources[0x78]	569	1			T41	1		T18	12		T7	1
valid_sources[0x79]	581	1			T18	12		T44	7		T56	2
valid_sources[0x7a]	743	1			T41	1		T18	10		T7	1
valid_sources[0x7b]	901	1			T18	7		T22	1		T42	4
valid_sources[0x7c]	960	1			T18	12		T44	2		T56	2
valid_sources[0x7d]	953	1			T18	7		T42	11		T136	2
valid_sources[0x7e]	732	1			T18	8		T55	1		T20	10
valid_sources[0x7f]	858	1			T18	14		T61	1		T40	1
valid_sources[0x80]	671	1			T18	6		T7	1		T56	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

44173

1

T1

14

T6

2

T11

10

values[0x0]

all_enables

biggest_size

61010

1

T1

11

T2

1

T4

1

values[0x1]

all_enables

biggest_size

59110

1

T1

1

T5

4

T6

1