Summary for Variable cp_num_num_enable_bytes
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_num_num_enable_bytes
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
partial |
13601545 |
1 |
|
|
T1 |
28 |
|
T3 |
36751 |
|
T4 |
81 |
full_word |
53743318 |
1 |
|
|
T1 |
333 |
|
T3 |
368352 |
|
T5 |
34816 |
Summary for Variable cp_tl_intg_err_type
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
4 |
0 |
4 |
100.00 |
Automatically Generated Bins for cp_tl_intg_err_type
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
67344553 |
1 |
|
|
T1 |
361 |
|
T3 |
405103 |
|
T5 |
34816 |
auto[TlIntgErrCmd] |
119 |
1 |
|
|
T50 |
10 |
|
T51 |
9 |
|
T52 |
6 |
auto[TlIntgErrData] |
92 |
1 |
|
|
T50 |
6 |
|
T51 |
4 |
|
T52 |
1 |
auto[TlIntgErrBoth] |
99 |
1 |
|
|
T50 |
4 |
|
T51 |
7 |
|
T52 |
3 |
Summary for Variable cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_write
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
30827499 |
1 |
|
|
T1 |
174 |
|
T3 |
202762 |
|
T5 |
17408 |
auto[1] |
36517364 |
1 |
|
|
T1 |
187 |
|
T3 |
202341 |
|
T5 |
17408 |
Summary for Cross cr_all
Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
16 |
0 |
16 |
100.00 |
|
Automatically Generated Cross Bins for cr_all
Bins
cp_tl_intg_err_type | cp_num_num_enable_bytes | cp_write | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
partial |
auto[0] |
6481649 |
1 |
|
|
T1 |
13 |
|
T3 |
18433 |
|
T4 |
43 |
auto[TlIntgErrNone] |
partial |
auto[1] |
7119621 |
1 |
|
|
T1 |
15 |
|
T3 |
18318 |
|
T4 |
38 |
auto[TlIntgErrNone] |
full_word |
auto[0] |
24345714 |
1 |
|
|
T1 |
161 |
|
T3 |
184329 |
|
T5 |
17408 |
auto[TlIntgErrNone] |
full_word |
auto[1] |
29397569 |
1 |
|
|
T1 |
172 |
|
T3 |
184023 |
|
T5 |
17408 |
auto[TlIntgErrCmd] |
partial |
auto[0] |
45 |
1 |
|
|
T50 |
3 |
|
T51 |
2 |
|
T52 |
1 |
auto[TlIntgErrCmd] |
partial |
auto[1] |
61 |
1 |
|
|
T50 |
4 |
|
T51 |
7 |
|
T52 |
5 |
auto[TlIntgErrCmd] |
full_word |
auto[0] |
6 |
1 |
|
|
T50 |
1 |
|
T103 |
2 |
|
T122 |
1 |
auto[TlIntgErrCmd] |
full_word |
auto[1] |
7 |
1 |
|
|
T50 |
2 |
|
T103 |
1 |
|
T124 |
1 |
auto[TlIntgErrData] |
partial |
auto[0] |
36 |
1 |
|
|
T50 |
3 |
|
T51 |
1 |
|
T52 |
1 |
auto[TlIntgErrData] |
partial |
auto[1] |
46 |
1 |
|
|
T50 |
2 |
|
T51 |
3 |
|
T103 |
3 |
auto[TlIntgErrData] |
full_word |
auto[0] |
5 |
1 |
|
|
T50 |
1 |
|
T103 |
2 |
|
T123 |
1 |
auto[TlIntgErrData] |
full_word |
auto[1] |
5 |
1 |
|
|
T125 |
1 |
|
T124 |
1 |
|
T126 |
1 |
auto[TlIntgErrBoth] |
partial |
auto[0] |
40 |
1 |
|
|
T50 |
1 |
|
T51 |
4 |
|
T52 |
1 |
auto[TlIntgErrBoth] |
partial |
auto[1] |
47 |
1 |
|
|
T50 |
3 |
|
T51 |
2 |
|
T52 |
2 |
auto[TlIntgErrBoth] |
full_word |
auto[0] |
4 |
1 |
|
|
T51 |
1 |
|
T123 |
2 |
|
T127 |
1 |
auto[TlIntgErrBoth] |
full_word |
auto[1] |
8 |
1 |
|
|
T120 |
1 |
|
T128 |
3 |
|
T125 |
1 |