Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	732480	1			T1	1		T6	1		T9	20
auto[1]	10458433	1			T1	12		T3	168717		T4	234
auto[2]	621295	1			T1	2		T9	12		T18	18
auto[3]	10363243	1			T1	8		T3	168387		T4	212

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14689022	1			T1	16		T3	281455		T4	308
auto[1]	2078792	1			T1	3		T3	26512		T4	57
auto[2]	2100413	1			T1	4		T3	26558		T4	69
auto[3]	3307224	1			T3	2579		T4	12		T9	215

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8992608

1

T1

23

T3

40

T4

445

auto[1]

13182843

1

T3

337064

T4

1

T11

9

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	327894	1			T1	1		T6	1		T18	16
auto[0]	auto[0]	auto[1]	34229	1			T18	1		T21	70		T60	30
auto[0]	auto[0]	auto[2]	34131	1			T21	62		T60	28		T7	65
auto[0]	auto[0]	auto[3]	11579	1			T9	20		T21	9		T60	109
auto[0]	auto[1]	auto[0]	3378966	1			T1	10		T3	16		T4	162
auto[0]	auto[1]	auto[1]	352998	1			T1	2		T4	28		T11	444
auto[0]	auto[1]	auto[2]	338093	1			T3	1		T4	39		T9	3
auto[0]	auto[1]	auto[3]	63383	1			T4	4		T9	62		T11	31
auto[0]	auto[2]	auto[0]	289333	1			T18	14		T21	652		T55	174
auto[0]	auto[2]	auto[1]	30020	1			T21	60		T55	18		T56	215
auto[0]	auto[2]	auto[2]	30761	1			T1	2		T9	1		T18	4
auto[0]	auto[2]	auto[3]	9137	1			T9	11		T21	4		T60	94
auto[0]	auto[3]	auto[0]	3344066	1			T1	5		T3	17		T4	145
auto[0]	auto[3]	auto[1]	333962	1			T1	1		T3	3		T4	29
auto[0]	auto[3]	auto[2]	351180	1			T1	2		T3	3		T4	30
auto[0]	auto[3]	auto[3]	62876	1			T4	8		T9	122		T11	48
auto[1]	auto[0]	auto[0]	11190	1			T21	1		T56	2		T62	2
auto[1]	auto[0]	auto[1]	48325	1			T21	2		T62	1		T90	878
auto[1]	auto[0]	auto[2]	47955	1			T90	870		T92	596		T132	1
auto[1]	auto[0]	auto[3]	217177	1			T78	3		T90	3972		T92	2759
auto[1]	auto[1]	auto[0]	3665717	1			T3	140807		T4	1		T11	4
auto[1]	auto[1]	auto[1]	640061	1			T3	12585		T39	3		T40	4
auto[1]	auto[1]	auto[2]	625273	1			T3	13990		T39	4		T7	1
auto[1]	auto[1]	auto[3]	1393942	1			T3	1318		T11	1		T60	1
auto[1]	auto[2]	auto[0]	7067	1			T21	1		T55	1		T56	1
auto[1]	auto[2]	auto[1]	31069	1			T56	1		T133	1		T29	1
auto[1]	auto[2]	auto[2]	40937	1			T7	1		T90	802		T29	2
auto[1]	auto[2]	auto[3]	182971	1			T134	1		T90	3508		T92	2381
auto[1]	auto[3]	auto[0]	3664789	1			T3	140615		T11	2		T37	6
auto[1]	auto[3]	auto[1]	608128	1			T3	13924		T11	2		T39	4
auto[1]	auto[3]	auto[2]	632083	1			T3	12564		T39	3		T7	3
auto[1]	auto[3]	auto[3]	1366159	1			T3	1261		T61	1		T134	1