Unified Coverage Report :: Module :: prim_sync_reqack_data

Module : prim_sync_reqack_data

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_sync_reqack_data	100.00	100.00					100.00

---

Module Instance : tb.dut.u_prim_sync_reqack_data

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_sync_reqack	100.00	100.00	100.00			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_sync_reqack_data

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	153	0	0
CONT_ASSIGN	156	0	0
ALWAYS	159	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
153		unreachable
156		unreachable
159		unreachable
160		unreachable
162		unreachable

---

Assert Coverage for Module : prim_sync_reqack_data

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	305371424	8733	0	0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	305371424	8732	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA

Name	Attempts	Real Successes	Failures	Incomplete
Total	305371424	8733	0	0
T1	63480	38	0	0
T2	1291	0	0	0
T3	487200	6	0	0
T4	3676	2	0	0
T5	72308	17	0	0
T6	7295	4	0	0
T9	8689	1	0	0
T10	5370	1	0	0
T11	352538	3	0	0
T12	9336	0	0	0
T37	0	7	0	0
T41	0	24	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB

Name	Attempts	Real Successes	Failures	Incomplete
Total	305371424	8732	0	0
T1	63480	38	0	0
T2	1291	0	0	0
T3	487200	6	0	0
T4	3676	2	0	0
T5	72308	17	0	0
T6	7295	4	0	0
T9	8689	1	0	0
T10	5370	1	0	0
T11	352538	3	0	0
T12	9336	0	0	0
T37	0	7	0	0
T41	0	24	0	0