Module Definition
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Module : sram_ctrl_regs_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.sram_ctrl_regs_csr_assert 100.00 100.00



Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.90 100.00 88.89 100.00 100.00 70.59 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 306694299 255627 0 0
ctrl_regwen_rd_A 306694299 3278 0 0
exec_rd_A 306694299 3010 0 0
exec_regwen_rd_A 306694299 3429 0 0
readback_rd_A 306694299 1478 0 0
readback_regwen_rd_A 306694299 1113 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 306694299 255627 0 0
T7 556674 0 0 0
T13 1318 0 0 0
T18 133239 3865 0 0
T21 610361 0 0 0
T22 0 4613 0 0
T23 0 3936 0 0
T38 10142 0 0 0
T39 117345 0 0 0
T40 209250 0 0 0
T42 0 2746 0 0
T43 0 3591 0 0
T46 14462 0 0 0
T47 0 16115 0 0
T49 0 6374 0 0
T57 0 3842 0 0
T58 0 1463 0 0
T59 0 5519 0 0
T60 43195 0 0 0
T61 4060 0 0 0

ctrl_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 306694299 3278 0 0
T52 0 59 0 0
T71 0 19 0 0
T96 311873 352 0 0
T97 0 181 0 0
T98 0 49 0 0
T99 0 85 0 0
T100 0 86 0 0
T101 0 413 0 0
T102 0 111 0 0
T103 0 87 0 0
T104 279368 0 0 0
T105 122879 0 0 0
T106 249413 0 0 0
T107 174610 0 0 0
T108 299550 0 0 0
T109 213503 0 0 0
T110 8567 0 0 0
T111 193850 0 0 0
T112 8289 0 0 0

exec_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 306694299 3010 0 0
T52 0 48 0 0
T71 0 13 0 0
T96 311873 269 0 0
T97 0 142 0 0
T98 0 91 0 0
T99 0 84 0 0
T100 0 119 0 0
T101 0 306 0 0
T102 0 144 0 0
T104 279368 0 0 0
T105 122879 0 0 0
T106 249413 0 0 0
T107 174610 0 0 0
T108 299550 0 0 0
T109 213503 0 0 0
T110 8567 0 0 0
T111 193850 0 0 0
T112 8289 0 0 0
T113 0 1 0 0

exec_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 306694299 3429 0 0
T52 0 35 0 0
T71 0 6 0 0
T96 311873 387 0 0
T97 0 155 0 0
T98 0 84 0 0
T99 0 67 0 0
T100 0 158 0 0
T101 0 406 0 0
T102 0 166 0 0
T104 279368 0 0 0
T105 122879 0 0 0
T106 249413 0 0 0
T107 174610 0 0 0
T108 299550 0 0 0
T109 213503 0 0 0
T110 8567 0 0 0
T111 193850 0 0 0
T112 8289 0 0 0
T113 0 5 0 0

readback_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 306694299 1478 0 0
T96 311873 388 0 0
T97 0 190 0 0
T98 0 53 0 0
T99 0 94 0 0
T100 0 50 0 0
T101 0 359 0 0
T102 0 110 0 0
T104 279368 0 0 0
T105 122879 0 0 0
T106 249413 0 0 0
T107 174610 0 0 0
T108 299550 0 0 0
T109 213503 0 0 0
T110 8567 0 0 0
T111 193850 0 0 0
T112 8289 0 0 0
T114 0 46 0 0
T115 0 44 0 0
T116 0 14 0 0

readback_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 306694299 1113 0 0
T96 311873 202 0 0
T97 0 118 0 0
T98 0 52 0 0
T99 0 35 0 0
T100 0 107 0 0
T101 0 327 0 0
T102 0 70 0 0
T104 279368 0 0 0
T105 122879 0 0 0
T106 249413 0 0 0
T107 174610 0 0 0
T108 299550 0 0 0
T109 213503 0 0 0
T110 8567 0 0 0
T111 193850 0 0 0
T112 8289 0 0 0
T114 0 48 0 0
T115 0 44 0 0
T116 0 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%