SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.90 | 100.00 | 88.89 | 100.00 | 100.00 | 70.59 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
89.00 | 100.00 | 100.00 | 100.00 | 95.00 | 50.00 | u_tlul_lc_gate |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 2 | 2 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1786 | 1786 | 0 | 0 |
OutputsKnown_A | 610742848 | 610508148 | 0 | 0 |
gen_flops.OutputDelay_A | 305371424 | 305241393 | 0 | 2679 |
gen_no_flops.OutputDelay_A | 305371424 | 305254074 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1786 | 1786 | 0 | 0 |
T1 | 2 | 2 | 0 | 0 |
T2 | 2 | 2 | 0 | 0 |
T3 | 2 | 2 | 0 | 0 |
T4 | 2 | 2 | 0 | 0 |
T5 | 2 | 2 | 0 | 0 |
T6 | 2 | 2 | 0 | 0 |
T9 | 2 | 2 | 0 | 0 |
T10 | 2 | 2 | 0 | 0 |
T11 | 2 | 2 | 0 | 0 |
T12 | 2 | 2 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 610742848 | 610508148 | 0 | 0 |
T1 | 126960 | 126464 | 0 | 0 |
T2 | 2582 | 2440 | 0 | 0 |
T3 | 974400 | 974252 | 0 | 0 |
T4 | 7352 | 7232 | 0 | 0 |
T5 | 144616 | 144464 | 0 | 0 |
T6 | 14590 | 14406 | 0 | 0 |
T9 | 17378 | 17234 | 0 | 0 |
T10 | 10740 | 10584 | 0 | 0 |
T11 | 705076 | 704900 | 0 | 0 |
T12 | 18672 | 18528 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 305371424 | 305241393 | 0 | 2679 |
T1 | 63480 | 63097 | 0 | 3 |
T2 | 1291 | 1217 | 0 | 3 |
T3 | 487200 | 487123 | 0 | 3 |
T4 | 3676 | 3613 | 0 | 3 |
T5 | 72308 | 72229 | 0 | 3 |
T6 | 7295 | 7184 | 0 | 3 |
T9 | 8689 | 8614 | 0 | 3 |
T10 | 5370 | 5289 | 0 | 3 |
T11 | 352538 | 352447 | 0 | 3 |
T12 | 9336 | 9261 | 0 | 3 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 305371424 | 305254074 | 0 | 0 |
T1 | 63480 | 63232 | 0 | 0 |
T2 | 1291 | 1220 | 0 | 0 |
T3 | 487200 | 487126 | 0 | 0 |
T4 | 3676 | 3616 | 0 | 0 |
T5 | 72308 | 72232 | 0 | 0 |
T6 | 7295 | 7203 | 0 | 0 |
T9 | 8689 | 8617 | 0 | 0 |
T10 | 5370 | 5292 | 0 | 0 |
T11 | 352538 | 352450 | 0 | 0 |
T12 | 9336 | 9264 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 893 | 893 | 0 | 0 |
OutputsKnown_A | 305371424 | 305254074 | 0 | 0 |
gen_flops.OutputDelay_A | 305371424 | 305241393 | 0 | 2679 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 893 | 893 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 305371424 | 305254074 | 0 | 0 |
T1 | 63480 | 63232 | 0 | 0 |
T2 | 1291 | 1220 | 0 | 0 |
T3 | 487200 | 487126 | 0 | 0 |
T4 | 3676 | 3616 | 0 | 0 |
T5 | 72308 | 72232 | 0 | 0 |
T6 | 7295 | 7203 | 0 | 0 |
T9 | 8689 | 8617 | 0 | 0 |
T10 | 5370 | 5292 | 0 | 0 |
T11 | 352538 | 352450 | 0 | 0 |
T12 | 9336 | 9264 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 305371424 | 305241393 | 0 | 2679 |
T1 | 63480 | 63097 | 0 | 3 |
T2 | 1291 | 1217 | 0 | 3 |
T3 | 487200 | 487123 | 0 | 3 |
T4 | 3676 | 3613 | 0 | 3 |
T5 | 72308 | 72229 | 0 | 3 |
T6 | 7295 | 7184 | 0 | 3 |
T9 | 8689 | 8614 | 0 | 3 |
T10 | 5370 | 5289 | 0 | 3 |
T11 | 352538 | 352447 | 0 | 3 |
T12 | 9336 | 9261 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 893 | 893 | 0 | 0 |
OutputsKnown_A | 305371424 | 305254074 | 0 | 0 |
gen_no_flops.OutputDelay_A | 305371424 | 305254074 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 893 | 893 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 305371424 | 305254074 | 0 | 0 |
T1 | 63480 | 63232 | 0 | 0 |
T2 | 1291 | 1220 | 0 | 0 |
T3 | 487200 | 487126 | 0 | 0 |
T4 | 3676 | 3616 | 0 | 0 |
T5 | 72308 | 72232 | 0 | 0 |
T6 | 7295 | 7203 | 0 | 0 |
T9 | 8689 | 8617 | 0 | 0 |
T10 | 5370 | 5292 | 0 | 0 |
T11 | 352538 | 352450 | 0 | 0 |
T12 | 9336 | 9264 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 305371424 | 305254074 | 0 | 0 |
T1 | 63480 | 63232 | 0 | 0 |
T2 | 1291 | 1220 | 0 | 0 |
T3 | 487200 | 487126 | 0 | 0 |
T4 | 3676 | 3616 | 0 | 0 |
T5 | 72308 | 72232 | 0 | 0 |
T6 | 7295 | 7203 | 0 | 0 |
T9 | 8689 | 8617 | 0 | 0 |
T10 | 5370 | 5292 | 0 | 0 |
T11 | 352538 | 352450 | 0 | 0 |
T12 | 9336 | 9264 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |