Line Coverage for Module :
tlul_sram_byte
| Line No. | Total | Covered | Percent |
TOTAL | | 145 | 144 | 99.31 |
ALWAYS | 105 | 3 | 3 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
CONT_ASSIGN | 142 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
ALWAYS | 239 | 95 | 94 | 98.95 |
CONT_ASSIGN | 506 | 1 | 1 | 100.00 |
CONT_ASSIGN | 517 | 1 | 1 | 100.00 |
ALWAYS | 542 | 2 | 2 | 100.00 |
ALWAYS | 553 | 0 | 0 | |
ALWAYS | 553 | 2 | 2 | 100.00 |
ALWAYS | 572 | 2 | 2 | 100.00 |
ALWAYS | 579 | 22 | 22 | 100.00 |
CONT_ASSIGN | 633 | 1 | 1 | 100.00 |
ALWAYS | 658 | 4 | 4 | 100.00 |
CONT_ASSIGN | 676 | 1 | 1 | 100.00 |
CONT_ASSIGN | 699 | 1 | 1 | 100.00 |
CONT_ASSIGN | 716 | 1 | 1 | 100.00 |
CONT_ASSIGN | 717 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
105 |
1 |
1 |
106 |
1 |
1 |
108 |
1 |
1 |
138 |
1 |
1 |
139 |
1 |
1 |
140 |
1 |
1 |
141 |
1 |
1 |
142 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
156 |
1 |
1 |
239 |
1 |
1 |
240 |
1 |
1 |
241 |
1 |
1 |
242 |
1 |
1 |
243 |
1 |
1 |
244 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
247 |
1 |
1 |
248 |
1 |
1 |
249 |
1 |
1 |
250 |
1 |
1 |
251 |
1 |
1 |
252 |
1 |
1 |
253 |
1 |
1 |
255 |
1 |
1 |
257 |
1 |
1 |
262 |
1 |
1 |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
0 |
1 |
|
|
|
MISSING_ELSE |
|
|
|
MISSING_ELSE |
271 |
1 |
1 |
272 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
|
|
|
MISSING_ELSE |
276 |
1 |
1 |
280 |
1 |
1 |
281 |
1 |
1 |
|
|
|
MISSING_ELSE |
284 |
1 |
1 |
287 |
1 |
1 |
|
|
|
MISSING_ELSE |
295 |
1 |
1 |
296 |
1 |
1 |
297 |
1 |
1 |
298 |
1 |
1 |
299 |
1 |
1 |
300 |
1 |
1 |
|
|
|
==> MISSING_ELSE |
|
|
|
MISSING_ELSE |
306 |
1 |
1 |
307 |
1 |
1 |
309 |
1 |
1 |
310 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
313 |
1 |
1 |
|
|
|
==> MISSING_ELSE |
320 |
1 |
1 |
322 |
|
unreachable |
|
|
|
MISSING_ELSE |
326 |
1 |
1 |
330 |
1 |
1 |
331 |
1 |
1 |
334 |
1 |
1 |
335 |
1 |
1 |
336 |
1 |
1 |
337 |
1 |
1 |
340 |
1 |
1 |
343 |
1 |
1 |
|
|
|
MISSING_ELSE |
350 |
1 |
1 |
352 |
|
unreachable |
|
|
|
MISSING_ELSE |
355 |
1 |
1 |
357 |
1 |
1 |
359 |
1 |
1 |
365 |
1 |
1 |
367 |
|
unreachable |
|
|
|
MISSING_ELSE |
371 |
1 |
1 |
373 |
1 |
1 |
375 |
1 |
1 |
378 |
1 |
1 |
|
|
|
MISSING_ELSE |
385 |
1 |
1 |
387 |
|
unreachable |
|
|
|
MISSING_ELSE |
392 |
1 |
1 |
395 |
1 |
1 |
398 |
1 |
1 |
400 |
1 |
1 |
403 |
1 |
1 |
409 |
1 |
1 |
|
|
|
==> MISSING_ELSE |
417 |
1 |
1 |
419 |
|
unreachable |
|
|
|
MISSING_ELSE |
422 |
1 |
1 |
424 |
1 |
1 |
426 |
1 |
1 |
430 |
1 |
1 |
432 |
|
unreachable |
|
|
|
MISSING_ELSE |
435 |
1 |
1 |
438 |
1 |
1 |
440 |
1 |
1 |
443 |
1 |
1 |
|
|
|
MISSING_ELSE |
448 |
1 |
1 |
450 |
|
unreachable |
|
|
|
MISSING_ELSE |
455 |
1 |
1 |
459 |
1 |
1 |
460 |
1 |
1 |
462 |
1 |
1 |
463 |
1 |
1 |
465 |
1 |
1 |
466 |
1 |
1 |
467 |
1 |
1 |
470 |
1 |
1 |
|
|
|
MISSING_ELSE |
476 |
1 |
1 |
478 |
|
unreachable |
|
|
|
MISSING_ELSE |
481 |
1 |
1 |
483 |
1 |
1 |
486 |
1 |
1 |
488 |
1 |
1 |
489 |
1 |
1 |
490 |
1 |
1 |
|
|
|
MISSING_ELSE |
506 |
1 |
1 |
517 |
1 |
1 |
542 |
1 |
1 |
543 |
1 |
1 |
|
|
|
MISSING_ELSE |
553 |
1 |
1 |
554 |
1 |
1 |
572 |
1 |
1 |
573 |
1 |
1 |
579 |
1 |
1 |
581 |
1 |
1 |
590 |
1 |
1 |
591 |
1 |
1 |
593 |
1 |
1 |
596 |
1 |
1 |
598 |
1 |
1 |
602 |
1 |
1 |
603 |
1 |
1 |
605 |
1 |
1 |
606 |
1 |
1 |
607 |
1 |
1 |
608 |
1 |
1 |
610 |
1 |
1 |
612 |
1 |
1 |
614 |
1 |
1 |
617 |
1 |
1 |
618 |
1 |
1 |
620 |
1 |
1 |
621 |
1 |
1 |
|
|
|
MISSING_ELSE |
623 |
1 |
1 |
626 |
1 |
1 |
|
|
|
MISSING_ELSE |
633 |
1 |
1 |
658 |
1 |
1 |
661 |
1 |
1 |
665 |
1 |
1 |
670 |
1 |
1 |
676 |
1 |
1 |
699 |
1 |
1 |
716 |
1 |
1 |
717 |
1 |
1 |
Cond Coverage for Module :
tlul_sram_byte
| Total | Covered | Percent |
Conditions | 101 | 94 | 93.07 |
Logical | 101 | 94 | 93.07 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 138
EXPRESSION (tl_i.a_valid & tl_o.a_ready)
------1----- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T5 |
LINE 139
EXPRESSION (tl_o.d_valid & tl_i.d_ready)
------1----- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T4,T6 |
1 | 1 | Covered | T1,T3,T5 |
LINE 140
EXPRESSION (tl_sram_o.a_valid & tl_sram_i.a_ready)
--------1-------- --------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T6,T9 |
1 | 1 | Covered | T1,T3,T5 |
LINE 141
EXPRESSION (tl_sram_i.d_valid & tl_sram_o.d_ready)
--------1-------- --------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T4,T6 |
1 | 1 | Covered | T1,T3,T5 |
LINE 142
EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData))
---------------1-------------- ----------------2----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T5 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
LINE 142
SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 142
SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
----------------1----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T5 |
LINE 144
EXPRESSION (gen_integ_handling.byte_wr_txn & gen_integ_handling.a_ack & ((~error_i)))
---------------1-------------- ------------2----------- ------3-----
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T5 |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Covered | T11,T18,T21 |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 145
EXPRESSION (tl_i.a_valid & ((~&tl_i.a_mask)) & gen_integ_handling.wr_txn)
------1----- --------2-------- ------------3------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T3,T5 |
1 | 1 | 0 | Covered | T1,T3,T4 |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 156
EXPRESSION (gen_integ_handling.rdback_data_exp_q == tl_sram_i.d_data)
-----------------------------1----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T5,T4 |
LINE 266
EXPRESSION (((!gen_integ_handling.rdback_chk_ok)) && ((!error_i)))
------------------1------------------ ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T10,T12,T18 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 281
EXPRESSION (gen_integ_handling.wr_txn ? StWrReadBackInit : StRdReadBack)
------------1------------
-1- | Status | Tests |
0 | Covered | T10,T12,T18 |
1 | Covered | T10,T12,T18 |
LINE 297
EXPRESSION (gen_integ_handling.pending_txn_cnt == 2'(1))
----------------------1----------------------
-1- | Status | Tests |
0 | Covered | T1,T9,T18 |
1 | Covered | T1,T3,T4 |
LINE 330
EXPRESSION (gen_integ_handling.pending_txn_cnt == 2'(1))
----------------------1----------------------
-1- | Status | Tests |
0 | Covered | T18,T42,T43 |
1 | Covered | T10,T12,T18 |
LINE 395
EXPRESSION (gen_integ_handling.pending_txn_cnt == 2'(1))
----------------------1----------------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T10,T18,T38 |
LINE 459
EXPRESSION (gen_integ_handling.pending_txn_cnt == 2'(1))
----------------------1----------------------
-1- | Status | Tests |
0 | Covered | T18,T42,T43 |
1 | Covered | T10,T12,T18 |
LINE 517
EXPRESSION (gen_integ_handling.hold_tx_data | gen_integ_handling.byte_req_ack)
---------------1--------------- ---------------2---------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T10,T12,T18 |
LINE 542
EXPRESSION (gen_integ_handling.sram_d_ack && gen_integ_handling.rd_wait)
--------------1-------------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T1,T3,T4 |
LINE 554
EXPRESSION (gen_integ_handling.held_data.a_mask[i] ? gen_integ_handling.held_data.a_data[(i * 8)+:8] : gen_integ_handling.rsp_data[(i * 8)+:8])
-------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T3,T4 |
1 | Covered | T1,T3,T4 |
LINE 581
EXPRESSION (tl_i.d_ready | gen_integ_handling.rd_wait | gen_integ_handling.rdback_wait)
------1----- -------------2------------ ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T18,T38,T44 |
0 | 1 | 0 | Covered | T1,T4,T6 |
1 | 0 | 0 | Covered | T1,T2,T3 |
LINE 590
EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase | gen_integ_handling.rdback_phase_wrreadback)
-------------1------------- ---------------2--------------- ---------------------3--------------------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T10,T18,T38 |
0 | 1 | 0 | Covered | T10,T12,T18 |
1 | 0 | 0 | Covered | T1,T3,T4 |
LINE 593
EXPRESSION (gen_integ_handling.wr_phase ? PutFullData : Get)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T10,T12,T18 |
1 | Covered | T1,T3,T4 |
LINE 596
EXPRESSION
Number Term
1 (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback) ? (2'(gen_integ_handling.AccessSize)) : gen_integ_handling.held_data.a_size)
-1- | Status | Tests |
0 | Covered | T10,T12,T18 |
1 | Covered | T1,T3,T4 |
LINE 596
SUB-EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)
-------------1------------- ---------------------2--------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T10,T12,T18 |
0 | 1 | Covered | T10,T18,T38 |
1 | 0 | Covered | T1,T3,T4 |
LINE 598
EXPRESSION ((gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback) ? ('{(*adjust*)default:'1}) : gen_integ_handling.held_data.a_mask)
-------------------------------------1------------------------------------
-1- | Status | Tests |
0 | Covered | T10,T12,T18 |
1 | Covered | T1,T3,T4 |
LINE 598
SUB-EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)
-------------1------------- ---------------------2--------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T10,T12,T18 |
0 | 1 | Covered | T10,T18,T38 |
1 | 0 | Covered | T1,T3,T4 |
LINE 603
EXPRESSION
Number Term
1 (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback) ? '0 : gen_integ_handling.held_data.a_address[(gen_integ_handling.AccessSize - 1):0])
-1- | Status | Tests |
0 | Covered | T10,T12,T18 |
1 | Covered | T1,T3,T4 |
LINE 603
SUB-EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)
-------------1------------- ---------------------2--------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T10,T12,T18 |
0 | 1 | Covered | T10,T18,T38 |
1 | 0 | Covered | T1,T3,T4 |
LINE 607
EXPRESSION (gen_integ_handling.wr_phase ? gen_integ_handling.combined_data : '0)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T10,T12,T18 |
1 | Covered | T1,T3,T4 |
LINE 608
EXPRESSION (gen_integ_handling.wr_phase ? gen_integ_handling.combined_user : '0)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T10,T12,T18 |
1 | Covered | T1,T3,T4 |
LINE 614
EXPRESSION (((!error_i)) || gen_integ_handling.stall_host)
------1----- --------------2--------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T11,T18,T21 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
LINE 620
EXPRESSION (tl_i.a_valid & ((~gen_integ_handling.stall_host)))
------1----- -----------------2----------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 633
EXPRESSION (error_i & ((~gen_integ_handling.stall_host)))
---1--- -----------------2----------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T2,T3 |
LINE 661
EXPRESSION (tl_sram_i.a_ready & ((~gen_integ_handling.stall_host)) & gen_integ_handling.fifo_rdy & gen_integ_handling.size_fifo_rdy)
--------1-------- -----------------2---------------- -------------3------------- ----------------4---------------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T3,T5 |
1 | 0 | 1 | 1 | Covered | T10,T18,T38 |
1 | 1 | 0 | 1 | Not Covered | |
1 | 1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 665
EXPRESSION (tl_sram_i.d_valid & ((~gen_integ_handling.rd_wait)) & ((~gen_integ_handling.rdback_wait)))
--------1-------- ---------------2--------------- -----------------3-----------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Covered | T10,T12,T18 |
1 | 1 | 1 | Covered | T1,T3,T5 |
LINE 699
EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase | gen_integ_handling.rdback_phase_wrreadback)
-------------1------------- ---------------2--------------- ---------------------3--------------------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T10,T18,T38 |
0 | 1 | 0 | Covered | T10,T12,T18 |
1 | 0 | 0 | Covered | T1,T3,T4 |
FSM Coverage for Module :
tlul_sram_byte
Summary for FSM :: gen_integ_handling.state_q
| Total | Covered | Percent | |
States |
11 |
11 |
100.00 |
(Not included in score) |
Transitions |
17 |
17 |
100.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: gen_integ_handling.state_q
states | Line No. | Covered | Tests |
StByteWrReadBack |
403 |
Covered |
T10,T18,T38 |
StByteWrReadBackDWait |
409 |
Covered |
T18,T38,T45 |
StByteWrReadBackInit |
310 |
Covered |
T10,T18,T38 |
StPassThru |
310 |
Covered |
T1,T2,T3 |
StRdReadBack |
281 |
Covered |
T10,T12,T18 |
StRdReadBackDWait |
470 |
Covered |
T18,T38,T44 |
StWaitRd |
274 |
Covered |
T1,T3,T4 |
StWrReadBack |
340 |
Covered |
T10,T12,T18 |
StWrReadBackDWait |
343 |
Covered |
T18,T38,T44 |
StWrReadBackInit |
281 |
Covered |
T10,T12,T18 |
StWriteCmd |
300 |
Covered |
T1,T3,T4 |
transitions | Line No. | Covered | Tests |
StByteWrReadBack->StPassThru |
426 |
Covered |
T10,T18,T38 |
StByteWrReadBackDWait->StByteWrReadBack |
443 |
Covered |
T18,T38,T45 |
StByteWrReadBackInit->StByteWrReadBack |
403 |
Covered |
T10,T18,T38 |
StByteWrReadBackInit->StByteWrReadBackDWait |
409 |
Covered |
T18,T38,T45 |
StPassThru->StRdReadBack |
281 |
Covered |
T10,T12,T18 |
StPassThru->StWaitRd |
274 |
Covered |
T1,T3,T4 |
StPassThru->StWrReadBackInit |
281 |
Covered |
T10,T12,T18 |
StRdReadBack->StPassThru |
463 |
Covered |
T10,T12,T18 |
StRdReadBack->StRdReadBackDWait |
470 |
Covered |
T18,T38,T44 |
StRdReadBackDWait->StPassThru |
486 |
Covered |
T18,T38,T44 |
StWaitRd->StWriteCmd |
300 |
Covered |
T1,T3,T4 |
StWrReadBack->StPassThru |
359 |
Covered |
T10,T12,T18 |
StWrReadBackDWait->StWrReadBack |
378 |
Covered |
T18,T38,T44 |
StWrReadBackInit->StWrReadBack |
340 |
Covered |
T10,T12,T18 |
StWrReadBackInit->StWrReadBackDWait |
343 |
Covered |
T18,T38,T44 |
StWriteCmd->StByteWrReadBackInit |
310 |
Covered |
T10,T18,T38 |
StWriteCmd->StPassThru |
310 |
Covered |
T1,T3,T4 |
Branch Coverage for Module :
tlul_sram_byte
| Line No. | Total | Covered | Percent |
Branches |
|
61 |
56 |
91.80 |
IF |
105 |
2 |
2 |
100.00 |
CASE |
255 |
39 |
34 |
87.18 |
IF |
542 |
2 |
2 |
100.00 |
TERNARY |
554 |
2 |
2 |
100.00 |
IF |
590 |
16 |
16 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 105 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 255 case (gen_integ_handling.state_q)
-2-: 257 if ((prim_mubi_pkg::mubi4_test_true_loose(gen_integ_handling.rdback_en_q) && prim_mubi_pkg::mubi4_test_true_loose(gen_integ_handling.rdback_check_q)))
-3-: 266 if (((!gen_integ_handling.rdback_chk_ok) && (!error_i)))
-4-: 271 if (gen_integ_handling.byte_wr_txn)
-5-: 273 if (gen_integ_handling.byte_req_ack)
-6-: 276 if (((gen_integ_handling.a_ack && prim_mubi_pkg::mubi4_test_true_loose(gen_integ_handling.rdback_en_q)) && (!error_i)))
-7-: 281 (gen_integ_handling.wr_txn) ?
-8-: 284 if ((((!tl_sram_o.a_valid) && (!tl_o.d_valid)) && prim_mubi_pkg::mubi4_test_false_strict(gen_integ_handling.rdback_check_q)))
-9-: 297 if ((gen_integ_handling.pending_txn_cnt == 2'(1)))
-10-: 299 if (gen_integ_handling.sram_d_ack)
-11-: 309 if (gen_integ_handling.sram_a_ack)
-12-: 320 if ((EnableReadback == 1'b0))
-13-: 330 if ((gen_integ_handling.pending_txn_cnt == 2'(1)))
-14-: 337 if (gen_integ_handling.d_ack)
-15-: 350 if ((EnableReadback == 1'b0))
-16-: 365 if ((EnableReadback == 1'b0))
-17-: 375 if (gen_integ_handling.d_ack)
-18-: 385 if ((EnableReadback == 1'b0))
-19-: 395 if ((gen_integ_handling.pending_txn_cnt == 2'(1)))
-20-: 400 if (gen_integ_handling.d_ack)
-21-: 417 if ((EnableReadback == 1'b0))
-22-: 430 if ((EnableReadback == 1'b0))
-23-: 440 if (gen_integ_handling.d_ack)
-24-: 448 if ((EnableReadback == 1'b0))
-25-: 459 if ((gen_integ_handling.pending_txn_cnt == 2'(1)))
-26-: 462 if (gen_integ_handling.d_ack)
-27-: 476 if ((EnableReadback == 1'b0))
-28-: 483 if (gen_integ_handling.d_ack)
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | -14- | -15- | -16- | -17- | -18- | -19- | -20- | -21- | -22- | -23- | -24- | -25- | -26- | -27- | -28- | Status | Tests |
StPassThru |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
StPassThru |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T10,T12,T18 |
StPassThru |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StPassThru |
- |
- |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T3,T4 |
StPassThru |
- |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T9,T11,T37 |
StPassThru |
- |
- |
0 |
- |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T10,T12,T18 |
StPassThru |
- |
- |
0 |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T10,T12,T18 |
StPassThru |
- |
- |
0 |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StPassThru |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StPassThru |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T3,T5 |
StWaitRd |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T3,T4 |
StWaitRd |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
StWaitRd |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T9,T18 |
StWriteCmd |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T3,T4 |
StWriteCmd |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
StWrReadBackInit |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
|
StWrReadBackInit |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T10,T12,T18 |
StWrReadBackInit |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T10,T12,T18 |
StWrReadBackInit |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T18,T38,T44 |
StWrReadBackInit |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T18,T42,T43 |
StWrReadBack |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
|
StWrReadBack |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T10,T12,T18 |
StWrReadBackDWait |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
|
StWrReadBackDWait |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T18,T38,T44 |
StWrReadBackDWait |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T18,T38,T44 |
StWrReadBackDWait |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T18,T38,T44 |
StByteWrReadBackInit |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
|
StByteWrReadBackInit |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T10,T18,T38 |
StByteWrReadBackInit |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T10,T18,T38 |
StByteWrReadBackInit |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T18,T38,T42 |
StByteWrReadBackInit |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
StByteWrReadBack |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
|
StByteWrReadBack |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T10,T18,T38 |
StByteWrReadBackDWait |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
Unreachable |
|
StByteWrReadBackDWait |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T18,T38,T45 |
StByteWrReadBackDWait |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T18,T38,T45 |
StByteWrReadBackDWait |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
Covered |
T18,T38,T45 |
StRdReadBack |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
Unreachable |
|
StRdReadBack |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
Covered |
T10,T12,T18 |
StRdReadBack |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
- |
- |
Covered |
T10,T12,T18 |
StRdReadBack |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
Covered |
T18,T38,T44 |
StRdReadBack |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
Covered |
T18,T42,T43 |
StRdReadBackDWait |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
Unreachable |
|
StRdReadBackDWait |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
Covered |
T18,T38,T44 |
StRdReadBackDWait |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T18,T38,T44 |
StRdReadBackDWait |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T18,T38,T44 |
default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
LineNo. Expression
-1-: 542 if ((gen_integ_handling.sram_d_ack && gen_integ_handling.rd_wait))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T3,T4 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 554 (gen_integ_handling.held_data.a_mask[i]) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T3,T4 |
0 |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 590 if (((gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase) | gen_integ_handling.rdback_phase_wrreadback))
-2-: 593 (gen_integ_handling.wr_phase) ?
-3-: 596 ((gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)) ?
-4-: 598 ((gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)) ?
-5-: 603 ((gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)) ?
-6-: 607 (gen_integ_handling.wr_phase) ?
-7-: 608 (gen_integ_handling.wr_phase) ?
-8-: 610 if (gen_integ_handling.rd_phase)
-9-: 614 if (((!error_i) || gen_integ_handling.stall_host))
-10-: 623 if (gen_integ_handling.wait_phase)
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | Status | Tests |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T3,T4 |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T10,T12,T18 |
1 |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T3,T4 |
1 |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T10,T12,T18 |
1 |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T3,T4 |
1 |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T10,T12,T18 |
1 |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T1,T3,T4 |
1 |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
Covered |
T10,T12,T18 |
1 |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
Covered |
T1,T3,T4 |
1 |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
Covered |
T10,T12,T18 |
1 |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
Covered |
T1,T3,T4 |
1 |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
Covered |
T10,T12,T18 |
0 |
- |
- |
- |
- |
- |
- |
1 |
1 |
- |
Covered |
T1,T3,T4 |
0 |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
Covered |
T11,T18,T21 |
0 |
- |
- |
- |
- |
- |
- |
0 |
- |
1 |
Covered |
T10,T12,T18 |
0 |
- |
- |
- |
- |
- |
- |
0 |
- |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
tlul_sram_byte
Assertion Details
SramReadbackAndIntg
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
893 |
893 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
gen_integ_handling.ByteAccessStateChange_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
305371424 |
6203538 |
0 |
0 |
T1 |
63480 |
15 |
0 |
0 |
T2 |
1291 |
0 |
0 |
0 |
T3 |
487200 |
18318 |
0 |
0 |
T4 |
3676 |
38 |
0 |
0 |
T5 |
72308 |
0 |
0 |
0 |
T6 |
7295 |
2 |
0 |
0 |
T9 |
8689 |
588 |
0 |
0 |
T10 |
5370 |
502 |
0 |
0 |
T11 |
352538 |
4166 |
0 |
0 |
T12 |
9336 |
0 |
0 |
0 |
T18 |
0 |
200 |
0 |
0 |
T37 |
0 |
1885 |
0 |
0 |
T46 |
0 |
229 |
0 |
0 |
gen_integ_handling.ReadCompleteStateChange_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
305371424 |
6203538 |
0 |
0 |
T1 |
63480 |
15 |
0 |
0 |
T2 |
1291 |
0 |
0 |
0 |
T3 |
487200 |
18318 |
0 |
0 |
T4 |
3676 |
38 |
0 |
0 |
T5 |
72308 |
0 |
0 |
0 |
T6 |
7295 |
2 |
0 |
0 |
T9 |
8689 |
588 |
0 |
0 |
T10 |
5370 |
502 |
0 |
0 |
T11 |
352538 |
4166 |
0 |
0 |
T12 |
9336 |
0 |
0 |
0 |
T18 |
0 |
200 |
0 |
0 |
T37 |
0 |
1885 |
0 |
0 |
T46 |
0 |
229 |
0 |
0 |
gen_integ_handling.ReadbackAccessAlwaysGranted_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
305371424 |
274094 |
0 |
0 |
T10 |
5370 |
895 |
0 |
0 |
T11 |
352538 |
0 |
0 |
0 |
T12 |
9336 |
2047 |
0 |
0 |
T13 |
1318 |
0 |
0 |
0 |
T18 |
133239 |
464 |
0 |
0 |
T21 |
610361 |
0 |
0 |
0 |
T22 |
0 |
1049 |
0 |
0 |
T23 |
0 |
18963 |
0 |
0 |
T37 |
82229 |
0 |
0 |
0 |
T38 |
10142 |
383 |
0 |
0 |
T41 |
100652 |
0 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T44 |
0 |
243 |
0 |
0 |
T45 |
0 |
338 |
0 |
0 |
T46 |
14462 |
0 |
0 |
0 |
T47 |
0 |
13765 |
0 |
0 |
gen_integ_handling.ReadbackDataImmediatelyAvailable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
305371424 |
385817 |
0 |
0 |
T10 |
5370 |
898 |
0 |
0 |
T11 |
352538 |
0 |
0 |
0 |
T12 |
9336 |
3070 |
0 |
0 |
T13 |
1318 |
0 |
0 |
0 |
T18 |
133239 |
718 |
0 |
0 |
T21 |
610361 |
0 |
0 |
0 |
T22 |
0 |
2110 |
0 |
0 |
T23 |
0 |
21195 |
0 |
0 |
T37 |
82229 |
0 |
0 |
0 |
T38 |
10142 |
555 |
0 |
0 |
T41 |
100652 |
0 |
0 |
0 |
T42 |
0 |
4 |
0 |
0 |
T44 |
0 |
686 |
0 |
0 |
T45 |
0 |
487 |
0 |
0 |
T46 |
14462 |
0 |
0 |
0 |
T47 |
0 |
19720 |
0 |
0 |
gen_integ_handling.TlulSramByteTlSize_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
305371424 |
305254074 |
0 |
0 |
T1 |
63480 |
63232 |
0 |
0 |
T2 |
1291 |
1220 |
0 |
0 |
T3 |
487200 |
487126 |
0 |
0 |
T4 |
3676 |
3616 |
0 |
0 |
T5 |
72308 |
72232 |
0 |
0 |
T6 |
7295 |
7203 |
0 |
0 |
T9 |
8689 |
8617 |
0 |
0 |
T10 |
5370 |
5292 |
0 |
0 |
T11 |
352538 |
352450 |
0 |
0 |
T12 |
9336 |
9264 |
0 |
0 |
gen_integ_handling.gen_readback_logic.NoPendingWriteAfterWrite_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
305371424 |
35048 |
0 |
0 |
T10 |
5370 |
502 |
0 |
0 |
T11 |
352538 |
0 |
0 |
0 |
T12 |
9336 |
0 |
0 |
0 |
T13 |
1318 |
0 |
0 |
0 |
T18 |
133239 |
176 |
0 |
0 |
T21 |
610361 |
0 |
0 |
0 |
T22 |
0 |
248 |
0 |
0 |
T23 |
0 |
805 |
0 |
0 |
T37 |
82229 |
0 |
0 |
0 |
T38 |
10142 |
535 |
0 |
0 |
T41 |
100652 |
0 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T45 |
0 |
541 |
0 |
0 |
T46 |
14462 |
0 |
0 |
0 |
T47 |
0 |
1201 |
0 |
0 |
T48 |
0 |
540 |
0 |
0 |
T49 |
0 |
926 |
0 |
0 |
gen_integ_handling.gen_readback_logic.WRCollisionDuringReadBack_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
305371424 |
578784 |
0 |
0 |
T10 |
5370 |
931 |
0 |
0 |
T11 |
352538 |
0 |
0 |
0 |
T12 |
9336 |
3071 |
0 |
0 |
T13 |
1318 |
0 |
0 |
0 |
T18 |
133239 |
4113 |
0 |
0 |
T21 |
610361 |
0 |
0 |
0 |
T22 |
0 |
5331 |
0 |
0 |
T23 |
0 |
21298 |
0 |
0 |
T37 |
82229 |
0 |
0 |
0 |
T38 |
10142 |
939 |
0 |
0 |
T41 |
100652 |
0 |
0 |
0 |
T42 |
0 |
17 |
0 |
0 |
T44 |
0 |
4250 |
0 |
0 |
T45 |
0 |
958 |
0 |
0 |
T46 |
14462 |
0 |
0 |
0 |
T47 |
0 |
26632 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte
| Line No. | Total | Covered | Percent |
TOTAL | | 145 | 144 | 99.31 |
ALWAYS | 105 | 3 | 3 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
CONT_ASSIGN | 142 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
ALWAYS | 239 | 95 | 94 | 98.95 |
CONT_ASSIGN | 506 | 1 | 1 | 100.00 |
CONT_ASSIGN | 517 | 1 | 1 | 100.00 |
ALWAYS | 542 | 2 | 2 | 100.00 |
ALWAYS | 553 | 0 | 0 | |
ALWAYS | 553 | 2 | 2 | 100.00 |
ALWAYS | 572 | 2 | 2 | 100.00 |
ALWAYS | 579 | 22 | 22 | 100.00 |
CONT_ASSIGN | 633 | 1 | 1 | 100.00 |
ALWAYS | 658 | 4 | 4 | 100.00 |
CONT_ASSIGN | 676 | 1 | 1 | 100.00 |
CONT_ASSIGN | 699 | 1 | 1 | 100.00 |
CONT_ASSIGN | 716 | 1 | 1 | 100.00 |
CONT_ASSIGN | 717 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
105 |
1 |
1 |
106 |
1 |
1 |
108 |
1 |
1 |
138 |
1 |
1 |
139 |
1 |
1 |
140 |
1 |
1 |
141 |
1 |
1 |
142 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
156 |
1 |
1 |
239 |
1 |
1 |
240 |
1 |
1 |
241 |
1 |
1 |
242 |
1 |
1 |
243 |
1 |
1 |
244 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
247 |
1 |
1 |
248 |
1 |
1 |
249 |
1 |
1 |
250 |
1 |
1 |
251 |
1 |
1 |
252 |
1 |
1 |
253 |
1 |
1 |
255 |
1 |
1 |
257 |
1 |
1 |
262 |
1 |
1 |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
0 |
1 |
|
|
|
MISSING_ELSE |
|
|
|
MISSING_ELSE |
271 |
1 |
1 |
272 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
|
|
|
MISSING_ELSE |
276 |
1 |
1 |
280 |
1 |
1 |
281 |
1 |
1 |
|
|
|
MISSING_ELSE |
284 |
1 |
1 |
287 |
1 |
1 |
|
|
|
MISSING_ELSE |
295 |
1 |
1 |
296 |
1 |
1 |
297 |
1 |
1 |
298 |
1 |
1 |
299 |
1 |
1 |
300 |
1 |
1 |
|
|
|
==> MISSING_ELSE |
|
|
|
MISSING_ELSE |
306 |
1 |
1 |
307 |
1 |
1 |
309 |
1 |
1 |
310 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
313 |
1 |
1 |
|
|
|
==> MISSING_ELSE |
320 |
1 |
1 |
322 |
|
unreachable |
|
|
|
MISSING_ELSE |
326 |
1 |
1 |
330 |
1 |
1 |
331 |
1 |
1 |
334 |
1 |
1 |
335 |
1 |
1 |
336 |
1 |
1 |
337 |
1 |
1 |
340 |
1 |
1 |
343 |
1 |
1 |
|
|
|
MISSING_ELSE |
350 |
1 |
1 |
352 |
|
unreachable |
|
|
|
MISSING_ELSE |
355 |
1 |
1 |
357 |
1 |
1 |
359 |
1 |
1 |
365 |
1 |
1 |
367 |
|
unreachable |
|
|
|
MISSING_ELSE |
371 |
1 |
1 |
373 |
1 |
1 |
375 |
1 |
1 |
378 |
1 |
1 |
|
|
|
MISSING_ELSE |
385 |
1 |
1 |
387 |
|
unreachable |
|
|
|
MISSING_ELSE |
392 |
1 |
1 |
395 |
1 |
1 |
398 |
1 |
1 |
400 |
1 |
1 |
403 |
1 |
1 |
409 |
1 |
1 |
|
|
|
==> MISSING_ELSE |
417 |
1 |
1 |
419 |
|
unreachable |
|
|
|
MISSING_ELSE |
422 |
1 |
1 |
424 |
1 |
1 |
426 |
1 |
1 |
430 |
1 |
1 |
432 |
|
unreachable |
|
|
|
MISSING_ELSE |
435 |
1 |
1 |
438 |
1 |
1 |
440 |
1 |
1 |
443 |
1 |
1 |
|
|
|
MISSING_ELSE |
448 |
1 |
1 |
450 |
|
unreachable |
|
|
|
MISSING_ELSE |
455 |
1 |
1 |
459 |
1 |
1 |
460 |
1 |
1 |
462 |
1 |
1 |
463 |
1 |
1 |
465 |
1 |
1 |
466 |
1 |
1 |
467 |
1 |
1 |
470 |
1 |
1 |
|
|
|
MISSING_ELSE |
476 |
1 |
1 |
478 |
|
unreachable |
|
|
|
MISSING_ELSE |
481 |
1 |
1 |
483 |
1 |
1 |
486 |
1 |
1 |
488 |
1 |
1 |
489 |
1 |
1 |
490 |
1 |
1 |
|
|
|
MISSING_ELSE |
506 |
1 |
1 |
517 |
1 |
1 |
542 |
1 |
1 |
543 |
1 |
1 |
|
|
|
MISSING_ELSE |
553 |
1 |
1 |
554 |
1 |
1 |
572 |
1 |
1 |
573 |
1 |
1 |
579 |
1 |
1 |
581 |
1 |
1 |
590 |
1 |
1 |
591 |
1 |
1 |
593 |
1 |
1 |
596 |
1 |
1 |
598 |
1 |
1 |
602 |
1 |
1 |
603 |
1 |
1 |
605 |
1 |
1 |
606 |
1 |
1 |
607 |
1 |
1 |
608 |
1 |
1 |
610 |
1 |
1 |
612 |
1 |
1 |
614 |
1 |
1 |
617 |
1 |
1 |
618 |
1 |
1 |
620 |
1 |
1 |
621 |
1 |
1 |
|
|
|
MISSING_ELSE |
623 |
1 |
1 |
626 |
1 |
1 |
|
|
|
MISSING_ELSE |
633 |
1 |
1 |
658 |
1 |
1 |
661 |
1 |
1 |
665 |
1 |
1 |
670 |
1 |
1 |
676 |
1 |
1 |
699 |
1 |
1 |
716 |
1 |
1 |
717 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte
| Total | Covered | Percent |
Conditions | 97 | 93 | 95.88 |
Logical | 97 | 93 | 95.88 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 138
EXPRESSION (tl_i.a_valid & tl_o.a_ready)
------1----- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T5 |
LINE 139
EXPRESSION (tl_o.d_valid & tl_i.d_ready)
------1----- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T4,T6 |
1 | 1 | Covered | T1,T3,T5 |
LINE 140
EXPRESSION (tl_sram_o.a_valid & tl_sram_i.a_ready)
--------1-------- --------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T6,T9 |
1 | 1 | Covered | T1,T3,T5 |
LINE 141
EXPRESSION (tl_sram_i.d_valid & tl_sram_o.d_ready)
--------1-------- --------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T4,T6 |
1 | 1 | Covered | T1,T3,T5 |
LINE 142
EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData))
---------------1-------------- ----------------2----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T5 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
LINE 142
SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 142
SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
----------------1----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T5 |
LINE 144
EXPRESSION (gen_integ_handling.byte_wr_txn & gen_integ_handling.a_ack & ((~error_i)))
---------------1-------------- ------------2----------- ------3-----
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T5 |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Covered | T11,T18,T21 |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 145
EXPRESSION (tl_i.a_valid & ((~&tl_i.a_mask)) & gen_integ_handling.wr_txn)
------1----- --------2-------- ------------3------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T3,T5 |
1 | 1 | 0 | Covered | T1,T3,T4 |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 156
EXPRESSION (gen_integ_handling.rdback_data_exp_q == tl_sram_i.d_data)
-----------------------------1----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T5,T4 |
LINE 266
EXPRESSION (((!gen_integ_handling.rdback_chk_ok)) && ((!error_i)))
------------------1------------------ ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T10,T12,T18 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 281
EXPRESSION (gen_integ_handling.wr_txn ? StWrReadBackInit : StRdReadBack)
------------1------------
-1- | Status | Tests |
0 | Covered | T10,T12,T18 |
1 | Covered | T10,T12,T18 |
LINE 297
EXPRESSION (gen_integ_handling.pending_txn_cnt == 2'(1))
----------------------1----------------------
-1- | Status | Tests |
0 | Covered | T1,T9,T18 |
1 | Covered | T1,T3,T4 |
LINE 330
EXPRESSION (gen_integ_handling.pending_txn_cnt == 2'(1))
----------------------1----------------------
-1- | Status | Tests |
0 | Covered | T18,T42,T43 |
1 | Covered | T10,T12,T18 |
LINE 395
EXPRESSION (gen_integ_handling.pending_txn_cnt == 2'(1))
----------------------1----------------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T10,T18,T38 |
LINE 459
EXPRESSION (gen_integ_handling.pending_txn_cnt == 2'(1))
----------------------1----------------------
-1- | Status | Tests |
0 | Covered | T18,T42,T43 |
1 | Covered | T10,T12,T18 |
LINE 517
EXPRESSION (gen_integ_handling.hold_tx_data | gen_integ_handling.byte_req_ack)
---------------1--------------- ---------------2---------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T10,T12,T18 |
LINE 542
EXPRESSION (gen_integ_handling.sram_d_ack && gen_integ_handling.rd_wait)
--------------1-------------- -------------2------------
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
[UNR] this should not happen because the read latency of prim_ram_1p_scr is always 1 cycle |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T1,T3,T4 |
LINE 554
EXPRESSION (gen_integ_handling.held_data.a_mask[i] ? gen_integ_handling.held_data.a_data[(i * 8)+:8] : gen_integ_handling.rsp_data[(i * 8)+:8])
-------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T3,T4 |
1 | Covered | T1,T3,T4 |
LINE 581
EXPRESSION (tl_i.d_ready | gen_integ_handling.rd_wait | gen_integ_handling.rdback_wait)
------1----- -------------2------------ ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T18,T38,T44 |
0 | 1 | 0 | Covered | T1,T4,T6 |
1 | 0 | 0 | Covered | T1,T2,T3 |
LINE 590
EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase | gen_integ_handling.rdback_phase_wrreadback)
-------------1------------- ---------------2--------------- ---------------------3--------------------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T10,T18,T38 |
0 | 1 | 0 | Covered | T10,T12,T18 |
1 | 0 | 0 | Covered | T1,T3,T4 |
LINE 593
EXPRESSION (gen_integ_handling.wr_phase ? PutFullData : Get)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T10,T12,T18 |
1 | Covered | T1,T3,T4 |
LINE 596
EXPRESSION
Number Term
1 (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback) ? (2'(gen_integ_handling.AccessSize)) : gen_integ_handling.held_data.a_size)
-1- | Status | Tests |
0 | Covered | T10,T12,T18 |
1 | Covered | T1,T3,T4 |
LINE 596
SUB-EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)
-------------1------------- ---------------------2--------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T10,T12,T18 |
0 | 1 | Covered | T10,T18,T38 |
1 | 0 | Covered | T1,T3,T4 |
LINE 598
EXPRESSION ((gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback) ? ('{(*adjust*)default:'1}) : gen_integ_handling.held_data.a_mask)
-------------------------------------1------------------------------------
-1- | Status | Tests |
0 | Covered | T10,T12,T18 |
1 | Covered | T1,T3,T4 |
LINE 598
SUB-EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)
-------------1------------- ---------------------2--------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T10,T12,T18 |
0 | 1 | Covered | T10,T18,T38 |
1 | 0 | Covered | T1,T3,T4 |
LINE 603
EXPRESSION
Number Term
1 (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback) ? '0 : gen_integ_handling.held_data.a_address[(gen_integ_handling.AccessSize - 1):0])
-1- | Status | Tests |
0 | Covered | T10,T12,T18 |
1 | Covered | T1,T3,T4 |
LINE 603
SUB-EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)
-------------1------------- ---------------------2--------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T10,T12,T18 |
0 | 1 | Covered | T10,T18,T38 |
1 | 0 | Covered | T1,T3,T4 |
LINE 607
EXPRESSION (gen_integ_handling.wr_phase ? gen_integ_handling.combined_data : '0)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T10,T12,T18 |
1 | Covered | T1,T3,T4 |
LINE 608
EXPRESSION (gen_integ_handling.wr_phase ? gen_integ_handling.combined_user : '0)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T10,T12,T18 |
1 | Covered | T1,T3,T4 |
LINE 614
EXPRESSION (((!error_i)) || gen_integ_handling.stall_host)
------1----- --------------2--------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T11,T18,T21 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
LINE 620
EXPRESSION (tl_i.a_valid & ((~gen_integ_handling.stall_host)))
------1----- -----------------2----------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 633
EXPRESSION (error_i & ((~gen_integ_handling.stall_host)))
---1--- -----------------2----------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T2,T3 |
LINE 661
EXPRESSION (tl_sram_i.a_ready & ((~gen_integ_handling.stall_host)) & gen_integ_handling.fifo_rdy & gen_integ_handling.size_fifo_rdy)
--------1-------- -----------------2---------------- -------------3------------- ----------------4---------------
-1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
0 | 1 | 1 | 1 | Covered | T1,T3,T5 |
1 | 0 | 1 | 1 | Excluded | T10,T18,T38 |
VC_COV_UNR |
1 | 1 | 0 | 1 | Excluded | |
VC_COV_UNR |
1 | 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 665
EXPRESSION (tl_sram_i.d_valid & ((~gen_integ_handling.rd_wait)) & ((~gen_integ_handling.rdback_wait)))
--------1-------- ---------------2--------------- -----------------3-----------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Covered | T10,T12,T18 |
1 | 1 | 1 | Covered | T1,T3,T5 |
LINE 699
EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase | gen_integ_handling.rdback_phase_wrreadback)
-------------1------------- ---------------2--------------- ---------------------3--------------------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T10,T18,T38 |
0 | 1 | 0 | Covered | T10,T12,T18 |
1 | 0 | 0 | Covered | T1,T3,T4 |
FSM Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte
Summary for FSM :: gen_integ_handling.state_q
| Total | Covered | Percent | |
States |
11 |
11 |
100.00 |
(Not included in score) |
Transitions |
17 |
17 |
100.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: gen_integ_handling.state_q
states | Line No. | Covered | Tests |
StByteWrReadBack |
403 |
Covered |
T10,T18,T38 |
StByteWrReadBackDWait |
409 |
Covered |
T18,T38,T45 |
StByteWrReadBackInit |
310 |
Covered |
T10,T18,T38 |
StPassThru |
310 |
Covered |
T1,T2,T3 |
StRdReadBack |
281 |
Covered |
T10,T12,T18 |
StRdReadBackDWait |
470 |
Covered |
T18,T38,T44 |
StWaitRd |
274 |
Covered |
T1,T3,T4 |
StWrReadBack |
340 |
Covered |
T10,T12,T18 |
StWrReadBackDWait |
343 |
Covered |
T18,T38,T44 |
StWrReadBackInit |
281 |
Covered |
T10,T12,T18 |
StWriteCmd |
300 |
Covered |
T1,T3,T4 |
transitions | Line No. | Covered | Tests |
StByteWrReadBack->StPassThru |
426 |
Covered |
T10,T18,T38 |
StByteWrReadBackDWait->StByteWrReadBack |
443 |
Covered |
T18,T38,T45 |
StByteWrReadBackInit->StByteWrReadBack |
403 |
Covered |
T10,T18,T38 |
StByteWrReadBackInit->StByteWrReadBackDWait |
409 |
Covered |
T18,T38,T45 |
StPassThru->StRdReadBack |
281 |
Covered |
T10,T12,T18 |
StPassThru->StWaitRd |
274 |
Covered |
T1,T3,T4 |
StPassThru->StWrReadBackInit |
281 |
Covered |
T10,T12,T18 |
StRdReadBack->StPassThru |
463 |
Covered |
T10,T12,T18 |
StRdReadBack->StRdReadBackDWait |
470 |
Covered |
T18,T38,T44 |
StRdReadBackDWait->StPassThru |
486 |
Covered |
T18,T38,T44 |
StWaitRd->StWriteCmd |
300 |
Covered |
T1,T3,T4 |
StWrReadBack->StPassThru |
359 |
Covered |
T10,T12,T18 |
StWrReadBackDWait->StWrReadBack |
378 |
Covered |
T18,T38,T44 |
StWrReadBackInit->StWrReadBack |
340 |
Covered |
T10,T12,T18 |
StWrReadBackInit->StWrReadBackDWait |
343 |
Covered |
T18,T38,T44 |
StWriteCmd->StByteWrReadBackInit |
310 |
Covered |
T10,T18,T38 |
StWriteCmd->StPassThru |
310 |
Covered |
T1,T3,T4 |
Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte
| Line No. | Total | Covered | Percent |
Branches |
|
61 |
56 |
91.80 |
IF |
105 |
2 |
2 |
100.00 |
CASE |
255 |
39 |
34 |
87.18 |
IF |
542 |
2 |
2 |
100.00 |
TERNARY |
554 |
2 |
2 |
100.00 |
IF |
590 |
16 |
16 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 105 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 255 case (gen_integ_handling.state_q)
-2-: 257 if ((prim_mubi_pkg::mubi4_test_true_loose(gen_integ_handling.rdback_en_q) && prim_mubi_pkg::mubi4_test_true_loose(gen_integ_handling.rdback_check_q)))
-3-: 266 if (((!gen_integ_handling.rdback_chk_ok) && (!error_i)))
-4-: 271 if (gen_integ_handling.byte_wr_txn)
-5-: 273 if (gen_integ_handling.byte_req_ack)
-6-: 276 if (((gen_integ_handling.a_ack && prim_mubi_pkg::mubi4_test_true_loose(gen_integ_handling.rdback_en_q)) && (!error_i)))
-7-: 281 (gen_integ_handling.wr_txn) ?
-8-: 284 if ((((!tl_sram_o.a_valid) && (!tl_o.d_valid)) && prim_mubi_pkg::mubi4_test_false_strict(gen_integ_handling.rdback_check_q)))
-9-: 297 if ((gen_integ_handling.pending_txn_cnt == 2'(1)))
-10-: 299 if (gen_integ_handling.sram_d_ack)
-11-: 309 if (gen_integ_handling.sram_a_ack)
-12-: 320 if ((EnableReadback == 1'b0))
-13-: 330 if ((gen_integ_handling.pending_txn_cnt == 2'(1)))
-14-: 337 if (gen_integ_handling.d_ack)
-15-: 350 if ((EnableReadback == 1'b0))
-16-: 365 if ((EnableReadback == 1'b0))
-17-: 375 if (gen_integ_handling.d_ack)
-18-: 385 if ((EnableReadback == 1'b0))
-19-: 395 if ((gen_integ_handling.pending_txn_cnt == 2'(1)))
-20-: 400 if (gen_integ_handling.d_ack)
-21-: 417 if ((EnableReadback == 1'b0))
-22-: 430 if ((EnableReadback == 1'b0))
-23-: 440 if (gen_integ_handling.d_ack)
-24-: 448 if ((EnableReadback == 1'b0))
-25-: 459 if ((gen_integ_handling.pending_txn_cnt == 2'(1)))
-26-: 462 if (gen_integ_handling.d_ack)
-27-: 476 if ((EnableReadback == 1'b0))
-28-: 483 if (gen_integ_handling.d_ack)
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | -14- | -15- | -16- | -17- | -18- | -19- | -20- | -21- | -22- | -23- | -24- | -25- | -26- | -27- | -28- | Status | Tests |
StPassThru |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
StPassThru |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T10,T12,T18 |
StPassThru |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StPassThru |
- |
- |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T3,T4 |
StPassThru |
- |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T9,T11,T37 |
StPassThru |
- |
- |
0 |
- |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T10,T12,T18 |
StPassThru |
- |
- |
0 |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T10,T12,T18 |
StPassThru |
- |
- |
0 |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StPassThru |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StPassThru |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T3,T5 |
StWaitRd |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T3,T4 |
StWaitRd |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
StWaitRd |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T9,T18 |
StWriteCmd |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T3,T4 |
StWriteCmd |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
StWrReadBackInit |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
|
StWrReadBackInit |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T10,T12,T18 |
StWrReadBackInit |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T10,T12,T18 |
StWrReadBackInit |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T18,T38,T44 |
StWrReadBackInit |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T18,T42,T43 |
StWrReadBack |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
|
StWrReadBack |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T10,T12,T18 |
StWrReadBackDWait |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
|
StWrReadBackDWait |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T18,T38,T44 |
StWrReadBackDWait |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T18,T38,T44 |
StWrReadBackDWait |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T18,T38,T44 |
StByteWrReadBackInit |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
|
StByteWrReadBackInit |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T10,T18,T38 |
StByteWrReadBackInit |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T10,T18,T38 |
StByteWrReadBackInit |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T18,T38,T42 |
StByteWrReadBackInit |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
StByteWrReadBack |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
|
StByteWrReadBack |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T10,T18,T38 |
StByteWrReadBackDWait |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
Unreachable |
|
StByteWrReadBackDWait |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T18,T38,T45 |
StByteWrReadBackDWait |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T18,T38,T45 |
StByteWrReadBackDWait |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
Covered |
T18,T38,T45 |
StRdReadBack |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
Unreachable |
|
StRdReadBack |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
Covered |
T10,T12,T18 |
StRdReadBack |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
- |
- |
Covered |
T10,T12,T18 |
StRdReadBack |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
Covered |
T18,T38,T44 |
StRdReadBack |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
Covered |
T18,T42,T43 |
StRdReadBackDWait |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
Unreachable |
|
StRdReadBackDWait |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
Covered |
T18,T38,T44 |
StRdReadBackDWait |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T18,T38,T44 |
StRdReadBackDWait |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T18,T38,T44 |
default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
LineNo. Expression
-1-: 542 if ((gen_integ_handling.sram_d_ack && gen_integ_handling.rd_wait))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T3,T4 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 554 (gen_integ_handling.held_data.a_mask[i]) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T3,T4 |
0 |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 590 if (((gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase) | gen_integ_handling.rdback_phase_wrreadback))
-2-: 593 (gen_integ_handling.wr_phase) ?
-3-: 596 ((gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)) ?
-4-: 598 ((gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)) ?
-5-: 603 ((gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)) ?
-6-: 607 (gen_integ_handling.wr_phase) ?
-7-: 608 (gen_integ_handling.wr_phase) ?
-8-: 610 if (gen_integ_handling.rd_phase)
-9-: 614 if (((!error_i) || gen_integ_handling.stall_host))
-10-: 623 if (gen_integ_handling.wait_phase)
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | Status | Tests |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T3,T4 |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T10,T12,T18 |
1 |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T3,T4 |
1 |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T10,T12,T18 |
1 |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T3,T4 |
1 |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T10,T12,T18 |
1 |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T1,T3,T4 |
1 |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
Covered |
T10,T12,T18 |
1 |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
Covered |
T1,T3,T4 |
1 |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
Covered |
T10,T12,T18 |
1 |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
Covered |
T1,T3,T4 |
1 |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
Covered |
T10,T12,T18 |
0 |
- |
- |
- |
- |
- |
- |
1 |
1 |
- |
Covered |
T1,T3,T4 |
0 |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
Covered |
T11,T18,T21 |
0 |
- |
- |
- |
- |
- |
- |
0 |
- |
1 |
Covered |
T10,T12,T18 |
0 |
- |
- |
- |
- |
- |
- |
0 |
- |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte
Assertion Details
SramReadbackAndIntg
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
893 |
893 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
gen_integ_handling.ByteAccessStateChange_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
305371424 |
6203538 |
0 |
0 |
T1 |
63480 |
15 |
0 |
0 |
T2 |
1291 |
0 |
0 |
0 |
T3 |
487200 |
18318 |
0 |
0 |
T4 |
3676 |
38 |
0 |
0 |
T5 |
72308 |
0 |
0 |
0 |
T6 |
7295 |
2 |
0 |
0 |
T9 |
8689 |
588 |
0 |
0 |
T10 |
5370 |
502 |
0 |
0 |
T11 |
352538 |
4166 |
0 |
0 |
T12 |
9336 |
0 |
0 |
0 |
T18 |
0 |
200 |
0 |
0 |
T37 |
0 |
1885 |
0 |
0 |
T46 |
0 |
229 |
0 |
0 |
gen_integ_handling.ReadCompleteStateChange_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
305371424 |
6203538 |
0 |
0 |
T1 |
63480 |
15 |
0 |
0 |
T2 |
1291 |
0 |
0 |
0 |
T3 |
487200 |
18318 |
0 |
0 |
T4 |
3676 |
38 |
0 |
0 |
T5 |
72308 |
0 |
0 |
0 |
T6 |
7295 |
2 |
0 |
0 |
T9 |
8689 |
588 |
0 |
0 |
T10 |
5370 |
502 |
0 |
0 |
T11 |
352538 |
4166 |
0 |
0 |
T12 |
9336 |
0 |
0 |
0 |
T18 |
0 |
200 |
0 |
0 |
T37 |
0 |
1885 |
0 |
0 |
T46 |
0 |
229 |
0 |
0 |
gen_integ_handling.ReadbackAccessAlwaysGranted_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
305371424 |
274094 |
0 |
0 |
T10 |
5370 |
895 |
0 |
0 |
T11 |
352538 |
0 |
0 |
0 |
T12 |
9336 |
2047 |
0 |
0 |
T13 |
1318 |
0 |
0 |
0 |
T18 |
133239 |
464 |
0 |
0 |
T21 |
610361 |
0 |
0 |
0 |
T22 |
0 |
1049 |
0 |
0 |
T23 |
0 |
18963 |
0 |
0 |
T37 |
82229 |
0 |
0 |
0 |
T38 |
10142 |
383 |
0 |
0 |
T41 |
100652 |
0 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T44 |
0 |
243 |
0 |
0 |
T45 |
0 |
338 |
0 |
0 |
T46 |
14462 |
0 |
0 |
0 |
T47 |
0 |
13765 |
0 |
0 |
gen_integ_handling.ReadbackDataImmediatelyAvailable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
305371424 |
385817 |
0 |
0 |
T10 |
5370 |
898 |
0 |
0 |
T11 |
352538 |
0 |
0 |
0 |
T12 |
9336 |
3070 |
0 |
0 |
T13 |
1318 |
0 |
0 |
0 |
T18 |
133239 |
718 |
0 |
0 |
T21 |
610361 |
0 |
0 |
0 |
T22 |
0 |
2110 |
0 |
0 |
T23 |
0 |
21195 |
0 |
0 |
T37 |
82229 |
0 |
0 |
0 |
T38 |
10142 |
555 |
0 |
0 |
T41 |
100652 |
0 |
0 |
0 |
T42 |
0 |
4 |
0 |
0 |
T44 |
0 |
686 |
0 |
0 |
T45 |
0 |
487 |
0 |
0 |
T46 |
14462 |
0 |
0 |
0 |
T47 |
0 |
19720 |
0 |
0 |
gen_integ_handling.TlulSramByteTlSize_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
305371424 |
305254074 |
0 |
0 |
T1 |
63480 |
63232 |
0 |
0 |
T2 |
1291 |
1220 |
0 |
0 |
T3 |
487200 |
487126 |
0 |
0 |
T4 |
3676 |
3616 |
0 |
0 |
T5 |
72308 |
72232 |
0 |
0 |
T6 |
7295 |
7203 |
0 |
0 |
T9 |
8689 |
8617 |
0 |
0 |
T10 |
5370 |
5292 |
0 |
0 |
T11 |
352538 |
352450 |
0 |
0 |
T12 |
9336 |
9264 |
0 |
0 |
gen_integ_handling.gen_readback_logic.NoPendingWriteAfterWrite_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
305371424 |
35048 |
0 |
0 |
T10 |
5370 |
502 |
0 |
0 |
T11 |
352538 |
0 |
0 |
0 |
T12 |
9336 |
0 |
0 |
0 |
T13 |
1318 |
0 |
0 |
0 |
T18 |
133239 |
176 |
0 |
0 |
T21 |
610361 |
0 |
0 |
0 |
T22 |
0 |
248 |
0 |
0 |
T23 |
0 |
805 |
0 |
0 |
T37 |
82229 |
0 |
0 |
0 |
T38 |
10142 |
535 |
0 |
0 |
T41 |
100652 |
0 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T45 |
0 |
541 |
0 |
0 |
T46 |
14462 |
0 |
0 |
0 |
T47 |
0 |
1201 |
0 |
0 |
T48 |
0 |
540 |
0 |
0 |
T49 |
0 |
926 |
0 |
0 |
gen_integ_handling.gen_readback_logic.WRCollisionDuringReadBack_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
305371424 |
578784 |
0 |
0 |
T10 |
5370 |
931 |
0 |
0 |
T11 |
352538 |
0 |
0 |
0 |
T12 |
9336 |
3071 |
0 |
0 |
T13 |
1318 |
0 |
0 |
0 |
T18 |
133239 |
4113 |
0 |
0 |
T21 |
610361 |
0 |
0 |
0 |
T22 |
0 |
5331 |
0 |
0 |
T23 |
0 |
21298 |
0 |
0 |
T37 |
82229 |
0 |
0 |
0 |
T38 |
10142 |
939 |
0 |
0 |
T41 |
100652 |
0 |
0 |
0 |
T42 |
0 |
17 |
0 |
0 |
T44 |
0 |
4250 |
0 |
0 |
T45 |
0 |
958 |
0 |
0 |
T46 |
14462 |
0 |
0 |
0 |
T47 |
0 |
26632 |
0 |
0 |