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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.95 99.16 94.27 99.72 100.00 95.95 99.12 97.44


Total test records in report: 1025
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html

T796 /workspace/coverage/default/39.sram_ctrl_partial_access.38814425 Jul 10 05:18:44 PM PDT 24 Jul 10 05:21:15 PM PDT 24 789680787 ps
T797 /workspace/coverage/default/37.sram_ctrl_executable.1217247186 Jul 10 05:18:29 PM PDT 24 Jul 10 05:34:29 PM PDT 24 12358291236 ps
T798 /workspace/coverage/default/14.sram_ctrl_access_during_key_req.1367849173 Jul 10 05:16:37 PM PDT 24 Jul 10 05:17:07 PM PDT 24 4722135188 ps
T799 /workspace/coverage/default/19.sram_ctrl_multiple_keys.3664717450 Jul 10 05:16:53 PM PDT 24 Jul 10 05:35:15 PM PDT 24 13259782306 ps
T800 /workspace/coverage/default/18.sram_ctrl_mem_walk.1700659317 Jul 10 05:16:49 PM PDT 24 Jul 10 05:16:59 PM PDT 24 932471027 ps
T801 /workspace/coverage/default/10.sram_ctrl_multiple_keys.3807559552 Jul 10 05:16:35 PM PDT 24 Jul 10 05:51:04 PM PDT 24 58386440756 ps
T802 /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.919523499 Jul 10 05:17:35 PM PDT 24 Jul 10 05:18:35 PM PDT 24 510422013 ps
T803 /workspace/coverage/default/28.sram_ctrl_alert_test.3130282190 Jul 10 05:17:42 PM PDT 24 Jul 10 05:17:44 PM PDT 24 31860078 ps
T804 /workspace/coverage/default/39.sram_ctrl_mem_walk.3518916338 Jul 10 05:18:43 PM PDT 24 Jul 10 05:18:50 PM PDT 24 931830674 ps
T805 /workspace/coverage/default/26.sram_ctrl_partial_access.1816244184 Jul 10 05:17:23 PM PDT 24 Jul 10 05:19:26 PM PDT 24 244842598 ps
T806 /workspace/coverage/default/0.sram_ctrl_mem_partial_access.2161780275 Jul 10 05:16:12 PM PDT 24 Jul 10 05:16:20 PM PDT 24 93299367 ps
T807 /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.1067484373 Jul 10 05:16:50 PM PDT 24 Jul 10 05:20:22 PM PDT 24 113699011549 ps
T808 /workspace/coverage/default/21.sram_ctrl_mem_partial_access.874319209 Jul 10 05:17:02 PM PDT 24 Jul 10 05:17:07 PM PDT 24 380852287 ps
T809 /workspace/coverage/default/22.sram_ctrl_partial_access.4261302471 Jul 10 05:17:01 PM PDT 24 Jul 10 05:18:05 PM PDT 24 597480198 ps
T810 /workspace/coverage/default/43.sram_ctrl_executable.1251255652 Jul 10 05:19:12 PM PDT 24 Jul 10 05:32:04 PM PDT 24 3137528425 ps
T811 /workspace/coverage/default/4.sram_ctrl_smoke.3648086977 Jul 10 05:16:17 PM PDT 24 Jul 10 05:16:21 PM PDT 24 48231283 ps
T812 /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.3201240933 Jul 10 05:16:44 PM PDT 24 Jul 10 05:16:51 PM PDT 24 54345459 ps
T813 /workspace/coverage/default/45.sram_ctrl_stress_all.2520337372 Jul 10 05:19:29 PM PDT 24 Jul 10 05:57:25 PM PDT 24 48747138971 ps
T814 /workspace/coverage/default/12.sram_ctrl_bijection.3924548540 Jul 10 05:16:38 PM PDT 24 Jul 10 05:17:04 PM PDT 24 1312413120 ps
T815 /workspace/coverage/default/42.sram_ctrl_lc_escalation.482563820 Jul 10 05:19:05 PM PDT 24 Jul 10 05:19:07 PM PDT 24 67021222 ps
T816 /workspace/coverage/default/37.sram_ctrl_alert_test.2913341544 Jul 10 05:18:29 PM PDT 24 Jul 10 05:18:31 PM PDT 24 31465926 ps
T817 /workspace/coverage/default/41.sram_ctrl_smoke.1175036194 Jul 10 05:18:55 PM PDT 24 Jul 10 05:19:06 PM PDT 24 1593321975 ps
T818 /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.1525967139 Jul 10 05:16:45 PM PDT 24 Jul 10 05:16:59 PM PDT 24 709692372 ps
T819 /workspace/coverage/default/7.sram_ctrl_smoke.1426558925 Jul 10 05:16:22 PM PDT 24 Jul 10 05:17:49 PM PDT 24 232101155 ps
T820 /workspace/coverage/default/22.sram_ctrl_alert_test.3512474791 Jul 10 05:17:06 PM PDT 24 Jul 10 05:17:08 PM PDT 24 44414999 ps
T821 /workspace/coverage/default/12.sram_ctrl_mem_walk.2762865186 Jul 10 05:16:37 PM PDT 24 Jul 10 05:16:52 PM PDT 24 1804630507 ps
T822 /workspace/coverage/default/22.sram_ctrl_mem_partial_access.162076430 Jul 10 05:17:05 PM PDT 24 Jul 10 05:17:09 PM PDT 24 48436640 ps
T823 /workspace/coverage/default/43.sram_ctrl_stress_pipeline.4163097329 Jul 10 05:19:09 PM PDT 24 Jul 10 05:24:09 PM PDT 24 13112635865 ps
T824 /workspace/coverage/default/13.sram_ctrl_stress_pipeline.3585167253 Jul 10 05:16:35 PM PDT 24 Jul 10 05:21:55 PM PDT 24 28738264956 ps
T825 /workspace/coverage/default/48.sram_ctrl_stress_all.341840383 Jul 10 05:19:52 PM PDT 24 Jul 10 06:56:54 PM PDT 24 206587420982 ps
T826 /workspace/coverage/default/33.sram_ctrl_mem_walk.3876230775 Jul 10 05:18:05 PM PDT 24 Jul 10 05:18:12 PM PDT 24 230654277 ps
T827 /workspace/coverage/default/24.sram_ctrl_ram_cfg.3495543070 Jul 10 05:17:19 PM PDT 24 Jul 10 05:17:21 PM PDT 24 97037537 ps
T828 /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.458401332 Jul 10 05:16:24 PM PDT 24 Jul 10 05:18:57 PM PDT 24 1610325371 ps
T829 /workspace/coverage/default/14.sram_ctrl_mem_walk.3773298975 Jul 10 05:16:44 PM PDT 24 Jul 10 05:16:53 PM PDT 24 627410718 ps
T830 /workspace/coverage/default/24.sram_ctrl_alert_test.1007585867 Jul 10 05:17:19 PM PDT 24 Jul 10 05:17:20 PM PDT 24 39634872 ps
T831 /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.2403168023 Jul 10 05:17:42 PM PDT 24 Jul 10 05:18:22 PM PDT 24 197496043 ps
T832 /workspace/coverage/default/16.sram_ctrl_stress_all.1294225219 Jul 10 05:16:48 PM PDT 24 Jul 10 06:05:40 PM PDT 24 204699062589 ps
T833 /workspace/coverage/default/18.sram_ctrl_regwen.3630072593 Jul 10 05:16:47 PM PDT 24 Jul 10 05:21:19 PM PDT 24 1152592828 ps
T834 /workspace/coverage/default/23.sram_ctrl_smoke.3878057815 Jul 10 05:17:07 PM PDT 24 Jul 10 05:18:20 PM PDT 24 465467632 ps
T835 /workspace/coverage/default/5.sram_ctrl_bijection.3890219729 Jul 10 05:16:19 PM PDT 24 Jul 10 05:16:59 PM PDT 24 2201299810 ps
T836 /workspace/coverage/default/35.sram_ctrl_lc_escalation.1724776202 Jul 10 05:18:18 PM PDT 24 Jul 10 05:18:20 PM PDT 24 175320551 ps
T837 /workspace/coverage/default/12.sram_ctrl_partial_access.1379643150 Jul 10 05:16:36 PM PDT 24 Jul 10 05:17:21 PM PDT 24 395912138 ps
T838 /workspace/coverage/default/16.sram_ctrl_multiple_keys.1887494570 Jul 10 05:16:45 PM PDT 24 Jul 10 05:31:15 PM PDT 24 7637012345 ps
T839 /workspace/coverage/default/14.sram_ctrl_max_throughput.4321330 Jul 10 05:16:44 PM PDT 24 Jul 10 05:17:00 PM PDT 24 1276772079 ps
T840 /workspace/coverage/default/38.sram_ctrl_smoke.1381893497 Jul 10 05:18:26 PM PDT 24 Jul 10 05:18:34 PM PDT 24 60077977 ps
T841 /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.2876964360 Jul 10 05:16:27 PM PDT 24 Jul 10 05:22:49 PM PDT 24 14291802949 ps
T842 /workspace/coverage/default/19.sram_ctrl_mem_partial_access.1437283402 Jul 10 05:16:51 PM PDT 24 Jul 10 05:16:58 PM PDT 24 94599204 ps
T843 /workspace/coverage/default/40.sram_ctrl_mem_walk.1480532081 Jul 10 05:18:48 PM PDT 24 Jul 10 05:18:55 PM PDT 24 824587417 ps
T844 /workspace/coverage/default/31.sram_ctrl_lc_escalation.605829771 Jul 10 05:17:57 PM PDT 24 Jul 10 05:18:08 PM PDT 24 5113091255 ps
T845 /workspace/coverage/default/8.sram_ctrl_max_throughput.3117682820 Jul 10 05:16:22 PM PDT 24 Jul 10 05:17:21 PM PDT 24 488148310 ps
T846 /workspace/coverage/default/18.sram_ctrl_multiple_keys.2069093102 Jul 10 05:16:48 PM PDT 24 Jul 10 05:36:02 PM PDT 24 1161671386 ps
T847 /workspace/coverage/default/41.sram_ctrl_regwen.1136181396 Jul 10 05:19:06 PM PDT 24 Jul 10 05:26:20 PM PDT 24 4503112758 ps
T848 /workspace/coverage/default/15.sram_ctrl_partial_access.2043242952 Jul 10 05:16:44 PM PDT 24 Jul 10 05:16:56 PM PDT 24 3317266782 ps
T849 /workspace/coverage/default/26.sram_ctrl_stress_all.441656043 Jul 10 05:17:28 PM PDT 24 Jul 10 05:39:00 PM PDT 24 42936140453 ps
T850 /workspace/coverage/default/34.sram_ctrl_stress_pipeline.1944870832 Jul 10 05:18:12 PM PDT 24 Jul 10 05:22:03 PM PDT 24 2448313671 ps
T851 /workspace/coverage/default/25.sram_ctrl_ram_cfg.3147065513 Jul 10 05:17:22 PM PDT 24 Jul 10 05:17:24 PM PDT 24 42416007 ps
T852 /workspace/coverage/default/36.sram_ctrl_stress_pipeline.3713988070 Jul 10 05:18:15 PM PDT 24 Jul 10 05:24:02 PM PDT 24 14180611835 ps
T853 /workspace/coverage/default/33.sram_ctrl_regwen.82820418 Jul 10 05:18:03 PM PDT 24 Jul 10 05:25:31 PM PDT 24 2150620308 ps
T854 /workspace/coverage/default/30.sram_ctrl_smoke.3719152907 Jul 10 05:17:40 PM PDT 24 Jul 10 05:17:45 PM PDT 24 211431415 ps
T855 /workspace/coverage/default/16.sram_ctrl_max_throughput.1952962915 Jul 10 05:16:47 PM PDT 24 Jul 10 05:17:24 PM PDT 24 329930830 ps
T856 /workspace/coverage/default/23.sram_ctrl_mem_partial_access.1537750227 Jul 10 05:17:16 PM PDT 24 Jul 10 05:17:22 PM PDT 24 344883640 ps
T857 /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.3147938034 Jul 10 05:16:18 PM PDT 24 Jul 10 05:17:34 PM PDT 24 940274744 ps
T858 /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.1761148815 Jul 10 05:16:31 PM PDT 24 Jul 10 05:18:45 PM PDT 24 156157025 ps
T859 /workspace/coverage/default/19.sram_ctrl_bijection.2375702925 Jul 10 05:16:53 PM PDT 24 Jul 10 05:17:19 PM PDT 24 1446743111 ps
T860 /workspace/coverage/default/26.sram_ctrl_multiple_keys.2003615771 Jul 10 05:17:23 PM PDT 24 Jul 10 05:27:43 PM PDT 24 2460747043 ps
T861 /workspace/coverage/default/9.sram_ctrl_alert_test.3050878715 Jul 10 05:16:36 PM PDT 24 Jul 10 05:16:40 PM PDT 24 12687823 ps
T862 /workspace/coverage/default/10.sram_ctrl_mem_walk.2312227413 Jul 10 05:16:36 PM PDT 24 Jul 10 05:16:50 PM PDT 24 361317102 ps
T863 /workspace/coverage/default/48.sram_ctrl_multiple_keys.2645011794 Jul 10 05:19:47 PM PDT 24 Jul 10 05:20:12 PM PDT 24 405410644 ps
T864 /workspace/coverage/default/29.sram_ctrl_multiple_keys.2456860310 Jul 10 05:17:35 PM PDT 24 Jul 10 05:29:19 PM PDT 24 7852969091 ps
T865 /workspace/coverage/default/38.sram_ctrl_executable.4236473677 Jul 10 05:18:33 PM PDT 24 Jul 10 05:35:21 PM PDT 24 9136334336 ps
T866 /workspace/coverage/default/35.sram_ctrl_executable.2838198602 Jul 10 05:18:17 PM PDT 24 Jul 10 05:26:52 PM PDT 24 4383740538 ps
T867 /workspace/coverage/default/30.sram_ctrl_bijection.1628517714 Jul 10 05:17:42 PM PDT 24 Jul 10 05:18:54 PM PDT 24 1115502628 ps
T868 /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1981335244 Jul 10 05:19:19 PM PDT 24 Jul 10 05:25:20 PM PDT 24 19289204900 ps
T869 /workspace/coverage/default/32.sram_ctrl_mem_walk.1742997157 Jul 10 05:17:58 PM PDT 24 Jul 10 05:18:04 PM PDT 24 1279511007 ps
T870 /workspace/coverage/default/42.sram_ctrl_access_during_key_req.1426975327 Jul 10 05:19:05 PM PDT 24 Jul 10 05:26:47 PM PDT 24 2963696303 ps
T871 /workspace/coverage/default/25.sram_ctrl_regwen.1311713084 Jul 10 05:17:24 PM PDT 24 Jul 10 05:27:36 PM PDT 24 6182863410 ps
T872 /workspace/coverage/default/38.sram_ctrl_partial_access.965531224 Jul 10 05:18:32 PM PDT 24 Jul 10 05:18:56 PM PDT 24 95171745 ps
T873 /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.2070775078 Jul 10 05:19:10 PM PDT 24 Jul 10 05:20:15 PM PDT 24 433308405 ps
T874 /workspace/coverage/default/44.sram_ctrl_stress_pipeline.461406324 Jul 10 05:19:18 PM PDT 24 Jul 10 05:25:01 PM PDT 24 11866133134 ps
T875 /workspace/coverage/default/42.sram_ctrl_smoke.3864915228 Jul 10 05:19:04 PM PDT 24 Jul 10 05:19:15 PM PDT 24 922282555 ps
T876 /workspace/coverage/default/43.sram_ctrl_alert_test.1231946220 Jul 10 05:19:16 PM PDT 24 Jul 10 05:19:18 PM PDT 24 47047156 ps
T877 /workspace/coverage/default/34.sram_ctrl_mem_walk.2681755558 Jul 10 05:18:12 PM PDT 24 Jul 10 05:18:24 PM PDT 24 459222589 ps
T878 /workspace/coverage/default/40.sram_ctrl_stress_all.224665183 Jul 10 05:18:57 PM PDT 24 Jul 10 05:44:42 PM PDT 24 18426211320 ps
T879 /workspace/coverage/default/14.sram_ctrl_ram_cfg.3651188840 Jul 10 05:16:37 PM PDT 24 Jul 10 05:16:42 PM PDT 24 76366777 ps
T880 /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.691513774 Jul 10 05:17:24 PM PDT 24 Jul 10 05:21:54 PM PDT 24 1619275434 ps
T881 /workspace/coverage/default/35.sram_ctrl_access_during_key_req.3098785950 Jul 10 05:18:19 PM PDT 24 Jul 10 05:30:33 PM PDT 24 6025483627 ps
T882 /workspace/coverage/default/15.sram_ctrl_max_throughput.2683480961 Jul 10 05:16:45 PM PDT 24 Jul 10 05:17:47 PM PDT 24 456905871 ps
T883 /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.1778744438 Jul 10 05:16:13 PM PDT 24 Jul 10 05:17:30 PM PDT 24 480162166 ps
T884 /workspace/coverage/default/37.sram_ctrl_partial_access.2368669219 Jul 10 05:18:23 PM PDT 24 Jul 10 05:19:22 PM PDT 24 7541787835 ps
T885 /workspace/coverage/default/5.sram_ctrl_regwen.92793779 Jul 10 05:16:27 PM PDT 24 Jul 10 05:53:43 PM PDT 24 44808640061 ps
T886 /workspace/coverage/default/23.sram_ctrl_regwen.2967807251 Jul 10 05:17:13 PM PDT 24 Jul 10 05:45:26 PM PDT 24 9083547596 ps
T887 /workspace/coverage/default/3.sram_ctrl_regwen.1195416588 Jul 10 05:16:25 PM PDT 24 Jul 10 05:17:11 PM PDT 24 712352164 ps
T888 /workspace/coverage/default/31.sram_ctrl_stress_pipeline.1041455923 Jul 10 05:17:57 PM PDT 24 Jul 10 05:22:11 PM PDT 24 2598376761 ps
T889 /workspace/coverage/default/28.sram_ctrl_smoke.4240485524 Jul 10 05:17:35 PM PDT 24 Jul 10 05:17:42 PM PDT 24 313647042 ps
T890 /workspace/coverage/default/26.sram_ctrl_access_during_key_req.1749564006 Jul 10 05:17:29 PM PDT 24 Jul 10 05:36:37 PM PDT 24 3641196306 ps
T891 /workspace/coverage/default/31.sram_ctrl_access_during_key_req.4191096987 Jul 10 05:17:47 PM PDT 24 Jul 10 05:36:38 PM PDT 24 3043767218 ps
T892 /workspace/coverage/default/49.sram_ctrl_executable.2291239095 Jul 10 05:19:58 PM PDT 24 Jul 10 05:31:57 PM PDT 24 13529507370 ps
T893 /workspace/coverage/default/36.sram_ctrl_smoke.2938404377 Jul 10 05:18:21 PM PDT 24 Jul 10 05:18:37 PM PDT 24 81350095 ps
T894 /workspace/coverage/default/2.sram_ctrl_alert_test.2955714555 Jul 10 05:16:09 PM PDT 24 Jul 10 05:16:14 PM PDT 24 40356396 ps
T895 /workspace/coverage/default/10.sram_ctrl_stress_all.2296500270 Jul 10 05:16:38 PM PDT 24 Jul 10 05:43:15 PM PDT 24 23986561561 ps
T896 /workspace/coverage/default/41.sram_ctrl_ram_cfg.1030280284 Jul 10 05:19:04 PM PDT 24 Jul 10 05:19:05 PM PDT 24 35323091 ps
T897 /workspace/coverage/default/36.sram_ctrl_lc_escalation.275484812 Jul 10 05:18:17 PM PDT 24 Jul 10 05:18:25 PM PDT 24 2399548202 ps
T898 /workspace/coverage/default/33.sram_ctrl_mem_partial_access.760539510 Jul 10 05:18:03 PM PDT 24 Jul 10 05:18:08 PM PDT 24 1157580781 ps
T899 /workspace/coverage/default/21.sram_ctrl_regwen.2973729210 Jul 10 05:16:57 PM PDT 24 Jul 10 05:23:25 PM PDT 24 18211537085 ps
T900 /workspace/coverage/default/42.sram_ctrl_partial_access.45245589 Jul 10 05:19:05 PM PDT 24 Jul 10 05:19:10 PM PDT 24 243786025 ps
T901 /workspace/coverage/default/19.sram_ctrl_stress_all.1675758205 Jul 10 05:16:49 PM PDT 24 Jul 10 05:24:08 PM PDT 24 3582360982 ps
T902 /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.3851138775 Jul 10 05:16:46 PM PDT 24 Jul 10 05:16:58 PM PDT 24 72334386 ps
T903 /workspace/coverage/default/14.sram_ctrl_stress_all.3569364331 Jul 10 05:16:49 PM PDT 24 Jul 10 05:50:24 PM PDT 24 30740090713 ps
T904 /workspace/coverage/default/7.sram_ctrl_executable.2883418158 Jul 10 05:16:24 PM PDT 24 Jul 10 05:30:51 PM PDT 24 54734409693 ps
T905 /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.1820943668 Jul 10 05:17:35 PM PDT 24 Jul 10 05:25:36 PM PDT 24 79540517113 ps
T906 /workspace/coverage/default/0.sram_ctrl_regwen.3123709775 Jul 10 05:16:05 PM PDT 24 Jul 10 05:20:52 PM PDT 24 1965402429 ps
T907 /workspace/coverage/default/7.sram_ctrl_ram_cfg.1297116203 Jul 10 05:16:25 PM PDT 24 Jul 10 05:16:28 PM PDT 24 121887827 ps
T908 /workspace/coverage/default/40.sram_ctrl_stress_pipeline.1603955943 Jul 10 05:18:41 PM PDT 24 Jul 10 05:22:29 PM PDT 24 2342651652 ps
T909 /workspace/coverage/default/33.sram_ctrl_ram_cfg.2564520727 Jul 10 05:18:03 PM PDT 24 Jul 10 05:18:06 PM PDT 24 45473456 ps
T910 /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.2443350590 Jul 10 05:19:34 PM PDT 24 Jul 10 05:24:53 PM PDT 24 8553931639 ps
T911 /workspace/coverage/default/20.sram_ctrl_alert_test.355968367 Jul 10 05:16:57 PM PDT 24 Jul 10 05:17:00 PM PDT 24 40680442 ps
T912 /workspace/coverage/default/16.sram_ctrl_mem_partial_access.1874488947 Jul 10 05:16:47 PM PDT 24 Jul 10 05:16:54 PM PDT 24 221109851 ps
T913 /workspace/coverage/default/13.sram_ctrl_ram_cfg.2060057435 Jul 10 05:16:38 PM PDT 24 Jul 10 05:16:42 PM PDT 24 28080761 ps
T914 /workspace/coverage/default/43.sram_ctrl_ram_cfg.68594637 Jul 10 05:19:10 PM PDT 24 Jul 10 05:19:12 PM PDT 24 77298519 ps
T915 /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.2945468348 Jul 10 05:18:37 PM PDT 24 Jul 10 05:20:32 PM PDT 24 578543183 ps
T916 /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.832921603 Jul 10 05:16:36 PM PDT 24 Jul 10 05:18:25 PM PDT 24 669887761 ps
T917 /workspace/coverage/default/2.sram_ctrl_mem_walk.781570125 Jul 10 05:16:15 PM PDT 24 Jul 10 05:16:25 PM PDT 24 587914035 ps
T918 /workspace/coverage/default/7.sram_ctrl_stress_all.75864533 Jul 10 05:16:27 PM PDT 24 Jul 10 06:11:14 PM PDT 24 13846793732 ps
T919 /workspace/coverage/default/6.sram_ctrl_ram_cfg.3283875564 Jul 10 05:16:25 PM PDT 24 Jul 10 05:16:29 PM PDT 24 30882928 ps
T920 /workspace/coverage/default/9.sram_ctrl_executable.1019790662 Jul 10 05:16:28 PM PDT 24 Jul 10 05:49:57 PM PDT 24 12689834867 ps
T921 /workspace/coverage/default/35.sram_ctrl_stress_pipeline.464806330 Jul 10 05:18:13 PM PDT 24 Jul 10 05:21:45 PM PDT 24 9003661473 ps
T922 /workspace/coverage/default/11.sram_ctrl_bijection.994017159 Jul 10 05:16:36 PM PDT 24 Jul 10 05:16:56 PM PDT 24 3145164156 ps
T923 /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.4004142774 Jul 10 05:17:08 PM PDT 24 Jul 10 05:24:35 PM PDT 24 75736562226 ps
T924 /workspace/coverage/default/23.sram_ctrl_executable.2603440390 Jul 10 05:17:12 PM PDT 24 Jul 10 05:45:08 PM PDT 24 13336862933 ps
T925 /workspace/coverage/default/3.sram_ctrl_mem_walk.3648072177 Jul 10 05:16:16 PM PDT 24 Jul 10 05:16:24 PM PDT 24 1071903577 ps
T926 /workspace/coverage/default/11.sram_ctrl_alert_test.1969389055 Jul 10 05:16:37 PM PDT 24 Jul 10 05:16:41 PM PDT 24 32163906 ps
T927 /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.3637411263 Jul 10 05:18:11 PM PDT 24 Jul 10 05:24:59 PM PDT 24 6359834122 ps
T928 /workspace/coverage/default/5.sram_ctrl_mem_walk.384247247 Jul 10 05:16:22 PM PDT 24 Jul 10 05:16:29 PM PDT 24 315112182 ps
T929 /workspace/coverage/default/44.sram_ctrl_mem_walk.2289646700 Jul 10 05:19:21 PM PDT 24 Jul 10 05:19:33 PM PDT 24 175975354 ps
T930 /workspace/coverage/default/42.sram_ctrl_regwen.2900586681 Jul 10 05:19:05 PM PDT 24 Jul 10 05:24:59 PM PDT 24 8789063311 ps
T931 /workspace/coverage/default/21.sram_ctrl_access_during_key_req.1845150850 Jul 10 05:16:57 PM PDT 24 Jul 10 05:52:56 PM PDT 24 3716038357 ps
T932 /workspace/coverage/default/16.sram_ctrl_executable.4113692864 Jul 10 05:16:47 PM PDT 24 Jul 10 05:33:32 PM PDT 24 73982082351 ps
T933 /workspace/coverage/default/23.sram_ctrl_stress_all.1248763314 Jul 10 05:17:13 PM PDT 24 Jul 10 06:06:51 PM PDT 24 43411034272 ps
T934 /workspace/coverage/default/49.sram_ctrl_alert_test.2862407223 Jul 10 05:20:03 PM PDT 24 Jul 10 05:20:04 PM PDT 24 40848456 ps
T935 /workspace/coverage/default/12.sram_ctrl_stress_all.1969420213 Jul 10 05:16:37 PM PDT 24 Jul 10 06:24:56 PM PDT 24 54967567805 ps
T936 /workspace/coverage/default/16.sram_ctrl_regwen.2857113882 Jul 10 05:16:46 PM PDT 24 Jul 10 05:34:13 PM PDT 24 62285801148 ps
T937 /workspace/coverage/default/39.sram_ctrl_access_during_key_req.619531161 Jul 10 05:18:41 PM PDT 24 Jul 10 05:42:21 PM PDT 24 3494366906 ps
T938 /workspace/coverage/default/12.sram_ctrl_alert_test.463722192 Jul 10 05:16:39 PM PDT 24 Jul 10 05:16:43 PM PDT 24 14603696 ps
T53 /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.142264563 Jul 10 04:44:08 PM PDT 24 Jul 10 04:44:10 PM PDT 24 77527483 ps
T54 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2758292040 Jul 10 04:44:15 PM PDT 24 Jul 10 04:44:27 PM PDT 24 17413899 ps
T50 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2205853943 Jul 10 04:43:55 PM PDT 24 Jul 10 04:43:58 PM PDT 24 349517391 ps
T93 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.756217727 Jul 10 04:43:49 PM PDT 24 Jul 10 04:43:51 PM PDT 24 13927058 ps
T113 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.4289565148 Jul 10 04:43:57 PM PDT 24 Jul 10 04:43:58 PM PDT 24 105546985 ps
T94 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2570546914 Jul 10 04:43:55 PM PDT 24 Jul 10 04:43:56 PM PDT 24 36891394 ps
T63 /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.4031784588 Jul 10 04:44:05 PM PDT 24 Jul 10 04:44:07 PM PDT 24 53464417 ps
T51 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.618866157 Jul 10 04:43:48 PM PDT 24 Jul 10 04:43:52 PM PDT 24 263255988 ps
T89 /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.301000134 Jul 10 04:43:45 PM PDT 24 Jul 10 04:43:50 PM PDT 24 3547007567 ps
T64 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.386821867 Jul 10 04:43:43 PM PDT 24 Jul 10 04:43:44 PM PDT 24 38589706 ps
T52 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3805172550 Jul 10 04:43:53 PM PDT 24 Jul 10 04:43:55 PM PDT 24 118945822 ps
T939 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2199421546 Jul 10 04:43:54 PM PDT 24 Jul 10 04:43:57 PM PDT 24 149225404 ps
T65 /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1923146379 Jul 10 04:44:06 PM PDT 24 Jul 10 04:44:10 PM PDT 24 1577193377 ps
T66 /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1167763410 Jul 10 04:44:03 PM PDT 24 Jul 10 04:44:08 PM PDT 24 691412215 ps
T67 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3034104815 Jul 10 04:44:12 PM PDT 24 Jul 10 04:44:13 PM PDT 24 35763447 ps
T68 /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2393079435 Jul 10 04:44:18 PM PDT 24 Jul 10 04:44:20 PM PDT 24 19459217 ps
T940 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1948342951 Jul 10 04:44:10 PM PDT 24 Jul 10 04:44:12 PM PDT 24 48045341 ps
T69 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2421518159 Jul 10 04:43:52 PM PDT 24 Jul 10 04:43:53 PM PDT 24 74645508 ps
T70 /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.4092297272 Jul 10 04:44:17 PM PDT 24 Jul 10 04:44:21 PM PDT 24 1420192887 ps
T71 /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.75095729 Jul 10 04:44:09 PM PDT 24 Jul 10 04:44:12 PM PDT 24 30274072 ps
T941 /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1435349629 Jul 10 04:44:12 PM PDT 24 Jul 10 04:44:13 PM PDT 24 34666221 ps
T942 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2621112128 Jul 10 04:44:07 PM PDT 24 Jul 10 04:44:10 PM PDT 24 105207034 ps
T103 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1613691963 Jul 10 04:44:17 PM PDT 24 Jul 10 04:44:21 PM PDT 24 2329680378 ps
T943 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.433535981 Jul 10 04:43:57 PM PDT 24 Jul 10 04:44:02 PM PDT 24 635941785 ps
T121 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2443554699 Jul 10 04:44:13 PM PDT 24 Jul 10 04:44:15 PM PDT 24 588031144 ps
T72 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2976422022 Jul 10 04:44:09 PM PDT 24 Jul 10 04:44:12 PM PDT 24 16790307 ps
T944 /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2782228934 Jul 10 04:43:47 PM PDT 24 Jul 10 04:43:49 PM PDT 24 180040932 ps
T945 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.63015326 Jul 10 04:44:17 PM PDT 24 Jul 10 04:44:18 PM PDT 24 22262864 ps
T946 /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.417627667 Jul 10 04:44:19 PM PDT 24 Jul 10 04:44:21 PM PDT 24 83757958 ps
T947 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2967755048 Jul 10 04:44:17 PM PDT 24 Jul 10 04:44:19 PM PDT 24 35723052 ps
T122 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.206447274 Jul 10 04:43:59 PM PDT 24 Jul 10 04:44:01 PM PDT 24 95191517 ps
T948 /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1619829201 Jul 10 04:43:56 PM PDT 24 Jul 10 04:44:01 PM PDT 24 1716876584 ps
T949 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.186117847 Jul 10 04:44:04 PM PDT 24 Jul 10 04:44:08 PM PDT 24 24953224 ps
T950 /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3222356896 Jul 10 04:44:20 PM PDT 24 Jul 10 04:44:22 PM PDT 24 93943733 ps
T951 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1061976150 Jul 10 04:43:48 PM PDT 24 Jul 10 04:43:50 PM PDT 24 26239558 ps
T952 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.52529305 Jul 10 04:44:14 PM PDT 24 Jul 10 04:44:16 PM PDT 24 16183227 ps
T953 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3462722920 Jul 10 04:44:15 PM PDT 24 Jul 10 04:44:18 PM PDT 24 126949305 ps
T954 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.848330503 Jul 10 04:43:47 PM PDT 24 Jul 10 04:43:50 PM PDT 24 28336344 ps
T955 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1585476054 Jul 10 04:43:52 PM PDT 24 Jul 10 04:43:54 PM PDT 24 71605443 ps
T956 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.4199096236 Jul 10 04:44:15 PM PDT 24 Jul 10 04:44:24 PM PDT 24 37251544 ps
T957 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1090724154 Jul 10 04:43:52 PM PDT 24 Jul 10 04:43:54 PM PDT 24 137551293 ps
T958 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3896501116 Jul 10 04:44:10 PM PDT 24 Jul 10 04:44:15 PM PDT 24 441698316 ps
T959 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2313748796 Jul 10 04:43:49 PM PDT 24 Jul 10 04:43:51 PM PDT 24 14103252 ps
T960 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3785697042 Jul 10 04:44:12 PM PDT 24 Jul 10 04:44:15 PM PDT 24 108948592 ps
T73 /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3794206281 Jul 10 04:44:00 PM PDT 24 Jul 10 04:44:03 PM PDT 24 820944598 ps
T74 /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3131452208 Jul 10 04:44:14 PM PDT 24 Jul 10 04:44:16 PM PDT 24 767112977 ps
T75 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.671911011 Jul 10 04:43:46 PM PDT 24 Jul 10 04:43:47 PM PDT 24 21326733 ps
T961 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.597001495 Jul 10 04:44:09 PM PDT 24 Jul 10 04:44:12 PM PDT 24 108755297 ps
T114 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1391651336 Jul 10 04:43:48 PM PDT 24 Jul 10 04:43:54 PM PDT 24 519410766 ps
T76 /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2850087562 Jul 10 04:43:57 PM PDT 24 Jul 10 04:44:01 PM PDT 24 412185382 ps
T962 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1238592180 Jul 10 04:44:08 PM PDT 24 Jul 10 04:44:10 PM PDT 24 15063834 ps
T77 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3320217675 Jul 10 04:44:19 PM PDT 24 Jul 10 04:44:21 PM PDT 24 26639429 ps
T82 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.723983666 Jul 10 04:43:56 PM PDT 24 Jul 10 04:43:59 PM PDT 24 75782079 ps
T963 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.168303170 Jul 10 04:44:17 PM PDT 24 Jul 10 04:44:19 PM PDT 24 21041980 ps
T119 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.491181056 Jul 10 04:44:19 PM PDT 24 Jul 10 04:44:24 PM PDT 24 537462330 ps
T964 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3724398052 Jul 10 04:44:20 PM PDT 24 Jul 10 04:44:25 PM PDT 24 31300314 ps
T83 /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3101994601 Jul 10 04:44:02 PM PDT 24 Jul 10 04:44:05 PM PDT 24 813928665 ps
T965 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2119371812 Jul 10 04:44:17 PM PDT 24 Jul 10 04:44:19 PM PDT 24 60198943 ps
T966 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.568223617 Jul 10 04:43:57 PM PDT 24 Jul 10 04:44:01 PM PDT 24 129602820 ps
T120 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1926820329 Jul 10 04:44:06 PM PDT 24 Jul 10 04:44:10 PM PDT 24 107413779 ps
T967 /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2976259392 Jul 10 04:44:23 PM PDT 24 Jul 10 04:44:25 PM PDT 24 105398922 ps
T115 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1737856619 Jul 10 04:44:11 PM PDT 24 Jul 10 04:44:17 PM PDT 24 861262724 ps
T968 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2704293650 Jul 10 04:44:19 PM PDT 24 Jul 10 04:44:23 PM PDT 24 51126543 ps
T969 /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.955427349 Jul 10 04:44:08 PM PDT 24 Jul 10 04:44:10 PM PDT 24 28960697 ps
T84 /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2966769830 Jul 10 04:44:28 PM PDT 24 Jul 10 04:44:31 PM PDT 24 1415776598 ps
T970 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3817135543 Jul 10 04:43:46 PM PDT 24 Jul 10 04:43:47 PM PDT 24 29654719 ps
T85 /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1589988180 Jul 10 04:44:15 PM PDT 24 Jul 10 04:44:19 PM PDT 24 1714342350 ps
T86 /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1132968234 Jul 10 04:44:11 PM PDT 24 Jul 10 04:44:15 PM PDT 24 2289470383 ps
T116 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.4112118118 Jul 10 04:43:57 PM PDT 24 Jul 10 04:44:00 PM PDT 24 335502382 ps
T87 /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2684531537 Jul 10 04:43:47 PM PDT 24 Jul 10 04:43:50 PM PDT 24 1092310920 ps
T971 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1980137262 Jul 10 04:43:49 PM PDT 24 Jul 10 04:43:55 PM PDT 24 587981619 ps
T972 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2914089537 Jul 10 04:43:42 PM PDT 24 Jul 10 04:43:45 PM PDT 24 1287606565 ps
T123 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2103254636 Jul 10 04:44:09 PM PDT 24 Jul 10 04:44:13 PM PDT 24 496380227 ps
T88 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3876868815 Jul 10 04:43:47 PM PDT 24 Jul 10 04:43:48 PM PDT 24 21666760 ps
T973 /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2644406602 Jul 10 04:44:20 PM PDT 24 Jul 10 04:44:23 PM PDT 24 774099683 ps
T974 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1128008144 Jul 10 04:44:11 PM PDT 24 Jul 10 04:44:15 PM PDT 24 914988982 ps
T975 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2690890459 Jul 10 04:44:18 PM PDT 24 Jul 10 04:44:23 PM PDT 24 392635765 ps
T976 /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3800991126 Jul 10 04:43:49 PM PDT 24 Jul 10 04:43:52 PM PDT 24 416122106 ps
T977 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2810036850 Jul 10 04:44:06 PM PDT 24 Jul 10 04:44:10 PM PDT 24 1275347470 ps
T978 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3502422837 Jul 10 04:43:48 PM PDT 24 Jul 10 04:43:52 PM PDT 24 260092189 ps
T979 /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1336636147 Jul 10 04:44:06 PM PDT 24 Jul 10 04:44:08 PM PDT 24 14598492 ps
T980 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2745882345 Jul 10 04:43:57 PM PDT 24 Jul 10 04:44:00 PM PDT 24 172106547 ps
T981 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2615402483 Jul 10 04:44:14 PM PDT 24 Jul 10 04:44:15 PM PDT 24 104605432 ps
T982 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3705268399 Jul 10 04:44:06 PM PDT 24 Jul 10 04:44:11 PM PDT 24 166564222 ps
T983 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2889123250 Jul 10 04:43:54 PM PDT 24 Jul 10 04:43:56 PM PDT 24 12844201 ps
T128 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3652829453 Jul 10 04:44:05 PM PDT 24 Jul 10 04:44:09 PM PDT 24 3945908422 ps
T984 /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.492115093 Jul 10 04:44:01 PM PDT 24 Jul 10 04:44:04 PM PDT 24 208580223 ps
T985 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.4232083075 Jul 10 04:43:54 PM PDT 24 Jul 10 04:43:55 PM PDT 24 21077695 ps
T986 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3856340913 Jul 10 04:44:14 PM PDT 24 Jul 10 04:44:19 PM PDT 24 36265147 ps
T987 /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1880396892 Jul 10 04:44:16 PM PDT 24 Jul 10 04:44:21 PM PDT 24 3469922801 ps
T988 /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2188412936 Jul 10 04:44:08 PM PDT 24 Jul 10 04:44:10 PM PDT 24 305121431 ps
T125 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.396525080 Jul 10 04:44:21 PM PDT 24 Jul 10 04:44:24 PM PDT 24 195020474 ps
T989 /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1565677620 Jul 10 04:43:56 PM PDT 24 Jul 10 04:43:58 PM PDT 24 24970912 ps
T990 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2601050343 Jul 10 04:44:09 PM PDT 24 Jul 10 04:44:12 PM PDT 24 18016298 ps
T991 /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.200092234 Jul 10 04:43:52 PM PDT 24 Jul 10 04:43:53 PM PDT 24 12889382 ps
T992 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.881407416 Jul 10 04:43:52 PM PDT 24 Jul 10 04:43:53 PM PDT 24 42692209 ps
T993 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2005475805 Jul 10 04:44:17 PM PDT 24 Jul 10 04:44:19 PM PDT 24 49828073 ps
T994 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1429511984 Jul 10 04:44:20 PM PDT 24 Jul 10 04:44:24 PM PDT 24 110350068 ps
T995 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.4054087530 Jul 10 04:43:48 PM PDT 24 Jul 10 04:43:51 PM PDT 24 84417018 ps
T996 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1273756230 Jul 10 04:44:19 PM PDT 24 Jul 10 04:44:22 PM PDT 24 203898270 ps
T997 /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3770333421 Jul 10 04:44:19 PM PDT 24 Jul 10 04:44:24 PM PDT 24 2677083985 ps
T998 /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.251392029 Jul 10 04:43:55 PM PDT 24 Jul 10 04:43:56 PM PDT 24 17800098 ps
T999 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1881820913 Jul 10 04:44:13 PM PDT 24 Jul 10 04:44:14 PM PDT 24 14163279 ps
T127 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.484125531 Jul 10 04:44:06 PM PDT 24 Jul 10 04:44:09 PM PDT 24 190991156 ps
T1000 /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3205060967 Jul 10 04:44:22 PM PDT 24 Jul 10 04:44:27 PM PDT 24 630583614 ps
T1001 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1328917136 Jul 10 04:44:02 PM PDT 24 Jul 10 04:44:05 PM PDT 24 37736110 ps
T1002 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2220697365 Jul 10 04:43:59 PM PDT 24 Jul 10 04:44:00 PM PDT 24 152185705 ps
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