Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13851001	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

58584018

1

T1

303830

T3

93

T4

173146

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36114874	1			T1	167241		T3	958		T4	95294
values[0x0]	16776559	1			T1	80378		T3	339		T4	45657
values[0x1]	19543586	1			T1	86512		T3	743		T4	49471

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6898485	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

65536534

1

T1

318927

T3

939

T4

181745

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	295677	1			T1	1322		T4	727		T5	2
valid_sources[0x01]	310076	1			T1	1263		T3	21		T4	586
valid_sources[0x02]	249923	1			T1	1275		T3	41		T4	748
valid_sources[0x03]	325083	1			T1	1288		T4	670		T5	4
valid_sources[0x04]	259505	1			T1	1353		T3	13		T4	755
valid_sources[0x05]	283066	1			T1	1321		T3	15		T4	805
valid_sources[0x06]	280043	1			T1	1384		T3	12		T4	715
valid_sources[0x07]	258016	1			T1	1282		T4	653		T5	3
valid_sources[0x08]	273375	1			T1	1193		T3	3		T4	823
valid_sources[0x09]	272368	1			T1	1352		T3	16		T4	835
valid_sources[0x0a]	248648	1			T1	1278		T3	16		T4	755
valid_sources[0x0b]	314009	1			T1	1256		T3	16		T4	808
valid_sources[0x0c]	286177	1			T1	1335		T3	3		T4	724
valid_sources[0x0d]	310232	1			T1	1333		T3	31		T4	844
valid_sources[0x0e]	292968	1			T1	1300		T4	734		T5	2
valid_sources[0x0f]	280450	1			T1	1275		T3	3		T4	600
valid_sources[0x10]	295048	1			T1	1347		T3	8		T4	734
valid_sources[0x11]	260745	1			T1	1258		T3	1		T4	760
valid_sources[0x12]	300976	1			T1	1443		T3	11		T4	620
valid_sources[0x13]	276521	1			T1	1212		T4	750		T5	7
valid_sources[0x14]	256666	1			T1	1301		T3	15		T4	784
valid_sources[0x15]	282372	1			T1	1268		T3	6		T4	764
valid_sources[0x16]	249898	1			T1	1262		T3	12		T4	709
valid_sources[0x17]	259080	1			T1	1351		T3	3		T4	719
valid_sources[0x18]	356423	1			T1	1203		T3	38		T4	623
valid_sources[0x19]	280615	1			T1	1325		T3	2		T4	823
valid_sources[0x1a]	257884	1			T1	1335		T3	5		T4	806
valid_sources[0x1b]	252610	1			T1	1298		T3	12		T4	775
valid_sources[0x1c]	255348	1			T1	1348		T3	6		T4	744
valid_sources[0x1d]	248059	1			T1	1259		T3	9		T4	786
valid_sources[0x1e]	370484	1			T1	1318		T3	28		T4	716
valid_sources[0x1f]	256294	1			T1	1179		T3	1		T4	825
valid_sources[0x20]	248595	1			T1	1320		T3	14		T4	827
valid_sources[0x21]	290569	1			T1	1362		T3	9		T4	742
valid_sources[0x22]	288012	1			T1	1331		T3	1		T4	807
valid_sources[0x23]	347233	1			T1	1362		T3	12		T4	717
valid_sources[0x24]	264163	1			T1	1202		T3	4		T4	668
valid_sources[0x25]	301257	1			T1	1285		T3	11		T4	706
valid_sources[0x26]	260497	1			T1	1312		T3	1		T4	814
valid_sources[0x27]	264256	1			T1	1337		T3	7		T4	805
valid_sources[0x28]	298811	1			T1	1359		T3	14		T4	906
valid_sources[0x29]	273303	1			T1	1303		T4	1007		T5	5
valid_sources[0x2a]	301983	1			T1	1268		T3	7		T4	787
valid_sources[0x2b]	296759	1			T1	1192		T3	2		T4	735
valid_sources[0x2c]	270795	1			T1	1250		T3	5		T4	797
valid_sources[0x2d]	293808	1			T1	1312		T3	2		T4	696
valid_sources[0x2e]	281955	1			T1	1340		T3	6		T4	638
valid_sources[0x2f]	354471	1			T1	1293		T3	3		T4	561
valid_sources[0x30]	267561	1			T1	1410		T4	673		T5	4
valid_sources[0x31]	273136	1			T1	1314		T4	806		T5	4
valid_sources[0x32]	249714	1			T1	1274		T3	1		T4	793
valid_sources[0x33]	279755	1			T1	1317		T3	5		T4	854
valid_sources[0x34]	251727	1			T1	1232		T4	691		T5	7
valid_sources[0x35]	257140	1			T1	1222		T4	655		T5	6
valid_sources[0x36]	336153	1			T1	1245		T4	706		T5	2
valid_sources[0x37]	260066	1			T1	1271		T3	2		T4	716
valid_sources[0x38]	263352	1			T1	1397		T3	14		T4	682
valid_sources[0x39]	295187	1			T1	1231		T3	12		T4	830
valid_sources[0x3a]	306819	1			T1	1306		T3	1		T4	657
valid_sources[0x3b]	302611	1			T1	1428		T3	5		T4	896
valid_sources[0x3c]	306699	1			T1	1308		T4	691		T5	7
valid_sources[0x3d]	255467	1			T1	1318		T3	7		T4	818
valid_sources[0x3e]	262986	1			T1	1253		T3	16		T4	633
valid_sources[0x3f]	256894	1			T1	1291		T3	1		T4	776
valid_sources[0x40]	252329	1			T1	1360		T3	5		T4	646
valid_sources[0x41]	291995	1			T1	1394		T3	14		T4	721
valid_sources[0x42]	250333	1			T1	1446		T3	8		T4	866
valid_sources[0x43]	318852	1			T1	1265		T3	21		T4	704
valid_sources[0x44]	256790	1			T1	1346		T3	9		T4	725
valid_sources[0x45]	279979	1			T1	1280		T3	2		T4	758
valid_sources[0x46]	251827	1			T1	1275		T3	5		T4	639
valid_sources[0x47]	293866	1			T1	1348		T3	4		T4	734
valid_sources[0x48]	301442	1			T1	1264		T4	616		T5	4
valid_sources[0x49]	282212	1			T1	1314		T3	13		T4	670
valid_sources[0x4a]	348001	1			T1	1348		T3	8		T4	784
valid_sources[0x4b]	269067	1			T1	1328		T3	1		T4	839
valid_sources[0x4c]	256592	1			T1	1240		T3	11		T4	698
valid_sources[0x4d]	259084	1			T1	1297		T4	759		T5	4
valid_sources[0x4e]	290488	1			T1	1280		T3	1		T4	828
valid_sources[0x4f]	290793	1			T1	1305		T3	7		T4	667
valid_sources[0x50]	269666	1			T1	1308		T3	5		T4	759
valid_sources[0x51]	252778	1			T1	1280		T3	24		T4	620
valid_sources[0x52]	251125	1			T1	1336		T3	5		T4	640
valid_sources[0x53]	255407	1			T1	1388		T3	5		T4	812
valid_sources[0x54]	317661	1			T1	1300		T3	19		T4	732
valid_sources[0x55]	304559	1			T1	1334		T4	710		T5	3
valid_sources[0x56]	271740	1			T1	1288		T4	689		T5	1
valid_sources[0x57]	267352	1			T1	1381		T3	3		T4	766
valid_sources[0x58]	261569	1			T1	1360		T3	8		T4	718
valid_sources[0x59]	277334	1			T1	1219		T3	11		T4	814
valid_sources[0x5a]	329784	1			T1	1252		T3	16		T4	610
valid_sources[0x5b]	312560	1			T1	1438		T3	25		T4	634
valid_sources[0x5c]	319598	1			T1	1172		T3	3		T4	727
valid_sources[0x5d]	244747	1			T1	1304		T3	25		T4	770
valid_sources[0x5e]	255625	1			T1	1271		T3	5		T4	707
valid_sources[0x5f]	314400	1			T1	1220		T3	3		T4	863
valid_sources[0x60]	270278	1			T1	1236		T3	2		T4	710
valid_sources[0x61]	299915	1			T1	1232		T4	745		T5	2
valid_sources[0x62]	254173	1			T1	1291		T3	15		T4	768
valid_sources[0x63]	274004	1			T1	1281		T3	5		T4	729
valid_sources[0x64]	248705	1			T1	1282		T3	11		T4	792
valid_sources[0x65]	337355	1			T1	1379		T3	2		T4	855
valid_sources[0x66]	253741	1			T1	1257		T3	2		T4	823
valid_sources[0x67]	275468	1			T1	1281		T3	3		T4	752
valid_sources[0x68]	358954	1			T1	1286		T3	1		T4	782
valid_sources[0x69]	277599	1			T1	1317		T3	12		T4	745
valid_sources[0x6a]	289181	1			T1	1306		T4	725		T5	2
valid_sources[0x6b]	281290	1			T1	1467		T4	931		T5	4
valid_sources[0x6c]	311237	1			T1	1303		T3	2		T4	737
valid_sources[0x6d]	302375	1			T1	1278		T3	16		T4	638
valid_sources[0x6e]	294181	1			T1	1377		T3	8		T4	780
valid_sources[0x6f]	323803	1			T1	1276		T3	1		T4	686
valid_sources[0x70]	330095	1			T1	1218		T4	820		T5	3
valid_sources[0x71]	257450	1			T1	1337		T3	25		T4	797
valid_sources[0x72]	254373	1			T1	1279		T3	22		T4	747
valid_sources[0x73]	267782	1			T1	1361		T4	855		T5	3
valid_sources[0x74]	414146	1			T1	1360		T3	3		T4	750
valid_sources[0x75]	276162	1			T1	1312		T3	4		T4	787
valid_sources[0x76]	282913	1			T1	1251		T3	2		T4	828
valid_sources[0x77]	294813	1			T1	1290		T3	11		T4	674
valid_sources[0x78]	249521	1			T1	1385		T3	14		T4	704
valid_sources[0x79]	349257	1			T1	1306		T3	2		T4	775
valid_sources[0x7a]	264272	1			T1	1441		T3	2		T4	706
valid_sources[0x7b]	263217	1			T1	1313		T4	776		T5	7
valid_sources[0x7c]	295297	1			T1	1401		T3	1		T4	748
valid_sources[0x7d]	254053	1			T1	1299		T3	16		T4	724
valid_sources[0x7e]	254753	1			T1	1288		T3	31		T4	763
valid_sources[0x7f]	328524	1			T1	1275		T3	7		T4	670
valid_sources[0x80]	268651	1			T1	1325		T3	5		T4	697

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29189948

1

T1

152035

T3

6

T4

86697

values[0x0]

all_enables

biggest_size

14701408

1

T1

75815

T3

41

T4

43021

values[0x1]

all_enables

biggest_size

14692662

1

T1

75980

T3

46

T4

43428

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	36219	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

131662

1

T1

15

T2

1

T4

37

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	49247	1			T4	19		T6	65		T24	19
values[0x0]	57294	1			T1	29		T2	1		T3	3
values[0x1]	61340	1			T1	21		T10	1		T4	42

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	27455	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

140426

1

T1

17

T2

1

T4

45

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	815	1			T20	56		T143	2		T22	28
valid_sources[0x01]	661	1			T1	4		T4	1		T11	1
valid_sources[0x02]	752	1			T4	1		T6	1		T8	2
valid_sources[0x03]	707	1			T6	1		T14	1		T8	1
valid_sources[0x04]	593	1			T4	1		T6	1		T144	1
valid_sources[0x05]	639	1			T6	5		T65	1		T20	14
valid_sources[0x06]	751	1			T6	1		T8	1		T65	1
valid_sources[0x07]	529	1			T8	2		T20	15		T66	5
valid_sources[0x08]	783	1			T1	3		T4	1		T6	4
valid_sources[0x09]	896	1			T1	2		T4	2		T5	1
valid_sources[0x0a]	639	1			T4	1		T36	1		T29	3
valid_sources[0x0b]	661	1			T6	1		T20	46		T72	1
valid_sources[0x0c]	493	1			T8	1		T20	14		T145	1
valid_sources[0x0d]	600	1			T8	1		T20	33		T146	1
valid_sources[0x0e]	690	1			T5	2		T9	2		T28	1
valid_sources[0x0f]	866	1			T1	1		T6	1		T20	70
valid_sources[0x10]	527	1			T1	2		T4	1		T20	14
valid_sources[0x11]	590	1			T51	1		T20	51		T146	3
valid_sources[0x12]	582	1			T6	7		T8	1		T65	2
valid_sources[0x13]	655	1			T8	1		T20	60		T147	1
valid_sources[0x14]	520	1			T1	1		T7	1		T65	1
valid_sources[0x15]	591	1			T6	1		T30	3		T20	59
valid_sources[0x16]	666	1			T20	48		T138	1		T120	1
valid_sources[0x17]	710	1			T6	1		T65	1		T20	19
valid_sources[0x18]	895	1			T39	2		T8	1		T65	2
valid_sources[0x19]	491	1			T6	1		T13	2		T20	29
valid_sources[0x1a]	558	1			T20	36		T146	2		T22	33
valid_sources[0x1b]	582	1			T4	1		T6	2		T7	1
valid_sources[0x1c]	488	1			T6	2		T8	1		T20	7
valid_sources[0x1d]	425	1			T20	5		T67	1		T22	23
valid_sources[0x1e]	532	1			T6	1		T20	63		T66	2
valid_sources[0x1f]	559	1			T1	1		T6	2		T8	1
valid_sources[0x20]	736	1			T4	1		T7	1		T8	2
valid_sources[0x21]	790	1			T9	1		T7	1		T8	1
valid_sources[0x22]	637	1			T6	1		T20	53		T22	24
valid_sources[0x23]	752	1			T11	2		T6	1		T148	1
valid_sources[0x24]	624	1			T65	1		T20	19		T66	2
valid_sources[0x25]	511	1			T33	1		T20	23		T145	1
valid_sources[0x26]	618	1			T1	1		T8	1		T65	1
valid_sources[0x27]	582	1			T39	1		T20	53		T66	2
valid_sources[0x28]	616	1			T4	1		T14	2		T20	35
valid_sources[0x29]	923	1			T4	1		T7	1		T65	2
valid_sources[0x2a]	724	1			T20	5		T67	1		T22	29
valid_sources[0x2b]	625	1			T6	1		T39	7		T20	21
valid_sources[0x2c]	802	1			T65	1		T20	34		T120	3
valid_sources[0x2d]	535	1			T4	2		T11	4		T20	24
valid_sources[0x2e]	1032	1			T37	1		T30	1		T7	1
valid_sources[0x2f]	741	1			T14	1		T65	3		T20	61
valid_sources[0x30]	520	1			T15	1		T149	3		T20	14
valid_sources[0x31]	648	1			T8	1		T65	1		T20	24
valid_sources[0x32]	590	1			T1	3		T4	1		T6	1
valid_sources[0x33]	677	1			T6	1		T20	19		T138	2
valid_sources[0x34]	729	1			T10	1		T6	1		T20	48
valid_sources[0x35]	668	1			T6	2		T8	1		T20	5
valid_sources[0x36]	691	1			T4	2		T20	28		T22	21
valid_sources[0x37]	585	1			T4	1		T6	1		T7	3
valid_sources[0x38]	818	1			T148	1		T9	1		T8	1
valid_sources[0x39]	492	1			T20	8		T67	1		T142	1
valid_sources[0x3a]	544	1			T6	4		T8	1		T20	27
valid_sources[0x3b]	685	1			T4	1		T6	1		T39	7
valid_sources[0x3c]	642	1			T4	1		T20	8		T146	2
valid_sources[0x3d]	607	1			T6	1		T7	1		T20	13
valid_sources[0x3e]	536	1			T6	2		T8	2		T20	22
valid_sources[0x3f]	590	1			T20	95		T120	1		T150	2
valid_sources[0x40]	599	1			T4	1		T9	1		T65	1
valid_sources[0x41]	757	1			T11	1		T37	1		T9	1
valid_sources[0x42]	651	1			T9	2		T20	22		T67	1
valid_sources[0x43]	571	1			T6	4		T7	1		T8	2
valid_sources[0x44]	543	1			T6	2		T9	1		T15	1
valid_sources[0x45]	596	1			T4	1		T6	1		T9	1
valid_sources[0x46]	573	1			T4	1		T57	1		T20	27
valid_sources[0x47]	516	1			T4	1		T14	1		T20	26
valid_sources[0x48]	617	1			T4	1		T14	1		T20	29
valid_sources[0x49]	594	1			T65	1		T20	38		T66	1
valid_sources[0x4a]	513	1			T4	1		T6	2		T8	1
valid_sources[0x4b]	906	1			T6	1		T24	1		T65	1
valid_sources[0x4c]	659	1			T6	2		T16	1		T20	51
valid_sources[0x4d]	783	1			T6	4		T24	12		T7	1
valid_sources[0x4e]	649	1			T11	1		T65	1		T20	13
valid_sources[0x4f]	669	1			T4	1		T65	1		T20	8
valid_sources[0x50]	630	1			T4	1		T6	4		T30	1
valid_sources[0x51]	553	1			T4	1		T65	1		T20	22
valid_sources[0x52]	583	1			T20	54		T138	1		T151	16
valid_sources[0x53]	636	1			T37	1		T8	1		T20	61
valid_sources[0x54]	590	1			T6	5		T20	9		T66	1
valid_sources[0x55]	650	1			T8	1		T20	65		T152	1
valid_sources[0x56]	647	1			T20	52		T151	3		T22	20
valid_sources[0x57]	620	1			T8	1		T20	34		T120	1
valid_sources[0x58]	657	1			T20	30		T146	3		T150	2
valid_sources[0x59]	743	1			T4	1		T20	25		T66	1
valid_sources[0x5a]	658	1			T6	2		T9	1		T31	11
valid_sources[0x5b]	628	1			T6	2		T65	1		T20	21
valid_sources[0x5c]	925	1			T20	9		T66	1		T147	3
valid_sources[0x5d]	566	1			T14	1		T9	1		T20	14
valid_sources[0x5e]	566	1			T1	2		T6	2		T65	1
valid_sources[0x5f]	819	1			T8	1		T65	1		T20	24
valid_sources[0x60]	841	1			T9	1		T8	1		T20	45
valid_sources[0x61]	564	1			T9	1		T7	1		T8	1
valid_sources[0x62]	509	1			T4	1		T11	1		T6	2
valid_sources[0x63]	587	1			T65	2		T20	13		T153	1
valid_sources[0x64]	651	1			T1	1		T6	2		T24	9
valid_sources[0x65]	695	1			T4	1		T6	3		T20	29
valid_sources[0x66]	557	1			T4	1		T11	2		T20	45
valid_sources[0x67]	530	1			T1	1		T4	1		T8	1
valid_sources[0x68]	592	1			T6	2		T20	38		T67	1
valid_sources[0x69]	775	1			T1	2		T6	2		T9	1
valid_sources[0x6a]	654	1			T1	1		T4	2		T6	1
valid_sources[0x6b]	651	1			T4	2		T31	5		T8	1
valid_sources[0x6c]	567	1			T6	1		T7	4		T20	15
valid_sources[0x6d]	505	1			T6	2		T65	1		T20	8
valid_sources[0x6e]	752	1			T144	1		T65	1		T20	58
valid_sources[0x6f]	708	1			T4	1		T6	1		T16	3
valid_sources[0x70]	547	1			T6	1		T34	11		T65	1
valid_sources[0x71]	537	1			T1	1		T9	1		T20	15
valid_sources[0x72]	693	1			T8	2		T65	1		T20	74
valid_sources[0x73]	537	1			T4	1		T65	1		T20	45
valid_sources[0x74]	478	1			T6	2		T20	18		T22	26
valid_sources[0x75]	605	1			T1	1		T6	2		T32	3
valid_sources[0x76]	559	1			T8	1		T65	1		T20	3
valid_sources[0x77]	912	1			T65	1		T16	1		T20	47
valid_sources[0x78]	659	1			T6	1		T8	1		T65	1
valid_sources[0x79]	700	1			T6	1		T20	22		T66	4
valid_sources[0x7a]	822	1			T4	2		T6	1		T65	1
valid_sources[0x7b]	638	1			T6	1		T9	1		T65	1
valid_sources[0x7c]	562	1			T6	2		T65	2		T20	19
valid_sources[0x7d]	545	1			T4	1		T11	6		T9	2
valid_sources[0x7e]	788	1			T8	1		T20	32		T67	2
valid_sources[0x7f]	757	1			T65	1		T20	21		T146	1
valid_sources[0x80]	546	1			T2	1		T4	2		T20	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

36174

1

T4

11

T6

27

T24

10

values[0x0]

all_enables

biggest_size

48710

1

T1

12

T2

1

T4

19

values[0x1]

all_enables

biggest_size

46778

1

T1

3

T4

7

T11

9