Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
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Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block] 100.00 1 100 1 64 64




Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
partial 13562707 1 T1 30301 T3 1947 T4 13749
full_word 53957649 1 T1 303830 T3 93 T4 138714



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 67520026 1 T1 334131 T3 2040 T4 152463
auto[TlIntgErrCmd] 116 1 T60 9 T61 9 T62 3
auto[TlIntgErrData] 107 1 T60 7 T61 4 T62 2
auto[TlIntgErrBoth] 107 1 T60 4 T61 7 T62 5



Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 31148697 1 T1 167241 T3 958 T4 57335
auto[1] 36371659 1 T1 166890 T3 1082 T4 95128



Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 6504950 1 T1 15206 T3 952 T4 5070
auto[TlIntgErrNone] partial auto[1] 7057448 1 T1 15095 T3 995 T4 8679
auto[TlIntgErrNone] full_word auto[0] 24643606 1 T1 152035 T3 6 T4 52265
auto[TlIntgErrNone] full_word auto[1] 29314022 1 T1 151795 T3 87 T4 86449
auto[TlIntgErrCmd] partial auto[0] 42 1 T60 3 T61 2 T62 1
auto[TlIntgErrCmd] partial auto[1] 66 1 T60 4 T61 7 T62 2
auto[TlIntgErrCmd] full_word auto[0] 2 1 T130 1 T131 1 - -
auto[TlIntgErrCmd] full_word auto[1] 6 1 T60 2 T125 1 T124 1
auto[TlIntgErrData] partial auto[0] 49 1 T60 4 T61 1 T121 2
auto[TlIntgErrData] partial auto[1] 50 1 T60 3 T61 3 T62 2
auto[TlIntgErrData] full_word auto[0] 5 1 T130 1 T124 1 T128 1
auto[TlIntgErrData] full_word auto[1] 3 1 T129 1 T132 1 T133 1
auto[TlIntgErrBoth] partial auto[0] 41 1 T60 2 T61 2 T62 3
auto[TlIntgErrBoth] partial auto[1] 61 1 T60 2 T61 5 T62 1
auto[TlIntgErrBoth] full_word auto[0] 2 1 T129 1 T122 1 - -
auto[TlIntgErrBoth] full_word auto[1] 3 1 T62 1 T134 1 T135 1

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