Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	719915	1			T3	55		T4	20		T5	104
auto[1]	10842603	1			T1	64429		T3	160		T4	383
auto[2]	588818	1			T3	31		T4	27		T5	79
auto[3]	10732045	1			T1	64501		T3	189		T4	382

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14656691	1			T1	106567		T4	609		T11	13030
auto[1]	2208522	1			T1	10694		T3	6		T4	68
auto[2]	2230798	1			T1	10611		T3	16		T4	122
auto[3]	3787370	1			T1	1058		T3	413		T4	13

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9172699

1

T1

128819

T3

435

T4

811

auto[1]

13710682

1

T1

111

T4

1

T5

3

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	338137	1			T4	12		T6	1869		T39	28
auto[0]	auto[0]	auto[1]	34903	1			T4	4		T5	3		T6	209
auto[0]	auto[0]	auto[2]	35067	1			T4	3		T5	1		T6	166
auto[0]	auto[0]	auto[3]	10783	1			T3	55		T4	1		T5	99
auto[0]	auto[1]	auto[0]	3435533	1			T1	53232		T4	310		T11	6499
auto[0]	auto[1]	auto[1]	363160	1			T1	5340		T3	2		T4	46
auto[0]	auto[1]	auto[2]	350951	1			T1	5253		T3	4		T4	24
auto[0]	auto[1]	auto[3]	78498	1			T1	532		T3	154		T4	2
auto[0]	auto[2]	auto[0]	280870	1			T6	1674		T24	1726		T57	983
auto[0]	auto[2]	auto[1]	29240	1			T5	13		T6	157		T24	168
auto[0]	auto[2]	auto[2]	32469	1			T4	25		T5	2		T6	120
auto[0]	auto[2]	auto[3]	9067	1			T3	31		T4	2		T5	63
auto[0]	auto[3]	auto[0]	3386997	1			T1	53241		T4	286		T11	6519
auto[0]	auto[3]	auto[1]	344229	1			T1	5351		T3	4		T4	18
auto[0]	auto[3]	auto[2]	362899	1			T1	5345		T3	12		T4	70
auto[0]	auto[3]	auto[3]	79896	1			T1	525		T3	173		T4	8
auto[1]	auto[0]	auto[0]	10122	1			T6	3		T24	1		T100	726
auto[1]	auto[0]	auto[1]	44856	1			T100	3488		T139	2		T103	747
auto[1]	auto[0]	auto[2]	44540	1			T100	3428		T103	722		T140	786
auto[1]	auto[0]	auto[3]	201507	1			T5	1		T74	2		T100	15595
auto[1]	auto[1]	auto[0]	3599013	1			T1	60		T4	1		T11	8
auto[1]	auto[1]	auto[1]	689474	1			T1	2		T11	1		T35	6627
auto[1]	auto[1]	auto[2]	685861	1			T1	9		T11	1		T35	6190
auto[1]	auto[1]	auto[3]	1640113	1			T1	1		T35	668		T37	461
auto[1]	auto[2]	auto[0]	7180	1			T6	1		T24	1		T57	1
auto[1]	auto[2]	auto[1]	31097	1			T100	3298		T120	1		T141	2
auto[1]	auto[2]	auto[2]	36427	1			T6	1		T24	1		T100	2336
auto[1]	auto[2]	auto[3]	162468	1			T5	1		T74	1		T100	10382
auto[1]	auto[3]	auto[0]	3598839	1			T1	34		T11	4		T13	1
auto[1]	auto[3]	auto[1]	671563	1			T1	1		T11	1		T35	6426
auto[1]	auto[3]	auto[2]	682584	1			T1	4		T11	2		T35	6415
auto[1]	auto[3]	auto[3]	1605038	1			T5	1		T35	603		T37	460