Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	315839377	188412	0	0
ctrl_regwen_rd_A	315839377	2970	0	0
exec_rd_A	315839377	3055	0	0
exec_regwen_rd_A	315839377	3039	0	0
readback_rd_A	315839377	1980	0	0
readback_regwen_rd_A	315839377	1387	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315839377	188412	0	0
T20	286695	14481	0	0
T21	681260	0	0	0
T22	0	8615	0	0
T23	0	2034	0	0
T40	0	2702	0	0
T41	0	3583	0	0
T53	0	5750	0	0
T54	0	5377	0	0
T66	127499	0	0	0
T67	53528	0	0	0
T68	0	829	0	0
T69	0	1706	0	0
T70	0	9961	0	0
T71	52834	0	0	0
T72	57996	0	0	0
T73	1014	0	0	0
T74	16085	0	0	0
T75	27506	0	0	0
T76	12689	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315839377	2970	0	0
T23	69579	197	0	0
T40	0	128	0	0
T42	0	204	0	0
T68	0	97	0	0
T69	0	136	0	0
T106	0	61	0	0
T107	0	215	0	0
T108	0	95	0	0
T109	0	296	0	0
T110	0	77	0	0
T111	29094	0	0	0
T112	355906	0	0	0
T113	206088	0	0	0
T114	13060	0	0	0
T115	2946	0	0	0
T116	212528	0	0	0
T117	307005	0	0	0
T118	29960	0	0	0
T119	15166	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315839377	3055	0	0
T23	69579	140	0	0
T40	0	137	0	0
T42	0	225	0	0
T68	0	82	0	0
T69	0	174	0	0
T106	0	78	0	0
T107	0	146	0	0
T108	0	84	0	0
T109	0	311	0	0
T110	0	96	0	0
T111	29094	0	0	0
T112	355906	0	0	0
T113	206088	0	0	0
T114	13060	0	0	0
T115	2946	0	0	0
T116	212528	0	0	0
T117	307005	0	0	0
T118	29960	0	0	0
T119	15166	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315839377	3039	0	0
T23	69579	153	0	0
T40	0	171	0	0
T42	0	298	0	0
T68	0	81	0	0
T69	0	164	0	0
T106	0	87	0	0
T107	0	173	0	0
T108	0	66	0	0
T109	0	296	0	0
T110	0	84	0	0
T111	29094	0	0	0
T112	355906	0	0	0
T113	206088	0	0	0
T114	13060	0	0	0
T115	2946	0	0	0
T116	212528	0	0	0
T117	307005	0	0	0
T118	29960	0	0	0
T119	15166	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315839377	1980	0	0
T23	69579	200	0	0
T40	0	146	0	0
T42	0	404	0	0
T68	0	60	0	0
T69	0	200	0	0
T106	0	25	0	0
T107	0	131	0	0
T108	0	60	0	0
T109	0	296	0	0
T110	0	77	0	0
T111	29094	0	0	0
T112	355906	0	0	0
T113	206088	0	0	0
T114	13060	0	0	0
T115	2946	0	0	0
T116	212528	0	0	0
T117	307005	0	0	0
T118	29960	0	0	0
T119	15166	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315839377	1387	0	0
T23	69579	94	0	0
T40	0	109	0	0
T42	0	249	0	0
T68	0	72	0	0
T69	0	101	0	0
T106	0	47	0	0
T107	0	169	0	0
T108	0	68	0	0
T109	0	180	0	0
T110	0	54	0	0
T111	29094	0	0	0
T112	355906	0	0	0
T113	206088	0	0	0
T114	13060	0	0	0
T115	2946	0	0	0
T116	212528	0	0	0
T117	307005	0	0	0
T118	29960	0	0	0
T119	15166	0	0	0