SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.90 | 100.00 | 88.89 | 100.00 | 100.00 | 70.59 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
89.00 | 100.00 | 100.00 | 100.00 | 95.00 | 50.00 | u_tlul_lc_gate |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 2 | 2 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1782 | 1782 | 0 | 0 |
OutputsKnown_A | 629221296 | 628981038 | 0 | 0 |
gen_flops.OutputDelay_A | 314610648 | 314477510 | 0 | 2673 |
gen_no_flops.OutputDelay_A | 314610648 | 314490519 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1782 | 1782 | 0 | 0 |
T1 | 2 | 2 | 0 | 0 |
T2 | 2 | 2 | 0 | 0 |
T3 | 2 | 2 | 0 | 0 |
T4 | 2 | 2 | 0 | 0 |
T5 | 2 | 2 | 0 | 0 |
T6 | 2 | 2 | 0 | 0 |
T10 | 2 | 2 | 0 | 0 |
T11 | 2 | 2 | 0 | 0 |
T12 | 2 | 2 | 0 | 0 |
T13 | 2 | 2 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 629221296 | 628981038 | 0 | 0 |
T1 | 1249838 | 1249738 | 0 | 0 |
T2 | 6374 | 6208 | 0 | 0 |
T3 | 28724 | 28578 | 0 | 0 |
T4 | 252456 | 252446 | 0 | 0 |
T5 | 19230 | 19106 | 0 | 0 |
T6 | 530562 | 530290 | 0 | 0 |
T10 | 4696 | 4578 | 0 | 0 |
T11 | 697528 | 697404 | 0 | 0 |
T12 | 3948 | 3836 | 0 | 0 |
T13 | 12858 | 12748 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 314610648 | 314477510 | 0 | 2673 |
T1 | 624919 | 624866 | 0 | 3 |
T2 | 3187 | 3101 | 0 | 3 |
T3 | 14362 | 14286 | 0 | 3 |
T4 | 126228 | 126223 | 0 | 3 |
T5 | 9615 | 9550 | 0 | 3 |
T6 | 265281 | 265129 | 0 | 3 |
T10 | 2348 | 2286 | 0 | 3 |
T11 | 348764 | 348699 | 0 | 3 |
T12 | 1974 | 1915 | 0 | 3 |
T13 | 6429 | 6371 | 0 | 3 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 314610648 | 314490519 | 0 | 0 |
T1 | 624919 | 624869 | 0 | 0 |
T2 | 3187 | 3104 | 0 | 0 |
T3 | 14362 | 14289 | 0 | 0 |
T4 | 126228 | 126223 | 0 | 0 |
T5 | 9615 | 9553 | 0 | 0 |
T6 | 265281 | 265145 | 0 | 0 |
T10 | 2348 | 2289 | 0 | 0 |
T11 | 348764 | 348702 | 0 | 0 |
T12 | 1974 | 1918 | 0 | 0 |
T13 | 6429 | 6374 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 891 | 891 | 0 | 0 |
OutputsKnown_A | 314610648 | 314490519 | 0 | 0 |
gen_flops.OutputDelay_A | 314610648 | 314477510 | 0 | 2673 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 891 | 891 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 314610648 | 314490519 | 0 | 0 |
T1 | 624919 | 624869 | 0 | 0 |
T2 | 3187 | 3104 | 0 | 0 |
T3 | 14362 | 14289 | 0 | 0 |
T4 | 126228 | 126223 | 0 | 0 |
T5 | 9615 | 9553 | 0 | 0 |
T6 | 265281 | 265145 | 0 | 0 |
T10 | 2348 | 2289 | 0 | 0 |
T11 | 348764 | 348702 | 0 | 0 |
T12 | 1974 | 1918 | 0 | 0 |
T13 | 6429 | 6374 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 314610648 | 314477510 | 0 | 2673 |
T1 | 624919 | 624866 | 0 | 3 |
T2 | 3187 | 3101 | 0 | 3 |
T3 | 14362 | 14286 | 0 | 3 |
T4 | 126228 | 126223 | 0 | 3 |
T5 | 9615 | 9550 | 0 | 3 |
T6 | 265281 | 265129 | 0 | 3 |
T10 | 2348 | 2286 | 0 | 3 |
T11 | 348764 | 348699 | 0 | 3 |
T12 | 1974 | 1915 | 0 | 3 |
T13 | 6429 | 6371 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 891 | 891 | 0 | 0 |
OutputsKnown_A | 314610648 | 314490519 | 0 | 0 |
gen_no_flops.OutputDelay_A | 314610648 | 314490519 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 891 | 891 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 314610648 | 314490519 | 0 | 0 |
T1 | 624919 | 624869 | 0 | 0 |
T2 | 3187 | 3104 | 0 | 0 |
T3 | 14362 | 14289 | 0 | 0 |
T4 | 126228 | 126223 | 0 | 0 |
T5 | 9615 | 9553 | 0 | 0 |
T6 | 265281 | 265145 | 0 | 0 |
T10 | 2348 | 2289 | 0 | 0 |
T11 | 348764 | 348702 | 0 | 0 |
T12 | 1974 | 1918 | 0 | 0 |
T13 | 6429 | 6374 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 314610648 | 314490519 | 0 | 0 |
T1 | 624919 | 624869 | 0 | 0 |
T2 | 3187 | 3104 | 0 | 0 |
T3 | 14362 | 14289 | 0 | 0 |
T4 | 126228 | 126223 | 0 | 0 |
T5 | 9615 | 9553 | 0 | 0 |
T6 | 265281 | 265145 | 0 | 0 |
T10 | 2348 | 2289 | 0 | 0 |
T11 | 348764 | 348702 | 0 | 0 |
T12 | 1974 | 1918 | 0 | 0 |
T13 | 6429 | 6374 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |