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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.95 99.16 94.27 99.72 100.00 95.95 99.12 97.44


Total test records in report: 1031
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html

T545 /workspace/coverage/default/14.sram_ctrl_stress_all.1885813240 Jul 26 07:12:02 PM PDT 24 Jul 26 07:29:01 PM PDT 24 14441800068 ps
T546 /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.551764040 Jul 26 07:13:21 PM PDT 24 Jul 26 07:15:53 PM PDT 24 310217504 ps
T547 /workspace/coverage/default/19.sram_ctrl_access_during_key_req.3445791289 Jul 26 07:12:39 PM PDT 24 Jul 26 07:25:34 PM PDT 24 10210448721 ps
T548 /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.654890663 Jul 26 07:12:51 PM PDT 24 Jul 26 07:15:21 PM PDT 24 591848073 ps
T549 /workspace/coverage/default/19.sram_ctrl_multiple_keys.926491840 Jul 26 07:12:29 PM PDT 24 Jul 26 07:15:53 PM PDT 24 10230889932 ps
T550 /workspace/coverage/default/20.sram_ctrl_stress_pipeline.3683281528 Jul 26 07:12:52 PM PDT 24 Jul 26 07:19:04 PM PDT 24 15322087566 ps
T551 /workspace/coverage/default/34.sram_ctrl_ram_cfg.1996402074 Jul 26 07:15:17 PM PDT 24 Jul 26 07:15:17 PM PDT 24 27897601 ps
T552 /workspace/coverage/default/3.sram_ctrl_mem_partial_access.841662099 Jul 26 07:11:03 PM PDT 24 Jul 26 07:11:09 PM PDT 24 610571981 ps
T553 /workspace/coverage/default/48.sram_ctrl_alert_test.3924747909 Jul 26 07:18:16 PM PDT 24 Jul 26 07:18:16 PM PDT 24 10662837 ps
T554 /workspace/coverage/default/44.sram_ctrl_partial_access.3285434834 Jul 26 07:17:19 PM PDT 24 Jul 26 07:19:17 PM PDT 24 1723645140 ps
T555 /workspace/coverage/default/28.sram_ctrl_regwen.3079254044 Jul 26 07:14:11 PM PDT 24 Jul 26 07:24:04 PM PDT 24 12298665589 ps
T556 /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.771614465 Jul 26 07:17:28 PM PDT 24 Jul 26 07:23:48 PM PDT 24 138658140805 ps
T557 /workspace/coverage/default/13.sram_ctrl_access_during_key_req.3710559672 Jul 26 07:11:54 PM PDT 24 Jul 26 07:39:20 PM PDT 24 15252829207 ps
T558 /workspace/coverage/default/23.sram_ctrl_mem_partial_access.830800613 Jul 26 07:13:22 PM PDT 24 Jul 26 07:13:28 PM PDT 24 303651324 ps
T559 /workspace/coverage/default/6.sram_ctrl_mem_partial_access.1318488652 Jul 26 07:11:09 PM PDT 24 Jul 26 07:11:14 PM PDT 24 365015437 ps
T560 /workspace/coverage/default/17.sram_ctrl_stress_pipeline.198364099 Jul 26 07:12:17 PM PDT 24 Jul 26 07:18:04 PM PDT 24 3626178356 ps
T561 /workspace/coverage/default/38.sram_ctrl_mem_walk.87499392 Jul 26 07:16:10 PM PDT 24 Jul 26 07:16:19 PM PDT 24 562018202 ps
T562 /workspace/coverage/default/37.sram_ctrl_access_during_key_req.718029599 Jul 26 07:15:49 PM PDT 24 Jul 26 07:24:35 PM PDT 24 1983877783 ps
T563 /workspace/coverage/default/11.sram_ctrl_ram_cfg.2933294582 Jul 26 07:11:38 PM PDT 24 Jul 26 07:11:38 PM PDT 24 50394629 ps
T564 /workspace/coverage/default/43.sram_ctrl_mem_walk.4111567472 Jul 26 07:17:12 PM PDT 24 Jul 26 07:17:18 PM PDT 24 693747838 ps
T565 /workspace/coverage/default/7.sram_ctrl_executable.1151037509 Jul 26 07:11:13 PM PDT 24 Jul 26 07:31:12 PM PDT 24 15935971803 ps
T566 /workspace/coverage/default/11.sram_ctrl_lc_escalation.3823931352 Jul 26 07:11:39 PM PDT 24 Jul 26 07:11:46 PM PDT 24 672670443 ps
T567 /workspace/coverage/default/15.sram_ctrl_mem_partial_access.2249423550 Jul 26 07:12:00 PM PDT 24 Jul 26 07:12:03 PM PDT 24 126485219 ps
T568 /workspace/coverage/default/16.sram_ctrl_mem_partial_access.205189117 Jul 26 07:12:10 PM PDT 24 Jul 26 07:12:14 PM PDT 24 262694211 ps
T569 /workspace/coverage/default/42.sram_ctrl_bijection.1170753418 Jul 26 07:16:44 PM PDT 24 Jul 26 07:17:45 PM PDT 24 5309932217 ps
T570 /workspace/coverage/default/41.sram_ctrl_alert_test.25596698 Jul 26 07:16:44 PM PDT 24 Jul 26 07:16:44 PM PDT 24 13903509 ps
T571 /workspace/coverage/default/23.sram_ctrl_regwen.1207150654 Jul 26 07:13:11 PM PDT 24 Jul 26 07:22:38 PM PDT 24 7610743780 ps
T572 /workspace/coverage/default/29.sram_ctrl_multiple_keys.2108906955 Jul 26 07:14:15 PM PDT 24 Jul 26 07:31:12 PM PDT 24 9893796564 ps
T573 /workspace/coverage/default/30.sram_ctrl_multiple_keys.1770321233 Jul 26 07:14:21 PM PDT 24 Jul 26 07:20:10 PM PDT 24 4347092754 ps
T574 /workspace/coverage/default/25.sram_ctrl_smoke.46890911 Jul 26 07:13:36 PM PDT 24 Jul 26 07:13:51 PM PDT 24 5287859547 ps
T575 /workspace/coverage/default/39.sram_ctrl_mem_walk.3800713812 Jul 26 07:16:24 PM PDT 24 Jul 26 07:16:30 PM PDT 24 348086294 ps
T576 /workspace/coverage/default/25.sram_ctrl_stress_all.2335441740 Jul 26 07:13:48 PM PDT 24 Jul 26 08:24:38 PM PDT 24 50625912249 ps
T577 /workspace/coverage/default/15.sram_ctrl_access_during_key_req.1102233720 Jul 26 07:12:01 PM PDT 24 Jul 26 07:27:15 PM PDT 24 8471483524 ps
T578 /workspace/coverage/default/18.sram_ctrl_ram_cfg.3246225514 Jul 26 07:12:29 PM PDT 24 Jul 26 07:12:30 PM PDT 24 74385473 ps
T579 /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.2336039570 Jul 26 07:18:23 PM PDT 24 Jul 26 07:18:57 PM PDT 24 4425128077 ps
T580 /workspace/coverage/default/6.sram_ctrl_ram_cfg.3648314109 Jul 26 07:11:12 PM PDT 24 Jul 26 07:11:13 PM PDT 24 48452323 ps
T581 /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.4067734406 Jul 26 07:17:59 PM PDT 24 Jul 26 07:18:01 PM PDT 24 39862380 ps
T582 /workspace/coverage/default/7.sram_ctrl_partial_access.3038881267 Jul 26 07:11:14 PM PDT 24 Jul 26 07:12:26 PM PDT 24 1127353614 ps
T583 /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.3070022839 Jul 26 07:14:10 PM PDT 24 Jul 26 07:14:36 PM PDT 24 1407784918 ps
T584 /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.1798069013 Jul 26 07:11:41 PM PDT 24 Jul 26 07:11:50 PM PDT 24 943441616 ps
T585 /workspace/coverage/default/39.sram_ctrl_stress_pipeline.755248364 Jul 26 07:16:09 PM PDT 24 Jul 26 07:19:29 PM PDT 24 3045219983 ps
T586 /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.917648687 Jul 26 07:18:14 PM PDT 24 Jul 26 07:18:16 PM PDT 24 132920998 ps
T587 /workspace/coverage/default/7.sram_ctrl_alert_test.413101538 Jul 26 07:11:10 PM PDT 24 Jul 26 07:11:11 PM PDT 24 21026145 ps
T588 /workspace/coverage/default/43.sram_ctrl_max_throughput.3492211993 Jul 26 07:17:01 PM PDT 24 Jul 26 07:19:35 PM PDT 24 134838447 ps
T589 /workspace/coverage/default/31.sram_ctrl_stress_pipeline.2009252883 Jul 26 07:14:33 PM PDT 24 Jul 26 07:17:21 PM PDT 24 1682072176 ps
T590 /workspace/coverage/default/13.sram_ctrl_bijection.2590288690 Jul 26 07:11:48 PM PDT 24 Jul 26 07:12:34 PM PDT 24 912069116 ps
T591 /workspace/coverage/default/41.sram_ctrl_executable.1074974321 Jul 26 07:16:37 PM PDT 24 Jul 26 07:29:19 PM PDT 24 8528495369 ps
T592 /workspace/coverage/default/26.sram_ctrl_mem_walk.3893363821 Jul 26 07:13:48 PM PDT 24 Jul 26 07:13:59 PM PDT 24 174819201 ps
T593 /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.3703712251 Jul 26 07:11:22 PM PDT 24 Jul 26 07:17:08 PM PDT 24 84468010547 ps
T594 /workspace/coverage/default/30.sram_ctrl_stress_all.728904119 Jul 26 07:14:41 PM PDT 24 Jul 26 07:31:16 PM PDT 24 47050054318 ps
T595 /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.244981606 Jul 26 07:11:28 PM PDT 24 Jul 26 07:11:30 PM PDT 24 46957000 ps
T596 /workspace/coverage/default/0.sram_ctrl_bijection.1141640962 Jul 26 07:10:31 PM PDT 24 Jul 26 07:10:57 PM PDT 24 4902491910 ps
T597 /workspace/coverage/default/5.sram_ctrl_stress_pipeline.1993259554 Jul 26 07:10:56 PM PDT 24 Jul 26 07:14:16 PM PDT 24 3981503378 ps
T598 /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.3923643736 Jul 26 07:17:21 PM PDT 24 Jul 26 07:25:10 PM PDT 24 17904948444 ps
T599 /workspace/coverage/default/39.sram_ctrl_partial_access.4040486759 Jul 26 07:16:09 PM PDT 24 Jul 26 07:16:19 PM PDT 24 742521061 ps
T600 /workspace/coverage/default/25.sram_ctrl_regwen.89506654 Jul 26 07:13:35 PM PDT 24 Jul 26 07:22:11 PM PDT 24 19927733280 ps
T601 /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.3175303317 Jul 26 07:13:09 PM PDT 24 Jul 26 07:13:26 PM PDT 24 286583928 ps
T602 /workspace/coverage/default/28.sram_ctrl_mem_partial_access.2201295160 Jul 26 07:14:12 PM PDT 24 Jul 26 07:14:18 PM PDT 24 702325958 ps
T603 /workspace/coverage/default/5.sram_ctrl_executable.1192730495 Jul 26 07:11:03 PM PDT 24 Jul 26 07:30:19 PM PDT 24 3112127285 ps
T604 /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.3333532477 Jul 26 07:14:10 PM PDT 24 Jul 26 07:15:08 PM PDT 24 121761164 ps
T605 /workspace/coverage/default/46.sram_ctrl_lc_escalation.1844260292 Jul 26 07:17:36 PM PDT 24 Jul 26 07:17:38 PM PDT 24 126939234 ps
T606 /workspace/coverage/default/2.sram_ctrl_ram_cfg.385638789 Jul 26 07:10:42 PM PDT 24 Jul 26 07:10:43 PM PDT 24 86219153 ps
T17 /workspace/coverage/default/0.sram_ctrl_sec_cm.3970540084 Jul 26 07:10:32 PM PDT 24 Jul 26 07:10:36 PM PDT 24 945038209 ps
T607 /workspace/coverage/default/44.sram_ctrl_max_throughput.115820664 Jul 26 07:17:23 PM PDT 24 Jul 26 07:17:41 PM PDT 24 76557960 ps
T608 /workspace/coverage/default/49.sram_ctrl_max_throughput.2809495175 Jul 26 07:18:17 PM PDT 24 Jul 26 07:19:28 PM PDT 24 1438756281 ps
T609 /workspace/coverage/default/3.sram_ctrl_mem_walk.563186245 Jul 26 07:10:57 PM PDT 24 Jul 26 07:11:03 PM PDT 24 909847537 ps
T610 /workspace/coverage/default/1.sram_ctrl_multiple_keys.2812317525 Jul 26 07:10:33 PM PDT 24 Jul 26 07:30:24 PM PDT 24 107221625033 ps
T611 /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.3901233500 Jul 26 07:14:35 PM PDT 24 Jul 26 07:14:39 PM PDT 24 174417494 ps
T612 /workspace/coverage/default/26.sram_ctrl_lc_escalation.1401989584 Jul 26 07:13:48 PM PDT 24 Jul 26 07:13:51 PM PDT 24 212014146 ps
T613 /workspace/coverage/default/5.sram_ctrl_smoke.3940387895 Jul 26 07:10:57 PM PDT 24 Jul 26 07:11:05 PM PDT 24 1597012821 ps
T614 /workspace/coverage/default/47.sram_ctrl_mem_partial_access.3240634233 Jul 26 07:18:01 PM PDT 24 Jul 26 07:18:07 PM PDT 24 720190913 ps
T615 /workspace/coverage/default/15.sram_ctrl_alert_test.1791920165 Jul 26 07:12:00 PM PDT 24 Jul 26 07:12:02 PM PDT 24 44472265 ps
T616 /workspace/coverage/default/30.sram_ctrl_ram_cfg.4058835358 Jul 26 07:14:36 PM PDT 24 Jul 26 07:14:37 PM PDT 24 82871122 ps
T617 /workspace/coverage/default/4.sram_ctrl_max_throughput.2713110461 Jul 26 07:10:57 PM PDT 24 Jul 26 07:12:35 PM PDT 24 235601250 ps
T618 /workspace/coverage/default/2.sram_ctrl_bijection.1896451296 Jul 26 07:10:42 PM PDT 24 Jul 26 07:11:13 PM PDT 24 10062062374 ps
T619 /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1271153183 Jul 26 07:11:04 PM PDT 24 Jul 26 07:16:16 PM PDT 24 11536081312 ps
T620 /workspace/coverage/default/13.sram_ctrl_lc_escalation.1390176268 Jul 26 07:11:50 PM PDT 24 Jul 26 07:11:57 PM PDT 24 505478398 ps
T621 /workspace/coverage/default/11.sram_ctrl_alert_test.869362023 Jul 26 07:11:35 PM PDT 24 Jul 26 07:11:36 PM PDT 24 14810798 ps
T622 /workspace/coverage/default/20.sram_ctrl_stress_all.1787554982 Jul 26 07:12:52 PM PDT 24 Jul 26 08:02:51 PM PDT 24 220714705138 ps
T623 /workspace/coverage/default/38.sram_ctrl_partial_access.647498487 Jul 26 07:15:58 PM PDT 24 Jul 26 07:16:05 PM PDT 24 125552878 ps
T624 /workspace/coverage/default/26.sram_ctrl_alert_test.4046784050 Jul 26 07:13:51 PM PDT 24 Jul 26 07:13:52 PM PDT 24 64709352 ps
T625 /workspace/coverage/default/27.sram_ctrl_max_throughput.3026005754 Jul 26 07:14:02 PM PDT 24 Jul 26 07:14:13 PM PDT 24 65841474 ps
T626 /workspace/coverage/default/35.sram_ctrl_alert_test.703282789 Jul 26 07:15:39 PM PDT 24 Jul 26 07:15:39 PM PDT 24 29796819 ps
T627 /workspace/coverage/default/7.sram_ctrl_stress_all.264016332 Jul 26 07:11:10 PM PDT 24 Jul 26 07:43:17 PM PDT 24 37868858143 ps
T628 /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.1348142962 Jul 26 07:13:36 PM PDT 24 Jul 26 07:29:58 PM PDT 24 1736135361 ps
T629 /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.3787648817 Jul 26 07:16:17 PM PDT 24 Jul 26 07:18:13 PM PDT 24 265398731 ps
T630 /workspace/coverage/default/42.sram_ctrl_stress_all.2365100084 Jul 26 07:17:01 PM PDT 24 Jul 26 08:27:49 PM PDT 24 36705822809 ps
T631 /workspace/coverage/default/2.sram_ctrl_regwen.3469121804 Jul 26 07:10:42 PM PDT 24 Jul 26 07:17:31 PM PDT 24 1747604453 ps
T632 /workspace/coverage/default/33.sram_ctrl_max_throughput.1159251165 Jul 26 07:14:57 PM PDT 24 Jul 26 07:15:01 PM PDT 24 93448482 ps
T633 /workspace/coverage/default/49.sram_ctrl_stress_all.465716188 Jul 26 07:18:26 PM PDT 24 Jul 26 07:51:39 PM PDT 24 10553717466 ps
T634 /workspace/coverage/default/37.sram_ctrl_lc_escalation.3064180699 Jul 26 07:15:50 PM PDT 24 Jul 26 07:15:54 PM PDT 24 885378082 ps
T635 /workspace/coverage/default/9.sram_ctrl_partial_access.730735695 Jul 26 07:11:21 PM PDT 24 Jul 26 07:12:22 PM PDT 24 394428606 ps
T636 /workspace/coverage/default/21.sram_ctrl_multiple_keys.3978428362 Jul 26 07:12:52 PM PDT 24 Jul 26 07:32:47 PM PDT 24 2705349843 ps
T637 /workspace/coverage/default/18.sram_ctrl_access_during_key_req.1651105808 Jul 26 07:12:32 PM PDT 24 Jul 26 07:28:13 PM PDT 24 10500377587 ps
T638 /workspace/coverage/default/26.sram_ctrl_ram_cfg.2464082790 Jul 26 07:13:50 PM PDT 24 Jul 26 07:13:51 PM PDT 24 30336995 ps
T639 /workspace/coverage/default/4.sram_ctrl_bijection.1588360707 Jul 26 07:10:56 PM PDT 24 Jul 26 07:11:29 PM PDT 24 2854901632 ps
T640 /workspace/coverage/default/7.sram_ctrl_mem_walk.2339529717 Jul 26 07:11:10 PM PDT 24 Jul 26 07:11:16 PM PDT 24 238223497 ps
T641 /workspace/coverage/default/42.sram_ctrl_alert_test.942884766 Jul 26 07:17:01 PM PDT 24 Jul 26 07:17:02 PM PDT 24 33023865 ps
T642 /workspace/coverage/default/37.sram_ctrl_smoke.1214412936 Jul 26 07:15:51 PM PDT 24 Jul 26 07:16:36 PM PDT 24 426912282 ps
T643 /workspace/coverage/default/44.sram_ctrl_bijection.2794556180 Jul 26 07:17:22 PM PDT 24 Jul 26 07:18:40 PM PDT 24 4447652346 ps
T644 /workspace/coverage/default/40.sram_ctrl_stress_all.3318438645 Jul 26 07:16:35 PM PDT 24 Jul 26 07:31:41 PM PDT 24 78499730667 ps
T645 /workspace/coverage/default/15.sram_ctrl_stress_pipeline.1992901573 Jul 26 07:11:59 PM PDT 24 Jul 26 07:16:45 PM PDT 24 11836084448 ps
T646 /workspace/coverage/default/31.sram_ctrl_stress_all.3195580374 Jul 26 07:14:47 PM PDT 24 Jul 26 07:53:09 PM PDT 24 97301446666 ps
T647 /workspace/coverage/default/15.sram_ctrl_ram_cfg.3342220936 Jul 26 07:12:03 PM PDT 24 Jul 26 07:12:04 PM PDT 24 31779648 ps
T648 /workspace/coverage/default/18.sram_ctrl_multiple_keys.353608912 Jul 26 07:12:18 PM PDT 24 Jul 26 07:27:57 PM PDT 24 21906049937 ps
T649 /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.2549873568 Jul 26 07:11:56 PM PDT 24 Jul 26 07:16:50 PM PDT 24 4115499604 ps
T650 /workspace/coverage/default/29.sram_ctrl_stress_all.2115878018 Jul 26 07:14:24 PM PDT 24 Jul 26 08:17:42 PM PDT 24 11183060034 ps
T651 /workspace/coverage/default/36.sram_ctrl_bijection.4194840063 Jul 26 07:15:40 PM PDT 24 Jul 26 07:16:11 PM PDT 24 9698517067 ps
T652 /workspace/coverage/default/9.sram_ctrl_alert_test.2645000276 Jul 26 07:11:33 PM PDT 24 Jul 26 07:11:34 PM PDT 24 12964581 ps
T653 /workspace/coverage/default/6.sram_ctrl_partial_access.4231269373 Jul 26 07:11:10 PM PDT 24 Jul 26 07:11:31 PM PDT 24 10858220348 ps
T654 /workspace/coverage/default/28.sram_ctrl_ram_cfg.1402018192 Jul 26 07:14:13 PM PDT 24 Jul 26 07:14:14 PM PDT 24 33471333 ps
T655 /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.3050877045 Jul 26 07:10:34 PM PDT 24 Jul 26 07:12:48 PM PDT 24 650247335 ps
T656 /workspace/coverage/default/35.sram_ctrl_smoke.3751234214 Jul 26 07:15:19 PM PDT 24 Jul 26 07:17:51 PM PDT 24 666487047 ps
T657 /workspace/coverage/default/39.sram_ctrl_executable.2984555371 Jul 26 07:16:19 PM PDT 24 Jul 26 07:20:02 PM PDT 24 2401942843 ps
T658 /workspace/coverage/default/49.sram_ctrl_access_during_key_req.2132475039 Jul 26 07:18:15 PM PDT 24 Jul 26 07:32:40 PM PDT 24 12782399060 ps
T659 /workspace/coverage/default/42.sram_ctrl_access_during_key_req.1101070803 Jul 26 07:16:53 PM PDT 24 Jul 26 07:41:08 PM PDT 24 22792666827 ps
T660 /workspace/coverage/default/32.sram_ctrl_mem_walk.2068191285 Jul 26 07:14:58 PM PDT 24 Jul 26 07:15:09 PM PDT 24 2433270905 ps
T661 /workspace/coverage/default/24.sram_ctrl_smoke.3702099404 Jul 26 07:13:21 PM PDT 24 Jul 26 07:14:15 PM PDT 24 857683874 ps
T662 /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.790033131 Jul 26 07:16:15 PM PDT 24 Jul 26 07:20:43 PM PDT 24 3619180123 ps
T663 /workspace/coverage/default/2.sram_ctrl_alert_test.1679374231 Jul 26 07:10:41 PM PDT 24 Jul 26 07:10:41 PM PDT 24 27886262 ps
T664 /workspace/coverage/default/18.sram_ctrl_stress_pipeline.1658432445 Jul 26 07:12:19 PM PDT 24 Jul 26 07:17:34 PM PDT 24 7378925603 ps
T665 /workspace/coverage/default/30.sram_ctrl_partial_access.2664424271 Jul 26 07:14:36 PM PDT 24 Jul 26 07:14:38 PM PDT 24 118064729 ps
T666 /workspace/coverage/default/12.sram_ctrl_multiple_keys.2442119223 Jul 26 07:11:37 PM PDT 24 Jul 26 07:21:10 PM PDT 24 2106087950 ps
T667 /workspace/coverage/default/15.sram_ctrl_regwen.4014205612 Jul 26 07:11:58 PM PDT 24 Jul 26 07:25:57 PM PDT 24 4493209199 ps
T668 /workspace/coverage/default/46.sram_ctrl_mem_partial_access.3157074391 Jul 26 07:17:49 PM PDT 24 Jul 26 07:17:53 PM PDT 24 181546008 ps
T669 /workspace/coverage/default/25.sram_ctrl_alert_test.1419801588 Jul 26 07:13:49 PM PDT 24 Jul 26 07:13:49 PM PDT 24 55399750 ps
T670 /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.1382840212 Jul 26 07:12:14 PM PDT 24 Jul 26 07:12:51 PM PDT 24 207479205 ps
T671 /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.1885414138 Jul 26 07:13:08 PM PDT 24 Jul 26 07:19:38 PM PDT 24 30061133094 ps
T672 /workspace/coverage/default/27.sram_ctrl_stress_pipeline.3902865161 Jul 26 07:14:01 PM PDT 24 Jul 26 07:17:44 PM PDT 24 6604499182 ps
T673 /workspace/coverage/default/0.sram_ctrl_partial_access.2161578693 Jul 26 07:10:32 PM PDT 24 Jul 26 07:11:02 PM PDT 24 1508985478 ps
T674 /workspace/coverage/default/32.sram_ctrl_stress_all.2175327876 Jul 26 07:14:56 PM PDT 24 Jul 26 08:21:27 PM PDT 24 129759432856 ps
T675 /workspace/coverage/default/29.sram_ctrl_mem_partial_access.1614474613 Jul 26 07:14:23 PM PDT 24 Jul 26 07:14:30 PM PDT 24 1489339201 ps
T676 /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.1284976536 Jul 26 07:14:10 PM PDT 24 Jul 26 07:20:39 PM PDT 24 10981531479 ps
T677 /workspace/coverage/default/43.sram_ctrl_access_during_key_req.1093888229 Jul 26 07:17:00 PM PDT 24 Jul 26 07:24:59 PM PDT 24 12188545701 ps
T678 /workspace/coverage/default/0.sram_ctrl_multiple_keys.3929912246 Jul 26 07:10:32 PM PDT 24 Jul 26 07:21:08 PM PDT 24 4690807933 ps
T679 /workspace/coverage/default/24.sram_ctrl_regwen.751725807 Jul 26 07:13:37 PM PDT 24 Jul 26 07:14:51 PM PDT 24 1291650073 ps
T680 /workspace/coverage/default/32.sram_ctrl_mem_partial_access.3789133144 Jul 26 07:14:57 PM PDT 24 Jul 26 07:15:03 PM PDT 24 691060274 ps
T681 /workspace/coverage/default/9.sram_ctrl_bijection.917550045 Jul 26 07:11:27 PM PDT 24 Jul 26 07:12:49 PM PDT 24 5240039637 ps
T682 /workspace/coverage/default/23.sram_ctrl_alert_test.4105121248 Jul 26 07:13:22 PM PDT 24 Jul 26 07:13:23 PM PDT 24 33672737 ps
T683 /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.3994450738 Jul 26 07:11:29 PM PDT 24 Jul 26 07:12:06 PM PDT 24 1373700301 ps
T684 /workspace/coverage/default/18.sram_ctrl_max_throughput.2448963939 Jul 26 07:12:29 PM PDT 24 Jul 26 07:15:10 PM PDT 24 136330540 ps
T685 /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.416870048 Jul 26 07:11:22 PM PDT 24 Jul 26 07:16:37 PM PDT 24 18547515370 ps
T686 /workspace/coverage/default/20.sram_ctrl_regwen.3610736340 Jul 26 07:12:50 PM PDT 24 Jul 26 07:21:33 PM PDT 24 20722399627 ps
T687 /workspace/coverage/default/9.sram_ctrl_mem_partial_access.620719785 Jul 26 07:11:27 PM PDT 24 Jul 26 07:11:30 PM PDT 24 177667878 ps
T688 /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.1562311604 Jul 26 07:17:59 PM PDT 24 Jul 26 07:22:40 PM PDT 24 22544551169 ps
T689 /workspace/coverage/default/40.sram_ctrl_executable.2759373547 Jul 26 07:16:35 PM PDT 24 Jul 26 07:31:13 PM PDT 24 45508717737 ps
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T695 /workspace/coverage/default/29.sram_ctrl_partial_access.3325343679 Jul 26 07:14:11 PM PDT 24 Jul 26 07:14:13 PM PDT 24 135557795 ps
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T697 /workspace/coverage/default/28.sram_ctrl_bijection.665216608 Jul 26 07:14:02 PM PDT 24 Jul 26 07:14:28 PM PDT 24 1387562528 ps
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T27 /workspace/coverage/default/3.sram_ctrl_sec_cm.1395497698 Jul 26 07:10:59 PM PDT 24 Jul 26 07:11:01 PM PDT 24 133338104 ps
T706 /workspace/coverage/default/14.sram_ctrl_stress_pipeline.3634857880 Jul 26 07:11:49 PM PDT 24 Jul 26 07:14:47 PM PDT 24 1989030276 ps
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T711 /workspace/coverage/default/41.sram_ctrl_access_during_key_req.475081664 Jul 26 07:16:35 PM PDT 24 Jul 26 07:29:29 PM PDT 24 2666281621 ps
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T713 /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.2530645246 Jul 26 07:14:33 PM PDT 24 Jul 26 07:15:06 PM PDT 24 985841032 ps
T714 /workspace/coverage/default/26.sram_ctrl_executable.471540291 Jul 26 07:13:48 PM PDT 24 Jul 26 07:45:53 PM PDT 24 16996280554 ps
T715 /workspace/coverage/default/21.sram_ctrl_mem_partial_access.1995586707 Jul 26 07:13:04 PM PDT 24 Jul 26 07:13:09 PM PDT 24 291159199 ps
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T717 /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.806864191 Jul 26 07:12:30 PM PDT 24 Jul 26 07:19:49 PM PDT 24 33311805787 ps
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T719 /workspace/coverage/default/41.sram_ctrl_lc_escalation.3552018615 Jul 26 07:16:35 PM PDT 24 Jul 26 07:16:41 PM PDT 24 687419859 ps
T720 /workspace/coverage/default/19.sram_ctrl_mem_partial_access.1412273324 Jul 26 07:12:38 PM PDT 24 Jul 26 07:12:41 PM PDT 24 111481557 ps
T721 /workspace/coverage/default/1.sram_ctrl_max_throughput.4024472683 Jul 26 07:10:34 PM PDT 24 Jul 26 07:13:19 PM PDT 24 143232374 ps
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T723 /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.1908989028 Jul 26 07:18:11 PM PDT 24 Jul 26 07:21:12 PM PDT 24 2587137405 ps
T724 /workspace/coverage/default/19.sram_ctrl_smoke.810550420 Jul 26 07:12:29 PM PDT 24 Jul 26 07:12:48 PM PDT 24 2344663227 ps
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T48 /workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.2963946859 Jul 26 07:13:11 PM PDT 24 Jul 26 07:14:32 PM PDT 24 2831707920 ps
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T727 /workspace/coverage/default/47.sram_ctrl_max_throughput.1667086084 Jul 26 07:17:58 PM PDT 24 Jul 26 07:18:37 PM PDT 24 167196802 ps
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T730 /workspace/coverage/default/18.sram_ctrl_partial_access.3648092117 Jul 26 07:12:20 PM PDT 24 Jul 26 07:13:51 PM PDT 24 1491502073 ps
T731 /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.882013740 Jul 26 07:12:39 PM PDT 24 Jul 26 07:13:02 PM PDT 24 198389215 ps
T732 /workspace/coverage/default/19.sram_ctrl_max_throughput.387890441 Jul 26 07:12:39 PM PDT 24 Jul 26 07:13:08 PM PDT 24 129260449 ps
T733 /workspace/coverage/default/40.sram_ctrl_bijection.3213446316 Jul 26 07:16:27 PM PDT 24 Jul 26 07:17:20 PM PDT 24 3239860551 ps
T734 /workspace/coverage/default/1.sram_ctrl_ram_cfg.4098921190 Jul 26 07:10:43 PM PDT 24 Jul 26 07:10:44 PM PDT 24 79976735 ps
T735 /workspace/coverage/default/35.sram_ctrl_stress_all.1438862732 Jul 26 07:15:39 PM PDT 24 Jul 26 08:53:18 PM PDT 24 106869543661 ps
T736 /workspace/coverage/default/6.sram_ctrl_max_throughput.3668848002 Jul 26 07:11:09 PM PDT 24 Jul 26 07:11:33 PM PDT 24 86170063 ps
T737 /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.1744217644 Jul 26 07:18:17 PM PDT 24 Jul 26 07:20:39 PM PDT 24 1965750247 ps
T738 /workspace/coverage/default/10.sram_ctrl_access_during_key_req.2688495727 Jul 26 07:11:23 PM PDT 24 Jul 26 07:27:26 PM PDT 24 9720570339 ps
T739 /workspace/coverage/default/24.sram_ctrl_bijection.351273172 Jul 26 07:13:21 PM PDT 24 Jul 26 07:14:37 PM PDT 24 9912475149 ps
T740 /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.423019515 Jul 26 07:12:17 PM PDT 24 Jul 26 07:14:32 PM PDT 24 671450494 ps
T741 /workspace/coverage/default/25.sram_ctrl_multiple_keys.2798331360 Jul 26 07:13:35 PM PDT 24 Jul 26 07:27:41 PM PDT 24 4736467366 ps
T742 /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.3089649635 Jul 26 07:10:31 PM PDT 24 Jul 26 07:16:58 PM PDT 24 54009026672 ps
T743 /workspace/coverage/default/20.sram_ctrl_bijection.1675373272 Jul 26 07:12:37 PM PDT 24 Jul 26 07:13:23 PM PDT 24 2825956126 ps
T744 /workspace/coverage/default/45.sram_ctrl_max_throughput.4087485038 Jul 26 07:17:34 PM PDT 24 Jul 26 07:18:10 PM PDT 24 331229202 ps
T745 /workspace/coverage/default/22.sram_ctrl_mem_walk.1038994170 Jul 26 07:13:09 PM PDT 24 Jul 26 07:13:15 PM PDT 24 430741712 ps
T746 /workspace/coverage/default/37.sram_ctrl_regwen.3124384677 Jul 26 07:15:50 PM PDT 24 Jul 26 07:39:12 PM PDT 24 17050749944 ps
T747 /workspace/coverage/default/38.sram_ctrl_regwen.1880926673 Jul 26 07:15:59 PM PDT 24 Jul 26 07:25:24 PM PDT 24 7100255258 ps
T748 /workspace/coverage/default/46.sram_ctrl_mem_walk.2893845940 Jul 26 07:17:50 PM PDT 24 Jul 26 07:17:55 PM PDT 24 1137109060 ps
T749 /workspace/coverage/default/42.sram_ctrl_mem_partial_access.1455873950 Jul 26 07:16:53 PM PDT 24 Jul 26 07:16:56 PM PDT 24 396173481 ps
T750 /workspace/coverage/default/44.sram_ctrl_stress_all.3044119378 Jul 26 07:17:21 PM PDT 24 Jul 26 08:10:07 PM PDT 24 70302490522 ps
T751 /workspace/coverage/default/42.sram_ctrl_multiple_keys.2500460786 Jul 26 07:16:46 PM PDT 24 Jul 26 07:23:07 PM PDT 24 68600968630 ps
T752 /workspace/coverage/default/9.sram_ctrl_access_during_key_req.1576803508 Jul 26 07:11:33 PM PDT 24 Jul 26 07:32:19 PM PDT 24 14902675162 ps
T120 /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.3719654331 Jul 26 07:10:42 PM PDT 24 Jul 26 07:13:05 PM PDT 24 1976302435 ps
T753 /workspace/coverage/default/5.sram_ctrl_max_throughput.3827407611 Jul 26 07:10:58 PM PDT 24 Jul 26 07:12:48 PM PDT 24 348157970 ps
T754 /workspace/coverage/default/3.sram_ctrl_stress_pipeline.2304205569 Jul 26 07:10:45 PM PDT 24 Jul 26 07:15:26 PM PDT 24 2693461393 ps
T755 /workspace/coverage/default/10.sram_ctrl_lc_escalation.1815066021 Jul 26 07:11:27 PM PDT 24 Jul 26 07:11:38 PM PDT 24 2054734667 ps
T756 /workspace/coverage/default/38.sram_ctrl_max_throughput.2497710204 Jul 26 07:15:58 PM PDT 24 Jul 26 07:17:36 PM PDT 24 256619343 ps
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T758 /workspace/coverage/default/32.sram_ctrl_ram_cfg.2065915580 Jul 26 07:14:56 PM PDT 24 Jul 26 07:14:57 PM PDT 24 40532740 ps
T759 /workspace/coverage/default/41.sram_ctrl_stress_pipeline.3240873379 Jul 26 07:16:42 PM PDT 24 Jul 26 07:20:42 PM PDT 24 7622544457 ps
T760 /workspace/coverage/default/19.sram_ctrl_ram_cfg.3926642075 Jul 26 07:12:38 PM PDT 24 Jul 26 07:12:39 PM PDT 24 81514039 ps
T761 /workspace/coverage/default/16.sram_ctrl_alert_test.2622121091 Jul 26 07:12:08 PM PDT 24 Jul 26 07:12:09 PM PDT 24 12731656 ps
T121 /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.622716721 Jul 26 07:11:22 PM PDT 24 Jul 26 07:11:34 PM PDT 24 740592102 ps
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T763 /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.534510353 Jul 26 07:11:29 PM PDT 24 Jul 26 07:16:01 PM PDT 24 6902172950 ps
T764 /workspace/coverage/default/33.sram_ctrl_alert_test.4113618511 Jul 26 07:15:08 PM PDT 24 Jul 26 07:15:09 PM PDT 24 19228409 ps
T765 /workspace/coverage/default/41.sram_ctrl_ram_cfg.2933631119 Jul 26 07:16:46 PM PDT 24 Jul 26 07:16:46 PM PDT 24 63502330 ps
T766 /workspace/coverage/default/4.sram_ctrl_multiple_keys.3131825766 Jul 26 07:10:59 PM PDT 24 Jul 26 07:28:58 PM PDT 24 37905925880 ps
T767 /workspace/coverage/default/2.sram_ctrl_max_throughput.895477003 Jul 26 07:10:42 PM PDT 24 Jul 26 07:11:42 PM PDT 24 701484664 ps
T768 /workspace/coverage/default/24.sram_ctrl_lc_escalation.2573792039 Jul 26 07:13:20 PM PDT 24 Jul 26 07:13:23 PM PDT 24 223263415 ps
T769 /workspace/coverage/default/45.sram_ctrl_partial_access.590526371 Jul 26 07:17:33 PM PDT 24 Jul 26 07:17:50 PM PDT 24 310992319 ps
T770 /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.2269983924 Jul 26 07:14:02 PM PDT 24 Jul 26 07:20:28 PM PDT 24 63047812628 ps
T771 /workspace/coverage/default/10.sram_ctrl_mem_partial_access.2618540449 Jul 26 07:11:23 PM PDT 24 Jul 26 07:11:26 PM PDT 24 42975179 ps
T772 /workspace/coverage/default/13.sram_ctrl_multiple_keys.3895578428 Jul 26 07:11:48 PM PDT 24 Jul 26 07:35:51 PM PDT 24 2884516315 ps
T773 /workspace/coverage/default/7.sram_ctrl_multiple_keys.1090722477 Jul 26 07:11:11 PM PDT 24 Jul 26 07:34:45 PM PDT 24 16894462255 ps
T774 /workspace/coverage/default/48.sram_ctrl_mem_walk.1124520418 Jul 26 07:18:16 PM PDT 24 Jul 26 07:18:23 PM PDT 24 1572974979 ps
T122 /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.591905612 Jul 26 07:11:51 PM PDT 24 Jul 26 07:13:07 PM PDT 24 5534978701 ps
T775 /workspace/coverage/default/27.sram_ctrl_ram_cfg.3376161612 Jul 26 07:14:00 PM PDT 24 Jul 26 07:14:00 PM PDT 24 41280435 ps
T776 /workspace/coverage/default/13.sram_ctrl_mem_walk.2782300255 Jul 26 07:11:48 PM PDT 24 Jul 26 07:12:00 PM PDT 24 3833561926 ps
T777 /workspace/coverage/default/35.sram_ctrl_lc_escalation.674393881 Jul 26 07:15:27 PM PDT 24 Jul 26 07:15:37 PM PDT 24 1755426835 ps
T778 /workspace/coverage/default/0.sram_ctrl_mem_partial_access.3029008529 Jul 26 07:10:34 PM PDT 24 Jul 26 07:10:40 PM PDT 24 2112489041 ps
T779 /workspace/coverage/default/44.sram_ctrl_mem_partial_access.4272172592 Jul 26 07:17:22 PM PDT 24 Jul 26 07:17:26 PM PDT 24 70333776 ps
T780 /workspace/coverage/default/5.sram_ctrl_mem_partial_access.597836389 Jul 26 07:11:09 PM PDT 24 Jul 26 07:11:14 PM PDT 24 234078521 ps
T28 /workspace/coverage/default/2.sram_ctrl_sec_cm.2540953571 Jul 26 07:10:42 PM PDT 24 Jul 26 07:10:45 PM PDT 24 699920307 ps
T781 /workspace/coverage/default/25.sram_ctrl_max_throughput.2211036220 Jul 26 07:13:36 PM PDT 24 Jul 26 07:15:01 PM PDT 24 123877448 ps
T782 /workspace/coverage/default/47.sram_ctrl_lc_escalation.2644544436 Jul 26 07:17:58 PM PDT 24 Jul 26 07:18:04 PM PDT 24 2319718065 ps
T783 /workspace/coverage/default/37.sram_ctrl_stress_pipeline.846671866 Jul 26 07:15:49 PM PDT 24 Jul 26 07:19:57 PM PDT 24 9878614063 ps
T784 /workspace/coverage/default/39.sram_ctrl_mem_partial_access.3049158290 Jul 26 07:16:21 PM PDT 24 Jul 26 07:16:24 PM PDT 24 444564604 ps
T785 /workspace/coverage/default/22.sram_ctrl_smoke.17154224 Jul 26 07:13:06 PM PDT 24 Jul 26 07:13:11 PM PDT 24 189887197 ps
T786 /workspace/coverage/default/49.sram_ctrl_regwen.102316033 Jul 26 07:18:15 PM PDT 24 Jul 26 07:34:57 PM PDT 24 11556050780 ps
T787 /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.4190386293 Jul 26 07:11:11 PM PDT 24 Jul 26 07:11:13 PM PDT 24 196641849 ps
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