| T788 |
/workspace/coverage/default/22.sram_ctrl_max_throughput.3269125290 |
|
|
Jul 26 07:13:01 PM PDT 24 |
Jul 26 07:13:32 PM PDT 24 |
320877830 ps |
| T789 |
/workspace/coverage/default/30.sram_ctrl_access_during_key_req.3749561976 |
|
|
Jul 26 07:14:34 PM PDT 24 |
Jul 26 07:34:39 PM PDT 24 |
20818033695 ps |
| T790 |
/workspace/coverage/default/48.sram_ctrl_regwen.1244417658 |
|
|
Jul 26 07:18:14 PM PDT 24 |
Jul 26 07:39:33 PM PDT 24 |
2208100743 ps |
| T791 |
/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.3167326216 |
|
|
Jul 26 07:12:17 PM PDT 24 |
Jul 26 07:19:42 PM PDT 24 |
41276753079 ps |
| T792 |
/workspace/coverage/default/48.sram_ctrl_bijection.3344747118 |
|
|
Jul 26 07:18:10 PM PDT 24 |
Jul 26 07:19:25 PM PDT 24 |
4767118909 ps |
| T793 |
/workspace/coverage/default/12.sram_ctrl_stress_all.1890158684 |
|
|
Jul 26 07:11:47 PM PDT 24 |
Jul 26 07:54:36 PM PDT 24 |
71877725228 ps |
| T794 |
/workspace/coverage/default/15.sram_ctrl_max_throughput.1139124953 |
|
|
Jul 26 07:11:57 PM PDT 24 |
Jul 26 07:12:16 PM PDT 24 |
155773203 ps |
| T795 |
/workspace/coverage/default/33.sram_ctrl_mem_partial_access.887616735 |
|
|
Jul 26 07:15:08 PM PDT 24 |
Jul 26 07:15:14 PM PDT 24 |
2740613230 ps |
| T796 |
/workspace/coverage/default/29.sram_ctrl_stress_pipeline.3037021118 |
|
|
Jul 26 07:14:14 PM PDT 24 |
Jul 26 07:16:49 PM PDT 24 |
5655393973 ps |
| T797 |
/workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.3759484242 |
|
|
Jul 26 07:15:48 PM PDT 24 |
Jul 26 07:16:18 PM PDT 24 |
223399618 ps |
| T798 |
/workspace/coverage/default/47.sram_ctrl_ram_cfg.4113436596 |
|
|
Jul 26 07:17:59 PM PDT 24 |
Jul 26 07:18:00 PM PDT 24 |
27811573 ps |
| T799 |
/workspace/coverage/default/6.sram_ctrl_executable.2321327583 |
|
|
Jul 26 07:11:06 PM PDT 24 |
Jul 26 07:19:15 PM PDT 24 |
5648537550 ps |
| T800 |
/workspace/coverage/default/1.sram_ctrl_stress_all.1181212482 |
|
|
Jul 26 07:10:43 PM PDT 24 |
Jul 26 08:23:09 PM PDT 24 |
74835485128 ps |
| T801 |
/workspace/coverage/default/49.sram_ctrl_multiple_keys.1022650097 |
|
|
Jul 26 07:18:15 PM PDT 24 |
Jul 26 07:18:43 PM PDT 24 |
1785762779 ps |
| T802 |
/workspace/coverage/default/10.sram_ctrl_stress_all.1562652291 |
|
|
Jul 26 07:11:21 PM PDT 24 |
Jul 26 07:45:25 PM PDT 24 |
26943421826 ps |
| T803 |
/workspace/coverage/default/45.sram_ctrl_regwen.3419790540 |
|
|
Jul 26 07:17:28 PM PDT 24 |
Jul 26 07:52:06 PM PDT 24 |
65946331528 ps |
| T804 |
/workspace/coverage/default/32.sram_ctrl_smoke.28725210 |
|
|
Jul 26 07:14:44 PM PDT 24 |
Jul 26 07:16:53 PM PDT 24 |
134065439 ps |
| T805 |
/workspace/coverage/default/35.sram_ctrl_access_during_key_req.1597888959 |
|
|
Jul 26 07:15:28 PM PDT 24 |
Jul 26 07:18:00 PM PDT 24 |
854167335 ps |
| T806 |
/workspace/coverage/default/43.sram_ctrl_alert_test.4242355897 |
|
|
Jul 26 07:17:09 PM PDT 24 |
Jul 26 07:17:10 PM PDT 24 |
101931640 ps |
| T807 |
/workspace/coverage/default/30.sram_ctrl_smoke.2208660058 |
|
|
Jul 26 07:14:23 PM PDT 24 |
Jul 26 07:14:30 PM PDT 24 |
223392057 ps |
| T808 |
/workspace/coverage/default/41.sram_ctrl_partial_access.3126203787 |
|
|
Jul 26 07:16:42 PM PDT 24 |
Jul 26 07:18:55 PM PDT 24 |
834222933 ps |
| T809 |
/workspace/coverage/default/10.sram_ctrl_mem_walk.622764062 |
|
|
Jul 26 07:11:26 PM PDT 24 |
Jul 26 07:11:31 PM PDT 24 |
231320452 ps |
| T810 |
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.3148840480 |
|
|
Jul 26 07:17:19 PM PDT 24 |
Jul 26 07:17:29 PM PDT 24 |
165332951 ps |
| T811 |
/workspace/coverage/default/43.sram_ctrl_executable.1070581188 |
|
|
Jul 26 07:17:01 PM PDT 24 |
Jul 26 07:17:38 PM PDT 24 |
2643314967 ps |
| T812 |
/workspace/coverage/default/46.sram_ctrl_stress_all.794680224 |
|
|
Jul 26 07:17:48 PM PDT 24 |
Jul 26 08:11:40 PM PDT 24 |
14694202817 ps |
| T813 |
/workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.1750505476 |
|
|
Jul 26 07:10:42 PM PDT 24 |
Jul 26 07:11:12 PM PDT 24 |
93897443 ps |
| T814 |
/workspace/coverage/default/20.sram_ctrl_multiple_keys.80765481 |
|
|
Jul 26 07:12:38 PM PDT 24 |
Jul 26 07:28:19 PM PDT 24 |
6165328690 ps |
| T815 |
/workspace/coverage/default/27.sram_ctrl_stress_all.1114523848 |
|
|
Jul 26 07:14:01 PM PDT 24 |
Jul 26 07:39:22 PM PDT 24 |
52073262934 ps |
| T816 |
/workspace/coverage/default/17.sram_ctrl_stress_all.290061341 |
|
|
Jul 26 07:12:18 PM PDT 24 |
Jul 26 07:31:42 PM PDT 24 |
4100880621 ps |
| T817 |
/workspace/coverage/default/22.sram_ctrl_access_during_key_req.1498697667 |
|
|
Jul 26 07:13:00 PM PDT 24 |
Jul 26 07:30:24 PM PDT 24 |
3768964283 ps |
| T818 |
/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.1310964089 |
|
|
Jul 26 07:12:51 PM PDT 24 |
Jul 26 07:14:22 PM PDT 24 |
496846079 ps |
| T819 |
/workspace/coverage/default/31.sram_ctrl_lc_escalation.59317040 |
|
|
Jul 26 07:14:38 PM PDT 24 |
Jul 26 07:14:43 PM PDT 24 |
462881361 ps |
| T820 |
/workspace/coverage/default/27.sram_ctrl_smoke.3130046863 |
|
|
Jul 26 07:14:01 PM PDT 24 |
Jul 26 07:14:11 PM PDT 24 |
397929136 ps |
| T821 |
/workspace/coverage/default/11.sram_ctrl_bijection.1494456380 |
|
|
Jul 26 07:11:25 PM PDT 24 |
Jul 26 07:12:43 PM PDT 24 |
8432328590 ps |
| T822 |
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.2221041873 |
|
|
Jul 26 07:17:10 PM PDT 24 |
Jul 26 07:17:16 PM PDT 24 |
664222698 ps |
| T823 |
/workspace/coverage/default/19.sram_ctrl_regwen.3163396188 |
|
|
Jul 26 07:12:38 PM PDT 24 |
Jul 26 07:29:32 PM PDT 24 |
79145451718 ps |
| T824 |
/workspace/coverage/default/28.sram_ctrl_alert_test.626066443 |
|
|
Jul 26 07:14:11 PM PDT 24 |
Jul 26 07:14:11 PM PDT 24 |
16144053 ps |
| T825 |
/workspace/coverage/default/45.sram_ctrl_alert_test.41321879 |
|
|
Jul 26 07:17:33 PM PDT 24 |
Jul 26 07:17:34 PM PDT 24 |
19079032 ps |
| T826 |
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.731617665 |
|
|
Jul 26 07:17:33 PM PDT 24 |
Jul 26 07:27:01 PM PDT 24 |
3024385243 ps |
| T827 |
/workspace/coverage/default/31.sram_ctrl_mem_partial_access.1923571457 |
|
|
Jul 26 07:14:47 PM PDT 24 |
Jul 26 07:14:50 PM PDT 24 |
118415460 ps |
| T49 |
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.2561125416 |
|
|
Jul 26 07:18:07 PM PDT 24 |
Jul 26 07:18:18 PM PDT 24 |
707028123 ps |
| T828 |
/workspace/coverage/default/14.sram_ctrl_smoke.412987458 |
|
|
Jul 26 07:11:56 PM PDT 24 |
Jul 26 07:12:04 PM PDT 24 |
347755552 ps |
| T829 |
/workspace/coverage/default/44.sram_ctrl_lc_escalation.1237079378 |
|
|
Jul 26 07:17:19 PM PDT 24 |
Jul 26 07:17:26 PM PDT 24 |
1708708916 ps |
| T830 |
/workspace/coverage/default/17.sram_ctrl_alert_test.2177956647 |
|
|
Jul 26 07:12:21 PM PDT 24 |
Jul 26 07:12:22 PM PDT 24 |
47179247 ps |
| T831 |
/workspace/coverage/default/2.sram_ctrl_stress_all.2568153033 |
|
|
Jul 26 07:10:42 PM PDT 24 |
Jul 26 07:50:15 PM PDT 24 |
92074644117 ps |
| T832 |
/workspace/coverage/default/0.sram_ctrl_lc_escalation.3537427081 |
|
|
Jul 26 07:10:32 PM PDT 24 |
Jul 26 07:10:36 PM PDT 24 |
363624705 ps |
| T833 |
/workspace/coverage/default/40.sram_ctrl_max_throughput.2821210865 |
|
|
Jul 26 07:16:28 PM PDT 24 |
Jul 26 07:19:02 PM PDT 24 |
137652531 ps |
| T834 |
/workspace/coverage/default/34.sram_ctrl_mem_partial_access.3819683500 |
|
|
Jul 26 07:15:17 PM PDT 24 |
Jul 26 07:15:19 PM PDT 24 |
151078664 ps |
| T835 |
/workspace/coverage/default/44.sram_ctrl_executable.442419375 |
|
|
Jul 26 07:17:21 PM PDT 24 |
Jul 26 07:30:18 PM PDT 24 |
13969841310 ps |
| T836 |
/workspace/coverage/default/23.sram_ctrl_multiple_keys.676668289 |
|
|
Jul 26 07:13:11 PM PDT 24 |
Jul 26 07:32:39 PM PDT 24 |
65146071161 ps |
| T837 |
/workspace/coverage/default/44.sram_ctrl_alert_test.946330392 |
|
|
Jul 26 07:17:18 PM PDT 24 |
Jul 26 07:17:19 PM PDT 24 |
16911185 ps |
| T838 |
/workspace/coverage/default/41.sram_ctrl_regwen.3634016420 |
|
|
Jul 26 07:16:45 PM PDT 24 |
Jul 26 07:30:26 PM PDT 24 |
25706566592 ps |
| T839 |
/workspace/coverage/default/31.sram_ctrl_mem_walk.2481142577 |
|
|
Jul 26 07:14:47 PM PDT 24 |
Jul 26 07:14:59 PM PDT 24 |
1118982045 ps |
| T840 |
/workspace/coverage/default/35.sram_ctrl_partial_access.3675452773 |
|
|
Jul 26 07:15:25 PM PDT 24 |
Jul 26 07:17:30 PM PDT 24 |
7136895376 ps |
| T841 |
/workspace/coverage/default/29.sram_ctrl_access_during_key_req.2569136993 |
|
|
Jul 26 07:14:22 PM PDT 24 |
Jul 26 07:36:14 PM PDT 24 |
13548533702 ps |
| T842 |
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.2055305273 |
|
|
Jul 26 07:17:07 PM PDT 24 |
Jul 26 07:22:36 PM PDT 24 |
6810243457 ps |
| T843 |
/workspace/coverage/default/2.sram_ctrl_access_during_key_req.487785586 |
|
|
Jul 26 07:10:44 PM PDT 24 |
Jul 26 07:17:46 PM PDT 24 |
3234159924 ps |
| T844 |
/workspace/coverage/default/24.sram_ctrl_partial_access.1918914200 |
|
|
Jul 26 07:13:21 PM PDT 24 |
Jul 26 07:13:33 PM PDT 24 |
210235974 ps |
| T845 |
/workspace/coverage/default/42.sram_ctrl_executable.3962545419 |
|
|
Jul 26 07:16:58 PM PDT 24 |
Jul 26 07:23:25 PM PDT 24 |
11880832421 ps |
| T846 |
/workspace/coverage/default/17.sram_ctrl_executable.3955003604 |
|
|
Jul 26 07:12:20 PM PDT 24 |
Jul 26 07:22:55 PM PDT 24 |
41981805425 ps |
| T847 |
/workspace/coverage/default/30.sram_ctrl_max_throughput.1311970528 |
|
|
Jul 26 07:14:37 PM PDT 24 |
Jul 26 07:15:12 PM PDT 24 |
94792647 ps |
| T848 |
/workspace/coverage/default/31.sram_ctrl_multiple_keys.3587617381 |
|
|
Jul 26 07:14:38 PM PDT 24 |
Jul 26 07:35:35 PM PDT 24 |
14990088768 ps |
| T849 |
/workspace/coverage/default/18.sram_ctrl_smoke.3768917133 |
|
|
Jul 26 07:12:22 PM PDT 24 |
Jul 26 07:12:35 PM PDT 24 |
466590402 ps |
| T850 |
/workspace/coverage/default/0.sram_ctrl_regwen.3019330086 |
|
|
Jul 26 07:10:34 PM PDT 24 |
Jul 26 07:30:36 PM PDT 24 |
26976540462 ps |
| T851 |
/workspace/coverage/default/37.sram_ctrl_multiple_keys.3092318561 |
|
|
Jul 26 07:15:49 PM PDT 24 |
Jul 26 07:29:00 PM PDT 24 |
2127502758 ps |
| T852 |
/workspace/coverage/default/13.sram_ctrl_smoke.573826094 |
|
|
Jul 26 07:11:56 PM PDT 24 |
Jul 26 07:12:00 PM PDT 24 |
148774969 ps |
| T853 |
/workspace/coverage/default/13.sram_ctrl_regwen.236666338 |
|
|
Jul 26 07:11:48 PM PDT 24 |
Jul 26 07:36:56 PM PDT 24 |
104100332162 ps |
| T854 |
/workspace/coverage/default/3.sram_ctrl_ram_cfg.1653716582 |
|
|
Jul 26 07:10:59 PM PDT 24 |
Jul 26 07:11:00 PM PDT 24 |
37681466 ps |
| T855 |
/workspace/coverage/default/27.sram_ctrl_partial_access.2849112423 |
|
|
Jul 26 07:14:01 PM PDT 24 |
Jul 26 07:14:10 PM PDT 24 |
173194191 ps |
| T856 |
/workspace/coverage/default/33.sram_ctrl_ram_cfg.2259810747 |
|
|
Jul 26 07:15:07 PM PDT 24 |
Jul 26 07:15:08 PM PDT 24 |
28186015 ps |
| T857 |
/workspace/coverage/default/41.sram_ctrl_max_throughput.3332623539 |
|
|
Jul 26 07:16:36 PM PDT 24 |
Jul 26 07:17:04 PM PDT 24 |
87277866 ps |
| T858 |
/workspace/coverage/default/39.sram_ctrl_smoke.1974054934 |
|
|
Jul 26 07:16:10 PM PDT 24 |
Jul 26 07:19:03 PM PDT 24 |
2657546320 ps |
| T859 |
/workspace/coverage/default/32.sram_ctrl_bijection.519821365 |
|
|
Jul 26 07:14:44 PM PDT 24 |
Jul 26 07:15:20 PM PDT 24 |
1030246534 ps |
| T860 |
/workspace/coverage/default/20.sram_ctrl_smoke.2345243900 |
|
|
Jul 26 07:12:38 PM PDT 24 |
Jul 26 07:12:41 PM PDT 24 |
134029926 ps |
| T861 |
/workspace/coverage/default/16.sram_ctrl_stress_all.2291064789 |
|
|
Jul 26 07:12:08 PM PDT 24 |
Jul 26 07:58:06 PM PDT 24 |
7686179152 ps |
| T862 |
/workspace/coverage/default/22.sram_ctrl_partial_access.224600251 |
|
|
Jul 26 07:13:00 PM PDT 24 |
Jul 26 07:13:03 PM PDT 24 |
50132993 ps |
| T863 |
/workspace/coverage/default/12.sram_ctrl_alert_test.1850735891 |
|
|
Jul 26 07:11:49 PM PDT 24 |
Jul 26 07:11:50 PM PDT 24 |
18771378 ps |
| T864 |
/workspace/coverage/default/31.sram_ctrl_smoke.3800336313 |
|
|
Jul 26 07:14:35 PM PDT 24 |
Jul 26 07:14:53 PM PDT 24 |
1147062554 ps |
| T865 |
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1937360652 |
|
|
Jul 26 07:11:22 PM PDT 24 |
Jul 26 07:18:57 PM PDT 24 |
2721860254 ps |
| T866 |
/workspace/coverage/default/24.sram_ctrl_multiple_keys.693317405 |
|
|
Jul 26 07:13:22 PM PDT 24 |
Jul 26 07:23:06 PM PDT 24 |
83205358499 ps |
| T867 |
/workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.3680356626 |
|
|
Jul 26 07:15:25 PM PDT 24 |
Jul 26 07:16:43 PM PDT 24 |
205856671 ps |
| T868 |
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.1188961631 |
|
|
Jul 26 07:17:27 PM PDT 24 |
Jul 26 07:17:30 PM PDT 24 |
86129339 ps |
| T869 |
/workspace/coverage/default/3.sram_ctrl_max_throughput.3756502610 |
|
|
Jul 26 07:10:57 PM PDT 24 |
Jul 26 07:12:17 PM PDT 24 |
123237165 ps |
| T870 |
/workspace/coverage/default/26.sram_ctrl_regwen.2105765648 |
|
|
Jul 26 07:13:48 PM PDT 24 |
Jul 26 07:28:38 PM PDT 24 |
9501394531 ps |
| T871 |
/workspace/coverage/default/35.sram_ctrl_max_throughput.2519882404 |
|
|
Jul 26 07:15:25 PM PDT 24 |
Jul 26 07:17:46 PM PDT 24 |
681910609 ps |
| T872 |
/workspace/coverage/default/1.sram_ctrl_smoke.384367273 |
|
|
Jul 26 07:10:35 PM PDT 24 |
Jul 26 07:10:37 PM PDT 24 |
196824645 ps |
| T873 |
/workspace/coverage/default/17.sram_ctrl_bijection.1068313895 |
|
|
Jul 26 07:12:08 PM PDT 24 |
Jul 26 07:13:11 PM PDT 24 |
9246308246 ps |
| T874 |
/workspace/coverage/default/48.sram_ctrl_partial_access.4096818756 |
|
|
Jul 26 07:18:08 PM PDT 24 |
Jul 26 07:20:22 PM PDT 24 |
789233496 ps |
| T875 |
/workspace/coverage/default/30.sram_ctrl_mem_partial_access.3154565883 |
|
|
Jul 26 07:14:33 PM PDT 24 |
Jul 26 07:14:38 PM PDT 24 |
337984636 ps |
| T876 |
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.1074531632 |
|
|
Jul 26 07:11:10 PM PDT 24 |
Jul 26 07:18:03 PM PDT 24 |
10964802064 ps |
| T877 |
/workspace/coverage/default/14.sram_ctrl_bijection.2604493263 |
|
|
Jul 26 07:11:51 PM PDT 24 |
Jul 26 07:12:43 PM PDT 24 |
50419590819 ps |
| T878 |
/workspace/coverage/default/33.sram_ctrl_executable.430239871 |
|
|
Jul 26 07:15:08 PM PDT 24 |
Jul 26 07:30:47 PM PDT 24 |
2784455248 ps |
| T879 |
/workspace/coverage/default/20.sram_ctrl_lc_escalation.3639978274 |
|
|
Jul 26 07:12:53 PM PDT 24 |
Jul 26 07:13:01 PM PDT 24 |
660843929 ps |
| T880 |
/workspace/coverage/default/41.sram_ctrl_mem_walk.2062164062 |
|
|
Jul 26 07:16:50 PM PDT 24 |
Jul 26 07:16:56 PM PDT 24 |
231960032 ps |
| T881 |
/workspace/coverage/default/12.sram_ctrl_mem_walk.2762194127 |
|
|
Jul 26 07:11:48 PM PDT 24 |
Jul 26 07:11:58 PM PDT 24 |
610092849 ps |
| T882 |
/workspace/coverage/default/25.sram_ctrl_access_during_key_req.2886585338 |
|
|
Jul 26 07:13:38 PM PDT 24 |
Jul 26 07:36:45 PM PDT 24 |
7295165725 ps |
| T883 |
/workspace/coverage/default/26.sram_ctrl_smoke.2490410063 |
|
|
Jul 26 07:13:49 PM PDT 24 |
Jul 26 07:13:53 PM PDT 24 |
50818247 ps |
| T884 |
/workspace/coverage/default/13.sram_ctrl_partial_access.2438558896 |
|
|
Jul 26 07:11:52 PM PDT 24 |
Jul 26 07:12:09 PM PDT 24 |
319882134 ps |
| T885 |
/workspace/coverage/default/15.sram_ctrl_executable.923210526 |
|
|
Jul 26 07:12:01 PM PDT 24 |
Jul 26 07:21:30 PM PDT 24 |
65521028359 ps |
| T886 |
/workspace/coverage/default/35.sram_ctrl_mem_walk.4019318024 |
|
|
Jul 26 07:15:32 PM PDT 24 |
Jul 26 07:15:41 PM PDT 24 |
290734199 ps |
| T887 |
/workspace/coverage/default/38.sram_ctrl_ram_cfg.2003162159 |
|
|
Jul 26 07:16:10 PM PDT 24 |
Jul 26 07:16:11 PM PDT 24 |
75559814 ps |
| T888 |
/workspace/coverage/default/5.sram_ctrl_bijection.1542892863 |
|
|
Jul 26 07:10:57 PM PDT 24 |
Jul 26 07:12:07 PM PDT 24 |
4543970555 ps |
| T889 |
/workspace/coverage/default/4.sram_ctrl_ram_cfg.3338939192 |
|
|
Jul 26 07:10:57 PM PDT 24 |
Jul 26 07:10:57 PM PDT 24 |
27524588 ps |
| T890 |
/workspace/coverage/default/28.sram_ctrl_stress_all.1949116196 |
|
|
Jul 26 07:14:10 PM PDT 24 |
Jul 26 07:41:50 PM PDT 24 |
26423114549 ps |
| T891 |
/workspace/coverage/default/9.sram_ctrl_executable.78292265 |
|
|
Jul 26 07:11:24 PM PDT 24 |
Jul 26 07:26:21 PM PDT 24 |
10839444945 ps |
| T892 |
/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.3344160818 |
|
|
Jul 26 07:15:08 PM PDT 24 |
Jul 26 07:15:19 PM PDT 24 |
320235121 ps |
| T893 |
/workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.3556693064 |
|
|
Jul 26 07:14:09 PM PDT 24 |
Jul 26 07:14:29 PM PDT 24 |
109383970 ps |
| T894 |
/workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.1329356688 |
|
|
Jul 26 07:14:22 PM PDT 24 |
Jul 26 07:20:33 PM PDT 24 |
4026864448 ps |
| T895 |
/workspace/coverage/default/23.sram_ctrl_mem_walk.646623847 |
|
|
Jul 26 07:13:22 PM PDT 24 |
Jul 26 07:13:33 PM PDT 24 |
2923950484 ps |
| T896 |
/workspace/coverage/default/0.sram_ctrl_mem_walk.2227957673 |
|
|
Jul 26 07:10:34 PM PDT 24 |
Jul 26 07:10:42 PM PDT 24 |
144044445 ps |
| T897 |
/workspace/coverage/default/22.sram_ctrl_alert_test.721006706 |
|
|
Jul 26 07:13:11 PM PDT 24 |
Jul 26 07:13:12 PM PDT 24 |
47306276 ps |
| T898 |
/workspace/coverage/default/10.sram_ctrl_regwen.611662093 |
|
|
Jul 26 07:11:33 PM PDT 24 |
Jul 26 07:32:35 PM PDT 24 |
2805862525 ps |
| T899 |
/workspace/coverage/default/1.sram_ctrl_executable.2833230464 |
|
|
Jul 26 07:10:43 PM PDT 24 |
Jul 26 07:32:37 PM PDT 24 |
180679820405 ps |
| T900 |
/workspace/coverage/default/7.sram_ctrl_ram_cfg.973282825 |
|
|
Jul 26 07:11:12 PM PDT 24 |
Jul 26 07:11:13 PM PDT 24 |
48628921 ps |
| T901 |
/workspace/coverage/default/40.sram_ctrl_smoke.2613525226 |
|
|
Jul 26 07:16:27 PM PDT 24 |
Jul 26 07:16:32 PM PDT 24 |
1454180443 ps |
| T902 |
/workspace/coverage/default/36.sram_ctrl_access_during_key_req.321815961 |
|
|
Jul 26 07:15:40 PM PDT 24 |
Jul 26 07:25:13 PM PDT 24 |
10972957769 ps |
| T903 |
/workspace/coverage/default/2.sram_ctrl_stress_pipeline.4048532457 |
|
|
Jul 26 07:10:43 PM PDT 24 |
Jul 26 07:16:34 PM PDT 24 |
3503516488 ps |
| T904 |
/workspace/coverage/default/31.sram_ctrl_partial_access.3562873947 |
|
|
Jul 26 07:14:36 PM PDT 24 |
Jul 26 07:14:44 PM PDT 24 |
250072989 ps |
| T905 |
/workspace/coverage/default/34.sram_ctrl_lc_escalation.477855814 |
|
|
Jul 26 07:15:21 PM PDT 24 |
Jul 26 07:15:28 PM PDT 24 |
2084387375 ps |
| T906 |
/workspace/coverage/default/2.sram_ctrl_mem_walk.1933712695 |
|
|
Jul 26 07:10:44 PM PDT 24 |
Jul 26 07:10:50 PM PDT 24 |
306579870 ps |
| T907 |
/workspace/coverage/default/48.sram_ctrl_lc_escalation.757732446 |
|
|
Jul 26 07:18:08 PM PDT 24 |
Jul 26 07:18:13 PM PDT 24 |
1654290922 ps |
| T908 |
/workspace/coverage/default/22.sram_ctrl_stress_pipeline.3881191067 |
|
|
Jul 26 07:13:05 PM PDT 24 |
Jul 26 07:18:23 PM PDT 24 |
12804237746 ps |
| T909 |
/workspace/coverage/default/43.sram_ctrl_regwen.722302951 |
|
|
Jul 26 07:17:00 PM PDT 24 |
Jul 26 07:30:40 PM PDT 24 |
52799789869 ps |
| T910 |
/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.4163398932 |
|
|
Jul 26 07:11:59 PM PDT 24 |
Jul 26 07:21:56 PM PDT 24 |
16673849670 ps |
| T911 |
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.3924680729 |
|
|
Jul 26 07:11:14 PM PDT 24 |
Jul 26 07:21:04 PM PDT 24 |
9727891677 ps |
| T912 |
/workspace/coverage/default/42.sram_ctrl_smoke.1669563105 |
|
|
Jul 26 07:16:47 PM PDT 24 |
Jul 26 07:19:20 PM PDT 24 |
1317115373 ps |
| T913 |
/workspace/coverage/default/44.sram_ctrl_regwen.1154930473 |
|
|
Jul 26 07:17:22 PM PDT 24 |
Jul 26 07:21:30 PM PDT 24 |
5506005376 ps |
| T914 |
/workspace/coverage/default/37.sram_ctrl_alert_test.1243212102 |
|
|
Jul 26 07:15:49 PM PDT 24 |
Jul 26 07:15:50 PM PDT 24 |
45849989 ps |
| T915 |
/workspace/coverage/default/12.sram_ctrl_max_throughput.3064200847 |
|
|
Jul 26 07:11:38 PM PDT 24 |
Jul 26 07:13:38 PM PDT 24 |
531244808 ps |
| T916 |
/workspace/coverage/default/38.sram_ctrl_smoke.1051276016 |
|
|
Jul 26 07:15:58 PM PDT 24 |
Jul 26 07:15:59 PM PDT 24 |
106849541 ps |
| T917 |
/workspace/coverage/default/20.sram_ctrl_access_during_key_req.2637097300 |
|
|
Jul 26 07:12:49 PM PDT 24 |
Jul 26 07:38:00 PM PDT 24 |
17888440982 ps |
| T918 |
/workspace/coverage/default/20.sram_ctrl_executable.3608331395 |
|
|
Jul 26 07:12:50 PM PDT 24 |
Jul 26 07:13:03 PM PDT 24 |
513952070 ps |
| T919 |
/workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.3589496542 |
|
|
Jul 26 07:12:31 PM PDT 24 |
Jul 26 07:16:42 PM PDT 24 |
1506285969 ps |
| T920 |
/workspace/coverage/default/3.sram_ctrl_lc_escalation.3081002424 |
|
|
Jul 26 07:10:56 PM PDT 24 |
Jul 26 07:11:06 PM PDT 24 |
750664469 ps |
| T921 |
/workspace/coverage/default/33.sram_ctrl_partial_access_b2b.1190341959 |
|
|
Jul 26 07:15:00 PM PDT 24 |
Jul 26 07:21:45 PM PDT 24 |
14893873189 ps |
| T922 |
/workspace/coverage/default/36.sram_ctrl_alert_test.2346546239 |
|
|
Jul 26 07:15:46 PM PDT 24 |
Jul 26 07:15:47 PM PDT 24 |
40694322 ps |
| T923 |
/workspace/coverage/default/10.sram_ctrl_executable.1524101279 |
|
|
Jul 26 07:11:23 PM PDT 24 |
Jul 26 07:32:46 PM PDT 24 |
37177570262 ps |
| T924 |
/workspace/coverage/default/45.sram_ctrl_bijection.3536765793 |
|
|
Jul 26 07:17:18 PM PDT 24 |
Jul 26 07:18:25 PM PDT 24 |
16713607120 ps |
| T925 |
/workspace/coverage/default/26.sram_ctrl_access_during_key_req.2012850471 |
|
|
Jul 26 07:13:49 PM PDT 24 |
Jul 26 07:24:36 PM PDT 24 |
11516801467 ps |
| T926 |
/workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.130608607 |
|
|
Jul 26 07:12:39 PM PDT 24 |
Jul 26 07:15:30 PM PDT 24 |
3019951369 ps |
| T927 |
/workspace/coverage/default/17.sram_ctrl_access_during_key_req.1285288016 |
|
|
Jul 26 07:12:18 PM PDT 24 |
Jul 26 07:17:22 PM PDT 24 |
3077252249 ps |
| T928 |
/workspace/coverage/default/26.sram_ctrl_multiple_keys.3703349880 |
|
|
Jul 26 07:13:50 PM PDT 24 |
Jul 26 07:29:47 PM PDT 24 |
11595542463 ps |
| T929 |
/workspace/coverage/default/0.sram_ctrl_alert_test.1227234190 |
|
|
Jul 26 07:10:33 PM PDT 24 |
Jul 26 07:10:34 PM PDT 24 |
44920826 ps |
| T930 |
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.2419931148 |
|
|
Jul 26 07:11:37 PM PDT 24 |
Jul 26 07:14:54 PM PDT 24 |
4521739360 ps |
| T931 |
/workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.2958799217 |
|
|
Jul 26 07:13:21 PM PDT 24 |
Jul 26 07:14:54 PM PDT 24 |
139166883 ps |
| T932 |
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.3489220694 |
|
|
Jul 26 07:11:48 PM PDT 24 |
Jul 26 07:11:51 PM PDT 24 |
390086988 ps |
| T933 |
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.1770835748 |
|
|
Jul 26 07:11:36 PM PDT 24 |
Jul 26 07:16:31 PM PDT 24 |
44489496139 ps |
| T66 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3760644186 |
|
|
Jul 26 07:10:20 PM PDT 24 |
Jul 26 07:10:23 PM PDT 24 |
290168465 ps |
| T72 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3349394738 |
|
|
Jul 26 07:09:48 PM PDT 24 |
Jul 26 07:09:49 PM PDT 24 |
67402701 ps |
| T934 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2740420603 |
|
|
Jul 26 07:10:23 PM PDT 24 |
Jul 26 07:10:25 PM PDT 24 |
75163407 ps |
| T935 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2318387232 |
|
|
Jul 26 07:10:12 PM PDT 24 |
Jul 26 07:10:14 PM PDT 24 |
47359713 ps |
| T73 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.718488368 |
|
|
Jul 26 07:10:11 PM PDT 24 |
Jul 26 07:10:11 PM PDT 24 |
96483945 ps |
| T87 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.399794584 |
|
|
Jul 26 07:10:20 PM PDT 24 |
Jul 26 07:10:21 PM PDT 24 |
13944765 ps |
| T88 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1649173552 |
|
|
Jul 26 07:10:24 PM PDT 24 |
Jul 26 07:10:27 PM PDT 24 |
1416487384 ps |
| T936 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.874407835 |
|
|
Jul 26 07:10:32 PM PDT 24 |
Jul 26 07:10:35 PM PDT 24 |
58516360 ps |
| T67 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1389484237 |
|
|
Jul 26 07:10:11 PM PDT 24 |
Jul 26 07:10:12 PM PDT 24 |
306803425 ps |
| T111 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3219956500 |
|
|
Jul 26 07:10:29 PM PDT 24 |
Jul 26 07:10:30 PM PDT 24 |
13289195 ps |
| T937 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2726127254 |
|
|
Jul 26 07:10:09 PM PDT 24 |
Jul 26 07:10:13 PM PDT 24 |
393699287 ps |
| T68 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3436111933 |
|
|
Jul 26 07:10:09 PM PDT 24 |
Jul 26 07:10:11 PM PDT 24 |
112074909 ps |
| T89 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2871619546 |
|
|
Jul 26 07:10:00 PM PDT 24 |
Jul 26 07:10:02 PM PDT 24 |
46343834 ps |
| T130 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.449269419 |
|
|
Jul 26 07:09:59 PM PDT 24 |
Jul 26 07:10:00 PM PDT 24 |
100969213 ps |
| T112 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1842841470 |
|
|
Jul 26 07:10:10 PM PDT 24 |
Jul 26 07:10:11 PM PDT 24 |
75417004 ps |
| T938 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3138815589 |
|
|
Jul 26 07:10:09 PM PDT 24 |
Jul 26 07:10:11 PM PDT 24 |
89634007 ps |
| T939 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1234557994 |
|
|
Jul 26 07:10:20 PM PDT 24 |
Jul 26 07:10:26 PM PDT 24 |
537053869 ps |
| T135 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1144054325 |
|
|
Jul 26 07:10:23 PM PDT 24 |
Jul 26 07:10:24 PM PDT 24 |
88582017 ps |
| T940 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3199196796 |
|
|
Jul 26 07:10:10 PM PDT 24 |
Jul 26 07:10:15 PM PDT 24 |
537528005 ps |
| T941 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3749241884 |
|
|
Jul 26 07:09:51 PM PDT 24 |
Jul 26 07:09:53 PM PDT 24 |
329116610 ps |
| T942 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2797630225 |
|
|
Jul 26 07:10:08 PM PDT 24 |
Jul 26 07:10:09 PM PDT 24 |
33465809 ps |
| T90 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3002684601 |
|
|
Jul 26 07:09:58 PM PDT 24 |
Jul 26 07:10:00 PM PDT 24 |
847422252 ps |
| T943 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1656195848 |
|
|
Jul 26 07:10:01 PM PDT 24 |
Jul 26 07:10:03 PM PDT 24 |
176703356 ps |
| T91 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3740948823 |
|
|
Jul 26 07:10:29 PM PDT 24 |
Jul 26 07:10:30 PM PDT 24 |
34918605 ps |
| T133 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.730946368 |
|
|
Jul 26 07:10:12 PM PDT 24 |
Jul 26 07:10:15 PM PDT 24 |
674651974 ps |
| T92 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3682315355 |
|
|
Jul 26 07:09:59 PM PDT 24 |
Jul 26 07:10:00 PM PDT 24 |
39428821 ps |
| T93 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3039358435 |
|
|
Jul 26 07:10:11 PM PDT 24 |
Jul 26 07:10:15 PM PDT 24 |
3653642992 ps |
| T944 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2871955879 |
|
|
Jul 26 07:10:31 PM PDT 24 |
Jul 26 07:10:32 PM PDT 24 |
57735838 ps |
| T94 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2052622389 |
|
|
Jul 26 07:09:59 PM PDT 24 |
Jul 26 07:10:03 PM PDT 24 |
433799005 ps |
| T945 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.44248725 |
|
|
Jul 26 07:10:30 PM PDT 24 |
Jul 26 07:10:31 PM PDT 24 |
111243276 ps |
| T946 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1609946952 |
|
|
Jul 26 07:10:21 PM PDT 24 |
Jul 26 07:10:22 PM PDT 24 |
98187015 ps |
| T947 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.458006904 |
|
|
Jul 26 07:09:59 PM PDT 24 |
Jul 26 07:10:01 PM PDT 24 |
634051648 ps |
| T95 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2557785114 |
|
|
Jul 26 07:10:08 PM PDT 24 |
Jul 26 07:10:10 PM PDT 24 |
222072378 ps |
| T948 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3133055807 |
|
|
Jul 26 07:09:58 PM PDT 24 |
Jul 26 07:09:59 PM PDT 24 |
14153051 ps |
| T949 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.4083603602 |
|
|
Jul 26 07:10:00 PM PDT 24 |
Jul 26 07:10:01 PM PDT 24 |
18308370 ps |
| T131 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1903922501 |
|
|
Jul 26 07:10:31 PM PDT 24 |
Jul 26 07:10:33 PM PDT 24 |
161341289 ps |
| T97 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.4211752607 |
|
|
Jul 26 07:10:00 PM PDT 24 |
Jul 26 07:10:00 PM PDT 24 |
44300987 ps |
| T950 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.813090157 |
|
|
Jul 26 07:09:57 PM PDT 24 |
Jul 26 07:09:58 PM PDT 24 |
14054951 ps |
| T98 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1957754854 |
|
|
Jul 26 07:09:58 PM PDT 24 |
Jul 26 07:09:59 PM PDT 24 |
13072658 ps |
| T109 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.920357450 |
|
|
Jul 26 07:10:09 PM PDT 24 |
Jul 26 07:10:10 PM PDT 24 |
19345216 ps |
| T142 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1064534468 |
|
|
Jul 26 07:10:09 PM PDT 24 |
Jul 26 07:10:11 PM PDT 24 |
182147453 ps |
| T951 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1390872437 |
|
|
Jul 26 07:09:50 PM PDT 24 |
Jul 26 07:09:51 PM PDT 24 |
30709285 ps |
| T952 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.158351721 |
|
|
Jul 26 07:10:09 PM PDT 24 |
Jul 26 07:10:10 PM PDT 24 |
46559859 ps |
| T953 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2741976264 |
|
|
Jul 26 07:10:09 PM PDT 24 |
Jul 26 07:10:10 PM PDT 24 |
15248034 ps |
| T138 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1458377069 |
|
|
Jul 26 07:10:31 PM PDT 24 |
Jul 26 07:10:33 PM PDT 24 |
474757750 ps |
| T954 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3388806007 |
|
|
Jul 26 07:10:00 PM PDT 24 |
Jul 26 07:10:01 PM PDT 24 |
37621043 ps |
| T136 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2345892595 |
|
|
Jul 26 07:09:47 PM PDT 24 |
Jul 26 07:09:49 PM PDT 24 |
596992750 ps |
| T955 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.568167084 |
|
|
Jul 26 07:10:36 PM PDT 24 |
Jul 26 07:10:38 PM PDT 24 |
100191661 ps |
| T110 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.173654263 |
|
|
Jul 26 07:10:01 PM PDT 24 |
Jul 26 07:10:03 PM PDT 24 |
818488614 ps |
| T956 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2010994307 |
|
|
Jul 26 07:09:48 PM PDT 24 |
Jul 26 07:09:50 PM PDT 24 |
373013285 ps |
| T99 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3825843448 |
|
|
Jul 26 07:10:11 PM PDT 24 |
Jul 26 07:10:13 PM PDT 24 |
582724430 ps |
| T107 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3432808006 |
|
|
Jul 26 07:10:21 PM PDT 24 |
Jul 26 07:10:22 PM PDT 24 |
73353035 ps |
| T957 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3588259710 |
|
|
Jul 26 07:10:31 PM PDT 24 |
Jul 26 07:10:32 PM PDT 24 |
37249920 ps |
| T108 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2405315577 |
|
|
Jul 26 07:09:58 PM PDT 24 |
Jul 26 07:09:59 PM PDT 24 |
39886594 ps |
| T958 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.88566739 |
|
|
Jul 26 07:10:33 PM PDT 24 |
Jul 26 07:10:36 PM PDT 24 |
509687433 ps |
| T959 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1440776745 |
|
|
Jul 26 07:10:32 PM PDT 24 |
Jul 26 07:10:33 PM PDT 24 |
44945613 ps |
| T137 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1343109081 |
|
|
Jul 26 07:10:22 PM PDT 24 |
Jul 26 07:10:24 PM PDT 24 |
519056502 ps |
| T960 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1759204229 |
|
|
Jul 26 07:10:19 PM PDT 24 |
Jul 26 07:10:20 PM PDT 24 |
50381597 ps |
| T961 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1254067441 |
|
|
Jul 26 07:10:32 PM PDT 24 |
Jul 26 07:10:33 PM PDT 24 |
25544666 ps |
| T962 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.435819044 |
|
|
Jul 26 07:10:00 PM PDT 24 |
Jul 26 07:10:04 PM PDT 24 |
451255803 ps |
| T963 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.584555831 |
|
|
Jul 26 07:10:23 PM PDT 24 |
Jul 26 07:10:26 PM PDT 24 |
1647690882 ps |
| T964 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2127656300 |
|
|
Jul 26 07:10:12 PM PDT 24 |
Jul 26 07:10:17 PM PDT 24 |
504655501 ps |
| T965 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1820225115 |
|
|
Jul 26 07:10:21 PM PDT 24 |
Jul 26 07:10:24 PM PDT 24 |
1571786061 ps |
| T966 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1552174635 |
|
|
Jul 26 07:10:21 PM PDT 24 |
Jul 26 07:10:21 PM PDT 24 |
38030775 ps |
| T967 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3940767466 |
|
|
Jul 26 07:10:29 PM PDT 24 |
Jul 26 07:10:32 PM PDT 24 |
1646192495 ps |
| T968 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.4096212110 |
|
|
Jul 26 07:10:32 PM PDT 24 |
Jul 26 07:10:33 PM PDT 24 |
18738062 ps |
| T969 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.787727900 |
|
|
Jul 26 07:09:59 PM PDT 24 |
Jul 26 07:10:04 PM PDT 24 |
266747431 ps |
| T970 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.837580948 |
|
|
Jul 26 07:10:33 PM PDT 24 |
Jul 26 07:10:36 PM PDT 24 |
93618299 ps |
| T971 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.553136338 |
|
|
Jul 26 07:10:20 PM PDT 24 |
Jul 26 07:10:22 PM PDT 24 |
863814888 ps |
| T972 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.4213017745 |
|
|
Jul 26 07:10:20 PM PDT 24 |
Jul 26 07:10:23 PM PDT 24 |
1653871485 ps |
| T973 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2351387082 |
|
|
Jul 26 07:10:20 PM PDT 24 |
Jul 26 07:10:21 PM PDT 24 |
56135441 ps |
| T974 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.76827375 |
|
|
Jul 26 07:10:21 PM PDT 24 |
Jul 26 07:10:21 PM PDT 24 |
13111331 ps |
| T975 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.143601987 |
|
|
Jul 26 07:10:10 PM PDT 24 |
Jul 26 07:10:11 PM PDT 24 |
44141935 ps |
| T976 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3057088290 |
|
|
Jul 26 07:10:00 PM PDT 24 |
Jul 26 07:10:01 PM PDT 24 |
38745220 ps |
| T977 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1351101623 |
|
|
Jul 26 07:09:59 PM PDT 24 |
Jul 26 07:10:00 PM PDT 24 |
116538343 ps |
| T978 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1476968890 |
|
|
Jul 26 07:10:09 PM PDT 24 |
Jul 26 07:10:11 PM PDT 24 |
46740895 ps |
| T979 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3771018787 |
|
|
Jul 26 07:10:22 PM PDT 24 |
Jul 26 07:10:24 PM PDT 24 |
91829131 ps |
| T980 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3178187392 |
|
|
Jul 26 07:10:12 PM PDT 24 |
Jul 26 07:10:13 PM PDT 24 |
91328970 ps |
| T981 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1832342064 |
|
|
Jul 26 07:10:01 PM PDT 24 |
Jul 26 07:10:02 PM PDT 24 |
24115862 ps |
| T982 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3827622920 |
|
|
Jul 26 07:09:48 PM PDT 24 |
Jul 26 07:09:52 PM PDT 24 |
1666883480 ps |
| T983 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2288176191 |
|
|
Jul 26 07:10:20 PM PDT 24 |
Jul 26 07:10:21 PM PDT 24 |
22470307 ps |
| T984 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2484684085 |
|
|
Jul 26 07:10:32 PM PDT 24 |
Jul 26 07:10:34 PM PDT 24 |
38633221 ps |
| T985 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1908322113 |
|
|
Jul 26 07:09:51 PM PDT 24 |
Jul 26 07:09:53 PM PDT 24 |
104648674 ps |
| T140 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3133804454 |
|
|
Jul 26 07:09:52 PM PDT 24 |
Jul 26 07:09:54 PM PDT 24 |
232520393 ps |
| T986 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3126576799 |
|
|
Jul 26 07:10:18 PM PDT 24 |
Jul 26 07:10:20 PM PDT 24 |
153178038 ps |
| T987 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.4120908580 |
|
|
Jul 26 07:10:30 PM PDT 24 |
Jul 26 07:10:31 PM PDT 24 |
11339814 ps |
| T988 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3466540248 |
|
|
Jul 26 07:10:35 PM PDT 24 |
Jul 26 07:10:39 PM PDT 24 |
137367918 ps |
| T989 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3928549897 |
|
|
Jul 26 07:10:09 PM PDT 24 |
Jul 26 07:10:13 PM PDT 24 |
805715813 ps |
| T990 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3266865057 |
|
|
Jul 26 07:10:10 PM PDT 24 |
Jul 26 07:10:11 PM PDT 24 |
55870115 ps |
| T991 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.299046684 |
|
|
Jul 26 07:10:24 PM PDT 24 |
Jul 26 07:10:25 PM PDT 24 |
18007254 ps |
| T992 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.81465331 |
|
|
Jul 26 07:10:22 PM PDT 24 |
Jul 26 07:10:23 PM PDT 24 |
24659721 ps |
| T993 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2628930521 |
|
|
Jul 26 07:09:58 PM PDT 24 |
Jul 26 07:09:58 PM PDT 24 |
26747748 ps |
| T994 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2470963217 |
|
|
Jul 26 07:09:49 PM PDT 24 |
Jul 26 07:09:49 PM PDT 24 |
39516622 ps |
| T995 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1950587012 |
|
|
Jul 26 07:09:59 PM PDT 24 |
Jul 26 07:10:00 PM PDT 24 |
56272666 ps |
| T996 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1440587500 |
|
|
Jul 26 07:10:21 PM PDT 24 |
Jul 26 07:10:22 PM PDT 24 |
115615053 ps |
| T997 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1604343609 |
|
|
Jul 26 07:09:49 PM PDT 24 |
Jul 26 07:09:51 PM PDT 24 |
1868450697 ps |
| T998 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2178760970 |
|
|
Jul 26 07:10:08 PM PDT 24 |
Jul 26 07:10:12 PM PDT 24 |
1614976305 ps |
| T999 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2924231502 |
|
|
Jul 26 07:10:20 PM PDT 24 |
Jul 26 07:10:21 PM PDT 24 |
47176361 ps |
| T1000 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2221121073 |
|
|
Jul 26 07:09:59 PM PDT 24 |
Jul 26 07:10:00 PM PDT 24 |
89741392 ps |
| T1001 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1930653062 |
|
|
Jul 26 07:09:52 PM PDT 24 |
Jul 26 07:09:53 PM PDT 24 |
65291451 ps |
| T132 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.893615654 |
|
|
Jul 26 07:10:21 PM PDT 24 |
Jul 26 07:10:23 PM PDT 24 |
95763469 ps |
| T1002 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2000430326 |
|
|
Jul 26 07:10:12 PM PDT 24 |
Jul 26 07:10:13 PM PDT 24 |
34026532 ps |
| T1003 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1727245677 |
|
|
Jul 26 07:10:30 PM PDT 24 |
Jul 26 07:10:34 PM PDT 24 |
400345498 ps |