| T793 |
/workspace/coverage/default/41.sram_ctrl_ram_cfg.1448548826 |
|
|
Jul 28 06:36:15 PM PDT 24 |
Jul 28 06:36:16 PM PDT 24 |
139030868 ps |
| T794 |
/workspace/coverage/default/14.sram_ctrl_bijection.2909204876 |
|
|
Jul 28 06:28:11 PM PDT 24 |
Jul 28 06:28:47 PM PDT 24 |
2229261718 ps |
| T795 |
/workspace/coverage/default/24.sram_ctrl_executable.824285369 |
|
|
Jul 28 06:31:26 PM PDT 24 |
Jul 28 06:43:19 PM PDT 24 |
7639400764 ps |
| T796 |
/workspace/coverage/default/26.sram_ctrl_partial_access_b2b.2007472731 |
|
|
Jul 28 06:31:50 PM PDT 24 |
Jul 28 06:43:10 PM PDT 24 |
473278362595 ps |
| T797 |
/workspace/coverage/default/8.sram_ctrl_stress_all.2473753173 |
|
|
Jul 28 06:26:31 PM PDT 24 |
Jul 28 06:54:25 PM PDT 24 |
66741819881 ps |
| T798 |
/workspace/coverage/default/39.sram_ctrl_stress_all.2195659314 |
|
|
Jul 28 06:35:45 PM PDT 24 |
Jul 28 07:11:38 PM PDT 24 |
169397590869 ps |
| T799 |
/workspace/coverage/default/14.sram_ctrl_partial_access_b2b.1776789381 |
|
|
Jul 28 06:28:21 PM PDT 24 |
Jul 28 06:35:27 PM PDT 24 |
218432612007 ps |
| T800 |
/workspace/coverage/default/43.sram_ctrl_stress_all.3878837688 |
|
|
Jul 28 06:36:49 PM PDT 24 |
Jul 28 07:19:44 PM PDT 24 |
46001638166 ps |
| T801 |
/workspace/coverage/default/21.sram_ctrl_partial_access.1382596722 |
|
|
Jul 28 06:30:24 PM PDT 24 |
Jul 28 06:30:27 PM PDT 24 |
342310066 ps |
| T802 |
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3896714819 |
|
|
Jul 28 06:37:34 PM PDT 24 |
Jul 28 06:43:11 PM PDT 24 |
2765130484 ps |
| T803 |
/workspace/coverage/default/0.sram_ctrl_regwen.157265453 |
|
|
Jul 28 06:24:29 PM PDT 24 |
Jul 28 06:45:22 PM PDT 24 |
14052970484 ps |
| T804 |
/workspace/coverage/default/3.sram_ctrl_partial_access.1470891325 |
|
|
Jul 28 06:25:05 PM PDT 24 |
Jul 28 06:25:15 PM PDT 24 |
385104879 ps |
| T805 |
/workspace/coverage/default/2.sram_ctrl_stress_pipeline.2085892748 |
|
|
Jul 28 06:24:52 PM PDT 24 |
Jul 28 06:28:03 PM PDT 24 |
2158481686 ps |
| T806 |
/workspace/coverage/default/8.sram_ctrl_bijection.395076009 |
|
|
Jul 28 06:26:16 PM PDT 24 |
Jul 28 06:27:00 PM PDT 24 |
8685065406 ps |
| T807 |
/workspace/coverage/default/43.sram_ctrl_partial_access.2442173579 |
|
|
Jul 28 06:36:37 PM PDT 24 |
Jul 28 06:36:53 PM PDT 24 |
1407047585 ps |
| T808 |
/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.54374691 |
|
|
Jul 28 06:36:00 PM PDT 24 |
Jul 28 06:37:18 PM PDT 24 |
123922337 ps |
| T809 |
/workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.450618544 |
|
|
Jul 28 06:31:20 PM PDT 24 |
Jul 28 06:31:49 PM PDT 24 |
381144330 ps |
| T810 |
/workspace/coverage/default/25.sram_ctrl_partial_access.4290088922 |
|
|
Jul 28 06:31:32 PM PDT 24 |
Jul 28 06:31:38 PM PDT 24 |
1144767258 ps |
| T811 |
/workspace/coverage/default/2.sram_ctrl_access_during_key_req.722661075 |
|
|
Jul 28 06:24:53 PM PDT 24 |
Jul 28 06:44:02 PM PDT 24 |
35408197106 ps |
| T812 |
/workspace/coverage/default/20.sram_ctrl_ram_cfg.1116023243 |
|
|
Jul 28 06:30:17 PM PDT 24 |
Jul 28 06:30:18 PM PDT 24 |
30093675 ps |
| T813 |
/workspace/coverage/default/15.sram_ctrl_stress_all.182140334 |
|
|
Jul 28 06:28:53 PM PDT 24 |
Jul 28 07:08:22 PM PDT 24 |
8802920173 ps |
| T814 |
/workspace/coverage/default/2.sram_ctrl_partial_access.1893255838 |
|
|
Jul 28 06:24:56 PM PDT 24 |
Jul 28 06:25:25 PM PDT 24 |
317308043 ps |
| T815 |
/workspace/coverage/default/21.sram_ctrl_ram_cfg.1243900302 |
|
|
Jul 28 06:30:40 PM PDT 24 |
Jul 28 06:30:40 PM PDT 24 |
100134446 ps |
| T816 |
/workspace/coverage/default/19.sram_ctrl_alert_test.2907017403 |
|
|
Jul 28 06:30:09 PM PDT 24 |
Jul 28 06:30:10 PM PDT 24 |
58924132 ps |
| T817 |
/workspace/coverage/default/35.sram_ctrl_regwen.3121543948 |
|
|
Jul 28 06:34:39 PM PDT 24 |
Jul 28 06:47:08 PM PDT 24 |
17608591478 ps |
| T818 |
/workspace/coverage/default/28.sram_ctrl_partial_access.2578792934 |
|
|
Jul 28 06:32:12 PM PDT 24 |
Jul 28 06:32:14 PM PDT 24 |
56178596 ps |
| T819 |
/workspace/coverage/default/41.sram_ctrl_regwen.3706517646 |
|
|
Jul 28 06:36:15 PM PDT 24 |
Jul 28 06:54:34 PM PDT 24 |
12982957802 ps |
| T820 |
/workspace/coverage/default/26.sram_ctrl_multiple_keys.2731021359 |
|
|
Jul 28 06:31:51 PM PDT 24 |
Jul 28 06:39:40 PM PDT 24 |
8080064317 ps |
| T821 |
/workspace/coverage/default/46.sram_ctrl_alert_test.3890623770 |
|
|
Jul 28 06:37:46 PM PDT 24 |
Jul 28 06:37:47 PM PDT 24 |
24629104 ps |
| T822 |
/workspace/coverage/default/25.sram_ctrl_ram_cfg.20412278 |
|
|
Jul 28 06:31:37 PM PDT 24 |
Jul 28 06:31:37 PM PDT 24 |
294622798 ps |
| T823 |
/workspace/coverage/default/19.sram_ctrl_bijection.564611991 |
|
|
Jul 28 06:29:46 PM PDT 24 |
Jul 28 06:30:04 PM PDT 24 |
1138894923 ps |
| T824 |
/workspace/coverage/default/28.sram_ctrl_executable.378241712 |
|
|
Jul 28 06:32:26 PM PDT 24 |
Jul 28 06:40:07 PM PDT 24 |
21087854648 ps |
| T825 |
/workspace/coverage/default/26.sram_ctrl_ram_cfg.234544792 |
|
|
Jul 28 06:31:56 PM PDT 24 |
Jul 28 06:31:57 PM PDT 24 |
51173106 ps |
| T826 |
/workspace/coverage/default/47.sram_ctrl_lc_escalation.2474868971 |
|
|
Jul 28 06:37:53 PM PDT 24 |
Jul 28 06:37:57 PM PDT 24 |
1667820517 ps |
| T827 |
/workspace/coverage/default/31.sram_ctrl_regwen.1591713923 |
|
|
Jul 28 06:33:22 PM PDT 24 |
Jul 28 06:41:43 PM PDT 24 |
7425617726 ps |
| T828 |
/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.4174998129 |
|
|
Jul 28 06:34:53 PM PDT 24 |
Jul 28 06:43:37 PM PDT 24 |
23714138837 ps |
| T829 |
/workspace/coverage/default/37.sram_ctrl_multiple_keys.684395490 |
|
|
Jul 28 06:35:06 PM PDT 24 |
Jul 28 06:53:56 PM PDT 24 |
25820265077 ps |
| T830 |
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.4078836735 |
|
|
Jul 28 06:38:35 PM PDT 24 |
Jul 28 06:38:39 PM PDT 24 |
53969304 ps |
| T831 |
/workspace/coverage/default/17.sram_ctrl_stress_all.115542162 |
|
|
Jul 28 06:29:24 PM PDT 24 |
Jul 28 06:29:54 PM PDT 24 |
638863320 ps |
| T832 |
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.1639772917 |
|
|
Jul 28 06:25:35 PM PDT 24 |
Jul 28 06:34:07 PM PDT 24 |
2326582030 ps |
| T833 |
/workspace/coverage/default/38.sram_ctrl_smoke.1849047355 |
|
|
Jul 28 06:35:23 PM PDT 24 |
Jul 28 06:35:24 PM PDT 24 |
26531685 ps |
| T834 |
/workspace/coverage/default/49.sram_ctrl_bijection.3099293112 |
|
|
Jul 28 06:38:26 PM PDT 24 |
Jul 28 06:39:48 PM PDT 24 |
49918474728 ps |
| T835 |
/workspace/coverage/default/39.sram_ctrl_executable.3120136799 |
|
|
Jul 28 06:35:44 PM PDT 24 |
Jul 28 06:56:02 PM PDT 24 |
26883222258 ps |
| T836 |
/workspace/coverage/default/29.sram_ctrl_mem_walk.138929687 |
|
|
Jul 28 06:32:45 PM PDT 24 |
Jul 28 06:32:56 PM PDT 24 |
1335616914 ps |
| T837 |
/workspace/coverage/default/32.sram_ctrl_stress_pipeline.1669104058 |
|
|
Jul 28 06:33:34 PM PDT 24 |
Jul 28 06:41:02 PM PDT 24 |
8384473441 ps |
| T838 |
/workspace/coverage/default/19.sram_ctrl_ram_cfg.2287584580 |
|
|
Jul 28 06:30:10 PM PDT 24 |
Jul 28 06:30:11 PM PDT 24 |
89941409 ps |
| T126 |
/workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.1412424746 |
|
|
Jul 28 06:25:01 PM PDT 24 |
Jul 28 06:25:10 PM PDT 24 |
269978728 ps |
| T839 |
/workspace/coverage/default/30.sram_ctrl_lc_escalation.4277077579 |
|
|
Jul 28 06:32:55 PM PDT 24 |
Jul 28 06:33:05 PM PDT 24 |
5217794421 ps |
| T840 |
/workspace/coverage/default/0.sram_ctrl_lc_escalation.3629932560 |
|
|
Jul 28 06:24:29 PM PDT 24 |
Jul 28 06:24:35 PM PDT 24 |
1066700400 ps |
| T841 |
/workspace/coverage/default/31.sram_ctrl_access_during_key_req.370761597 |
|
|
Jul 28 06:33:22 PM PDT 24 |
Jul 28 06:49:18 PM PDT 24 |
8917884159 ps |
| T842 |
/workspace/coverage/default/19.sram_ctrl_regwen.2065508857 |
|
|
Jul 28 06:30:02 PM PDT 24 |
Jul 28 06:48:57 PM PDT 24 |
12005571605 ps |
| T843 |
/workspace/coverage/default/17.sram_ctrl_stress_pipeline.380327842 |
|
|
Jul 28 06:29:19 PM PDT 24 |
Jul 28 06:33:47 PM PDT 24 |
2824644576 ps |
| T844 |
/workspace/coverage/default/14.sram_ctrl_alert_test.4192558314 |
|
|
Jul 28 06:28:31 PM PDT 24 |
Jul 28 06:28:32 PM PDT 24 |
17813557 ps |
| T845 |
/workspace/coverage/default/38.sram_ctrl_mem_walk.1923520448 |
|
|
Jul 28 06:35:40 PM PDT 24 |
Jul 28 06:35:52 PM PDT 24 |
2965330926 ps |
| T846 |
/workspace/coverage/default/11.sram_ctrl_partial_access.3337029985 |
|
|
Jul 28 06:27:16 PM PDT 24 |
Jul 28 06:29:48 PM PDT 24 |
3015036418 ps |
| T847 |
/workspace/coverage/default/18.sram_ctrl_access_during_key_req.3205227626 |
|
|
Jul 28 06:29:41 PM PDT 24 |
Jul 28 06:37:45 PM PDT 24 |
1374899616 ps |
| T848 |
/workspace/coverage/default/33.sram_ctrl_mem_walk.2494914451 |
|
|
Jul 28 06:34:07 PM PDT 24 |
Jul 28 06:34:15 PM PDT 24 |
273310399 ps |
| T849 |
/workspace/coverage/default/35.sram_ctrl_ram_cfg.2027009407 |
|
|
Jul 28 06:34:39 PM PDT 24 |
Jul 28 06:34:40 PM PDT 24 |
91388704 ps |
| T850 |
/workspace/coverage/default/32.sram_ctrl_max_throughput.3190324133 |
|
|
Jul 28 06:33:44 PM PDT 24 |
Jul 28 06:35:47 PM PDT 24 |
264739321 ps |
| T851 |
/workspace/coverage/default/24.sram_ctrl_alert_test.1307602987 |
|
|
Jul 28 06:31:26 PM PDT 24 |
Jul 28 06:31:27 PM PDT 24 |
108401994 ps |
| T852 |
/workspace/coverage/default/12.sram_ctrl_partial_access.3326699648 |
|
|
Jul 28 06:27:30 PM PDT 24 |
Jul 28 06:27:37 PM PDT 24 |
354835396 ps |
| T853 |
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.2869026381 |
|
|
Jul 28 06:27:07 PM PDT 24 |
Jul 28 06:29:57 PM PDT 24 |
4547108362 ps |
| T854 |
/workspace/coverage/default/32.sram_ctrl_stress_all.167315760 |
|
|
Jul 28 06:33:45 PM PDT 24 |
Jul 28 06:46:55 PM PDT 24 |
19004190520 ps |
| T855 |
/workspace/coverage/default/39.sram_ctrl_regwen.1321891486 |
|
|
Jul 28 06:35:40 PM PDT 24 |
Jul 28 06:53:43 PM PDT 24 |
36295152838 ps |
| T856 |
/workspace/coverage/default/22.sram_ctrl_bijection.2457453406 |
|
|
Jul 28 06:30:50 PM PDT 24 |
Jul 28 06:31:26 PM PDT 24 |
2466639158 ps |
| T857 |
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.1569193716 |
|
|
Jul 28 06:26:04 PM PDT 24 |
Jul 28 06:30:50 PM PDT 24 |
7628977124 ps |
| T858 |
/workspace/coverage/default/38.sram_ctrl_mem_partial_access.532942481 |
|
|
Jul 28 06:35:30 PM PDT 24 |
Jul 28 06:35:33 PM PDT 24 |
46031841 ps |
| T859 |
/workspace/coverage/default/13.sram_ctrl_stress_pipeline.419418804 |
|
|
Jul 28 06:27:53 PM PDT 24 |
Jul 28 06:33:08 PM PDT 24 |
8006142895 ps |
| T860 |
/workspace/coverage/default/16.sram_ctrl_regwen.3299099396 |
|
|
Jul 28 06:29:12 PM PDT 24 |
Jul 28 06:45:05 PM PDT 24 |
38890454502 ps |
| T861 |
/workspace/coverage/default/17.sram_ctrl_regwen.1542559470 |
|
|
Jul 28 06:29:24 PM PDT 24 |
Jul 28 06:45:14 PM PDT 24 |
6661211878 ps |
| T862 |
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.3436574511 |
|
|
Jul 28 06:37:54 PM PDT 24 |
Jul 28 06:37:56 PM PDT 24 |
149122539 ps |
| T863 |
/workspace/coverage/default/23.sram_ctrl_partial_access_b2b.3931173223 |
|
|
Jul 28 06:30:56 PM PDT 24 |
Jul 28 06:35:04 PM PDT 24 |
9540180864 ps |
| T864 |
/workspace/coverage/default/24.sram_ctrl_access_during_key_req.171150005 |
|
|
Jul 28 06:31:21 PM PDT 24 |
Jul 28 06:41:22 PM PDT 24 |
2301861410 ps |
| T865 |
/workspace/coverage/default/35.sram_ctrl_lc_escalation.1249065522 |
|
|
Jul 28 06:34:34 PM PDT 24 |
Jul 28 06:34:40 PM PDT 24 |
1594959405 ps |
| T866 |
/workspace/coverage/default/14.sram_ctrl_stress_all.1361422705 |
|
|
Jul 28 06:28:31 PM PDT 24 |
Jul 28 07:31:20 PM PDT 24 |
13870913864 ps |
| T867 |
/workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.855796080 |
|
|
Jul 28 06:34:40 PM PDT 24 |
Jul 28 06:38:24 PM PDT 24 |
4537707306 ps |
| T868 |
/workspace/coverage/default/15.sram_ctrl_mem_walk.1406036864 |
|
|
Jul 28 06:28:40 PM PDT 24 |
Jul 28 06:28:46 PM PDT 24 |
249751120 ps |
| T869 |
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.2677850618 |
|
|
Jul 28 06:36:23 PM PDT 24 |
Jul 28 06:36:25 PM PDT 24 |
67124673 ps |
| T870 |
/workspace/coverage/default/35.sram_ctrl_bijection.2918350031 |
|
|
Jul 28 06:34:23 PM PDT 24 |
Jul 28 06:35:37 PM PDT 24 |
6634777569 ps |
| T871 |
/workspace/coverage/default/2.sram_ctrl_multiple_keys.2617487231 |
|
|
Jul 28 06:24:54 PM PDT 24 |
Jul 28 06:34:52 PM PDT 24 |
11217046271 ps |
| T872 |
/workspace/coverage/default/23.sram_ctrl_stress_all.772436770 |
|
|
Jul 28 06:31:16 PM PDT 24 |
Jul 28 06:46:24 PM PDT 24 |
29030090632 ps |
| T873 |
/workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.1325637822 |
|
|
Jul 28 06:36:09 PM PDT 24 |
Jul 28 06:37:11 PM PDT 24 |
3379842467 ps |
| T874 |
/workspace/coverage/default/29.sram_ctrl_smoke.389551993 |
|
|
Jul 28 06:32:31 PM PDT 24 |
Jul 28 06:32:35 PM PDT 24 |
314510898 ps |
| T875 |
/workspace/coverage/default/10.sram_ctrl_multiple_keys.3659016967 |
|
|
Jul 28 06:26:50 PM PDT 24 |
Jul 28 06:47:59 PM PDT 24 |
13420883131 ps |
| T876 |
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.977200034 |
|
|
Jul 28 06:37:21 PM PDT 24 |
Jul 28 06:37:28 PM PDT 24 |
357480262 ps |
| T877 |
/workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.980452820 |
|
|
Jul 28 06:31:36 PM PDT 24 |
Jul 28 06:31:41 PM PDT 24 |
114084632 ps |
| T878 |
/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.1775289571 |
|
|
Jul 28 06:30:50 PM PDT 24 |
Jul 28 06:37:06 PM PDT 24 |
18766504890 ps |
| T879 |
/workspace/coverage/default/49.sram_ctrl_regwen.962757999 |
|
|
Jul 28 06:38:33 PM PDT 24 |
Jul 28 06:41:34 PM PDT 24 |
4753530646 ps |
| T880 |
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.2152082471 |
|
|
Jul 28 06:36:45 PM PDT 24 |
Jul 28 06:39:59 PM PDT 24 |
5255327212 ps |
| T881 |
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.297129091 |
|
|
Jul 28 06:38:08 PM PDT 24 |
Jul 28 06:43:32 PM PDT 24 |
3446589138 ps |
| T882 |
/workspace/coverage/default/3.sram_ctrl_bijection.818003239 |
|
|
Jul 28 06:25:07 PM PDT 24 |
Jul 28 06:25:56 PM PDT 24 |
2184259889 ps |
| T883 |
/workspace/coverage/default/47.sram_ctrl_ram_cfg.465461354 |
|
|
Jul 28 06:38:04 PM PDT 24 |
Jul 28 06:38:05 PM PDT 24 |
139067263 ps |
| T884 |
/workspace/coverage/default/12.sram_ctrl_lc_escalation.1123220322 |
|
|
Jul 28 06:27:37 PM PDT 24 |
Jul 28 06:27:44 PM PDT 24 |
451201332 ps |
| T885 |
/workspace/coverage/default/21.sram_ctrl_multiple_keys.3143855512 |
|
|
Jul 28 06:30:17 PM PDT 24 |
Jul 28 06:46:36 PM PDT 24 |
18616640627 ps |
| T886 |
/workspace/coverage/default/32.sram_ctrl_lc_escalation.3856414599 |
|
|
Jul 28 06:33:40 PM PDT 24 |
Jul 28 06:33:42 PM PDT 24 |
263781930 ps |
| T887 |
/workspace/coverage/default/19.sram_ctrl_stress_pipeline.3057689552 |
|
|
Jul 28 06:29:50 PM PDT 24 |
Jul 28 06:33:47 PM PDT 24 |
3608654149 ps |
| T888 |
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.4279822345 |
|
|
Jul 28 06:25:52 PM PDT 24 |
Jul 28 06:25:56 PM PDT 24 |
72163042 ps |
| T889 |
/workspace/coverage/default/23.sram_ctrl_access_during_key_req.2548485309 |
|
|
Jul 28 06:31:00 PM PDT 24 |
Jul 28 06:31:33 PM PDT 24 |
532014763 ps |
| T890 |
/workspace/coverage/default/30.sram_ctrl_ram_cfg.2981598577 |
|
|
Jul 28 06:33:03 PM PDT 24 |
Jul 28 06:33:04 PM PDT 24 |
49531745 ps |
| T891 |
/workspace/coverage/default/25.sram_ctrl_stress_pipeline.2556418246 |
|
|
Jul 28 06:31:33 PM PDT 24 |
Jul 28 06:37:39 PM PDT 24 |
14939781608 ps |
| T127 |
/workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.3075436721 |
|
|
Jul 28 06:35:31 PM PDT 24 |
Jul 28 06:35:43 PM PDT 24 |
611434550 ps |
| T892 |
/workspace/coverage/default/44.sram_ctrl_regwen.979420532 |
|
|
Jul 28 06:37:03 PM PDT 24 |
Jul 28 06:42:20 PM PDT 24 |
2434915203 ps |
| T893 |
/workspace/coverage/default/14.sram_ctrl_regwen.4064452302 |
|
|
Jul 28 06:28:22 PM PDT 24 |
Jul 28 06:36:53 PM PDT 24 |
1777433161 ps |
| T894 |
/workspace/coverage/default/23.sram_ctrl_multiple_keys.1588048181 |
|
|
Jul 28 06:30:52 PM PDT 24 |
Jul 28 06:47:00 PM PDT 24 |
6057382360 ps |
| T895 |
/workspace/coverage/default/29.sram_ctrl_multiple_keys.3626973976 |
|
|
Jul 28 06:32:30 PM PDT 24 |
Jul 28 06:40:06 PM PDT 24 |
6473656643 ps |
| T896 |
/workspace/coverage/default/8.sram_ctrl_ram_cfg.3676446751 |
|
|
Jul 28 06:26:26 PM PDT 24 |
Jul 28 06:26:27 PM PDT 24 |
202156235 ps |
| T897 |
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.1382868828 |
|
|
Jul 28 06:24:40 PM PDT 24 |
Jul 28 06:25:24 PM PDT 24 |
993085061 ps |
| T898 |
/workspace/coverage/default/31.sram_ctrl_multiple_keys.3350890577 |
|
|
Jul 28 06:33:15 PM PDT 24 |
Jul 28 06:43:02 PM PDT 24 |
1731968869 ps |
| T899 |
/workspace/coverage/default/43.sram_ctrl_multiple_keys.2244440673 |
|
|
Jul 28 06:36:37 PM PDT 24 |
Jul 28 06:42:33 PM PDT 24 |
840982891 ps |
| T900 |
/workspace/coverage/default/15.sram_ctrl_regwen.2585595829 |
|
|
Jul 28 06:28:42 PM PDT 24 |
Jul 28 06:46:22 PM PDT 24 |
7664808394 ps |
| T901 |
/workspace/coverage/default/11.sram_ctrl_lc_escalation.328727334 |
|
|
Jul 28 06:27:15 PM PDT 24 |
Jul 28 06:27:22 PM PDT 24 |
551516591 ps |
| T902 |
/workspace/coverage/default/28.sram_ctrl_partial_access_b2b.2226468994 |
|
|
Jul 28 06:32:22 PM PDT 24 |
Jul 28 06:41:26 PM PDT 24 |
92354283175 ps |
| T903 |
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.1206927189 |
|
|
Jul 28 06:27:20 PM PDT 24 |
Jul 28 06:27:57 PM PDT 24 |
520357200 ps |
| T904 |
/workspace/coverage/default/38.sram_ctrl_access_during_key_req.2449348505 |
|
|
Jul 28 06:35:24 PM PDT 24 |
Jul 28 06:49:32 PM PDT 24 |
33264262198 ps |
| T905 |
/workspace/coverage/default/29.sram_ctrl_ram_cfg.4014601877 |
|
|
Jul 28 06:32:44 PM PDT 24 |
Jul 28 06:32:45 PM PDT 24 |
28332568 ps |
| T906 |
/workspace/coverage/default/31.sram_ctrl_mem_walk.4168427922 |
|
|
Jul 28 06:33:30 PM PDT 24 |
Jul 28 06:33:41 PM PDT 24 |
667879547 ps |
| T907 |
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.2810771952 |
|
|
Jul 28 06:37:47 PM PDT 24 |
Jul 28 06:37:52 PM PDT 24 |
128275491 ps |
| T908 |
/workspace/coverage/default/30.sram_ctrl_multiple_keys.1460911409 |
|
|
Jul 28 06:32:49 PM PDT 24 |
Jul 28 06:50:01 PM PDT 24 |
17429573604 ps |
| T909 |
/workspace/coverage/default/35.sram_ctrl_max_throughput.730939013 |
|
|
Jul 28 06:34:35 PM PDT 24 |
Jul 28 06:34:53 PM PDT 24 |
145439118 ps |
| T910 |
/workspace/coverage/default/16.sram_ctrl_partial_access.360005574 |
|
|
Jul 28 06:28:57 PM PDT 24 |
Jul 28 06:29:06 PM PDT 24 |
79605207 ps |
| T911 |
/workspace/coverage/default/44.sram_ctrl_ram_cfg.2281080489 |
|
|
Jul 28 06:37:03 PM PDT 24 |
Jul 28 06:37:04 PM PDT 24 |
40108159 ps |
| T912 |
/workspace/coverage/default/47.sram_ctrl_regwen.4267442310 |
|
|
Jul 28 06:38:04 PM PDT 24 |
Jul 28 06:48:26 PM PDT 24 |
9214974191 ps |
| T913 |
/workspace/coverage/default/44.sram_ctrl_lc_escalation.1075316371 |
|
|
Jul 28 06:37:00 PM PDT 24 |
Jul 28 06:37:09 PM PDT 24 |
3003830528 ps |
| T914 |
/workspace/coverage/default/40.sram_ctrl_alert_test.1438014302 |
|
|
Jul 28 06:36:09 PM PDT 24 |
Jul 28 06:36:09 PM PDT 24 |
17116028 ps |
| T915 |
/workspace/coverage/default/36.sram_ctrl_alert_test.3514777712 |
|
|
Jul 28 06:35:03 PM PDT 24 |
Jul 28 06:35:03 PM PDT 24 |
28874383 ps |
| T916 |
/workspace/coverage/default/37.sram_ctrl_stress_pipeline.3791152923 |
|
|
Jul 28 06:35:09 PM PDT 24 |
Jul 28 06:38:57 PM PDT 24 |
9420710409 ps |
| T917 |
/workspace/coverage/default/31.sram_ctrl_alert_test.2379798567 |
|
|
Jul 28 06:33:31 PM PDT 24 |
Jul 28 06:33:31 PM PDT 24 |
125031077 ps |
| T918 |
/workspace/coverage/default/27.sram_ctrl_multiple_keys.950891988 |
|
|
Jul 28 06:32:03 PM PDT 24 |
Jul 28 06:38:10 PM PDT 24 |
24255979151 ps |
| T919 |
/workspace/coverage/default/41.sram_ctrl_alert_test.1283186336 |
|
|
Jul 28 06:36:22 PM PDT 24 |
Jul 28 06:36:23 PM PDT 24 |
34068973 ps |
| T920 |
/workspace/coverage/default/32.sram_ctrl_access_during_key_req.2582551727 |
|
|
Jul 28 06:33:40 PM PDT 24 |
Jul 28 06:36:35 PM PDT 24 |
4672864345 ps |
| T921 |
/workspace/coverage/default/16.sram_ctrl_stress_pipeline.75542999 |
|
|
Jul 28 06:28:57 PM PDT 24 |
Jul 28 06:31:25 PM PDT 24 |
6268713613 ps |
| T922 |
/workspace/coverage/default/48.sram_ctrl_smoke.2715376308 |
|
|
Jul 28 06:38:09 PM PDT 24 |
Jul 28 06:38:19 PM PDT 24 |
617007391 ps |
| T923 |
/workspace/coverage/default/3.sram_ctrl_executable.3261361539 |
|
|
Jul 28 06:25:10 PM PDT 24 |
Jul 28 06:41:59 PM PDT 24 |
12086808295 ps |
| T924 |
/workspace/coverage/default/13.sram_ctrl_mem_partial_access.736563096 |
|
|
Jul 28 06:28:06 PM PDT 24 |
Jul 28 06:28:12 PM PDT 24 |
89493588 ps |
| T925 |
/workspace/coverage/default/33.sram_ctrl_partial_access.320193446 |
|
|
Jul 28 06:33:52 PM PDT 24 |
Jul 28 06:34:03 PM PDT 24 |
1065346638 ps |
| T926 |
/workspace/coverage/default/6.sram_ctrl_smoke.3115189727 |
|
|
Jul 28 06:25:45 PM PDT 24 |
Jul 28 06:25:47 PM PDT 24 |
346086845 ps |
| T927 |
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.819418496 |
|
|
Jul 28 06:25:40 PM PDT 24 |
Jul 28 06:26:28 PM PDT 24 |
2948456397 ps |
| T928 |
/workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.3858137281 |
|
|
Jul 28 06:25:25 PM PDT 24 |
Jul 28 06:33:10 PM PDT 24 |
5395002745 ps |
| T929 |
/workspace/coverage/default/3.sram_ctrl_max_throughput.3682169796 |
|
|
Jul 28 06:25:05 PM PDT 24 |
Jul 28 06:25:11 PM PDT 24 |
55042183 ps |
| T930 |
/workspace/coverage/default/30.sram_ctrl_executable.2473398870 |
|
|
Jul 28 06:33:02 PM PDT 24 |
Jul 28 06:39:10 PM PDT 24 |
1547789520 ps |
| T104 |
/workspace/coverage/default/36.sram_ctrl_mem_partial_access.3204750811 |
|
|
Jul 28 06:35:02 PM PDT 24 |
Jul 28 06:35:08 PM PDT 24 |
355848482 ps |
| T931 |
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.3905498329 |
|
|
Jul 28 06:25:46 PM PDT 24 |
Jul 28 06:28:46 PM PDT 24 |
1896620287 ps |
| T932 |
/workspace/coverage/default/24.sram_ctrl_mem_walk.571782873 |
|
|
Jul 28 06:31:26 PM PDT 24 |
Jul 28 06:31:37 PM PDT 24 |
660752359 ps |
| T933 |
/workspace/coverage/default/42.sram_ctrl_ram_cfg.1382175509 |
|
|
Jul 28 06:36:27 PM PDT 24 |
Jul 28 06:36:28 PM PDT 24 |
109376829 ps |
| T934 |
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.1108191615 |
|
|
Jul 28 06:38:16 PM PDT 24 |
Jul 28 06:40:31 PM PDT 24 |
15487694160 ps |
| T935 |
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.2731413893 |
|
|
Jul 28 06:27:01 PM PDT 24 |
Jul 28 06:27:40 PM PDT 24 |
1231876498 ps |
| T936 |
/workspace/coverage/default/37.sram_ctrl_max_throughput.2041417362 |
|
|
Jul 28 06:35:10 PM PDT 24 |
Jul 28 06:37:14 PM PDT 24 |
882704444 ps |
| T71 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1261905649 |
|
|
Jul 28 05:39:47 PM PDT 24 |
Jul 28 05:39:50 PM PDT 24 |
1581838566 ps |
| T72 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2294372960 |
|
|
Jul 28 05:39:43 PM PDT 24 |
Jul 28 05:39:43 PM PDT 24 |
25055325 ps |
| T937 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1710404424 |
|
|
Jul 28 05:39:51 PM PDT 24 |
Jul 28 05:39:55 PM PDT 24 |
108082090 ps |
| T67 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3689500414 |
|
|
Jul 28 05:39:50 PM PDT 24 |
Jul 28 05:39:53 PM PDT 24 |
177141895 ps |
| T112 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.534080493 |
|
|
Jul 28 05:39:58 PM PDT 24 |
Jul 28 05:39:59 PM PDT 24 |
28608858 ps |
| T938 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2494573252 |
|
|
Jul 28 05:39:47 PM PDT 24 |
Jul 28 05:39:49 PM PDT 24 |
119155828 ps |
| T939 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3276796506 |
|
|
Jul 28 05:39:48 PM PDT 24 |
Jul 28 05:39:53 PM PDT 24 |
540460119 ps |
| T121 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.762365274 |
|
|
Jul 28 05:39:46 PM PDT 24 |
Jul 28 05:39:47 PM PDT 24 |
41978474 ps |
| T68 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1847029717 |
|
|
Jul 28 05:39:50 PM PDT 24 |
Jul 28 05:39:52 PM PDT 24 |
140548141 ps |
| T113 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3674942778 |
|
|
Jul 28 05:39:54 PM PDT 24 |
Jul 28 05:39:58 PM PDT 24 |
664016873 ps |
| T69 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2635470488 |
|
|
Jul 28 05:39:48 PM PDT 24 |
Jul 28 05:39:50 PM PDT 24 |
216830056 ps |
| T114 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1133104204 |
|
|
Jul 28 05:39:48 PM PDT 24 |
Jul 28 05:39:49 PM PDT 24 |
81276623 ps |
| T122 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3181258263 |
|
|
Jul 28 05:39:45 PM PDT 24 |
Jul 28 05:39:45 PM PDT 24 |
43102970 ps |
| T940 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2766951586 |
|
|
Jul 28 05:40:00 PM PDT 24 |
Jul 28 05:40:05 PM PDT 24 |
566228630 ps |
| T941 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3036519260 |
|
|
Jul 28 05:39:58 PM PDT 24 |
Jul 28 05:39:59 PM PDT 24 |
25023080 ps |
| T87 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3083980219 |
|
|
Jul 28 05:40:04 PM PDT 24 |
Jul 28 05:40:07 PM PDT 24 |
788204359 ps |
| T942 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2564053718 |
|
|
Jul 28 05:40:04 PM PDT 24 |
Jul 28 05:40:08 PM PDT 24 |
294843908 ps |
| T88 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2095719015 |
|
|
Jul 28 05:39:56 PM PDT 24 |
Jul 28 05:40:00 PM PDT 24 |
1563737330 ps |
| T943 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.501457723 |
|
|
Jul 28 05:39:46 PM PDT 24 |
Jul 28 05:39:49 PM PDT 24 |
142539294 ps |
| T115 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1895925604 |
|
|
Jul 28 05:39:47 PM PDT 24 |
Jul 28 05:39:48 PM PDT 24 |
22943446 ps |
| T89 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3932561180 |
|
|
Jul 28 05:39:57 PM PDT 24 |
Jul 28 05:39:59 PM PDT 24 |
230749646 ps |
| T90 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3882257391 |
|
|
Jul 28 05:39:49 PM PDT 24 |
Jul 28 05:39:50 PM PDT 24 |
15899655 ps |
| T136 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1098514405 |
|
|
Jul 28 05:39:50 PM PDT 24 |
Jul 28 05:39:53 PM PDT 24 |
1379962835 ps |
| T944 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.341996217 |
|
|
Jul 28 05:39:47 PM PDT 24 |
Jul 28 05:39:48 PM PDT 24 |
16883842 ps |
| T945 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1168688323 |
|
|
Jul 28 05:39:46 PM PDT 24 |
Jul 28 05:39:48 PM PDT 24 |
167701381 ps |
| T946 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1686570024 |
|
|
Jul 28 05:39:51 PM PDT 24 |
Jul 28 05:39:53 PM PDT 24 |
135101202 ps |
| T947 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.803526568 |
|
|
Jul 28 05:39:52 PM PDT 24 |
Jul 28 05:39:56 PM PDT 24 |
75576934 ps |
| T91 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2834054517 |
|
|
Jul 28 05:39:51 PM PDT 24 |
Jul 28 05:39:51 PM PDT 24 |
189866658 ps |
| T948 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1078152624 |
|
|
Jul 28 05:39:49 PM PDT 24 |
Jul 28 05:39:52 PM PDT 24 |
126677887 ps |
| T949 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2805837686 |
|
|
Jul 28 05:39:45 PM PDT 24 |
Jul 28 05:39:47 PM PDT 24 |
140236487 ps |
| T92 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3773829930 |
|
|
Jul 28 05:39:52 PM PDT 24 |
Jul 28 05:39:54 PM PDT 24 |
1776868035 ps |
| T950 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.244423471 |
|
|
Jul 28 05:39:55 PM PDT 24 |
Jul 28 05:39:57 PM PDT 24 |
269855672 ps |
| T951 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3075048269 |
|
|
Jul 28 05:39:44 PM PDT 24 |
Jul 28 05:39:44 PM PDT 24 |
17937565 ps |
| T93 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1339292588 |
|
|
Jul 28 05:39:46 PM PDT 24 |
Jul 28 05:39:47 PM PDT 24 |
85924997 ps |
| T94 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3564387180 |
|
|
Jul 28 05:39:39 PM PDT 24 |
Jul 28 05:39:40 PM PDT 24 |
29136757 ps |
| T137 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2238743913 |
|
|
Jul 28 05:39:51 PM PDT 24 |
Jul 28 05:39:53 PM PDT 24 |
171551975 ps |
| T952 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2033556554 |
|
|
Jul 28 05:39:45 PM PDT 24 |
Jul 28 05:39:50 PM PDT 24 |
590490391 ps |
| T139 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1126727710 |
|
|
Jul 28 05:39:57 PM PDT 24 |
Jul 28 05:39:59 PM PDT 24 |
648800082 ps |
| T953 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.4078390403 |
|
|
Jul 28 05:39:57 PM PDT 24 |
Jul 28 05:39:58 PM PDT 24 |
29571425 ps |
| T96 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.4221786520 |
|
|
Jul 28 05:39:46 PM PDT 24 |
Jul 28 05:39:48 PM PDT 24 |
248652550 ps |
| T954 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.68344594 |
|
|
Jul 28 05:39:53 PM PDT 24 |
Jul 28 05:39:54 PM PDT 24 |
122314157 ps |
| T140 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1279864870 |
|
|
Jul 28 05:40:02 PM PDT 24 |
Jul 28 05:40:03 PM PDT 24 |
475393529 ps |
| T955 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3255841108 |
|
|
Jul 28 05:39:47 PM PDT 24 |
Jul 28 05:39:48 PM PDT 24 |
13838927 ps |
| T956 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3467310365 |
|
|
Jul 28 05:39:45 PM PDT 24 |
Jul 28 05:39:47 PM PDT 24 |
815966048 ps |
| T957 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1405776223 |
|
|
Jul 28 05:39:42 PM PDT 24 |
Jul 28 05:39:43 PM PDT 24 |
50491619 ps |
| T958 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3419407789 |
|
|
Jul 28 05:39:43 PM PDT 24 |
Jul 28 05:39:45 PM PDT 24 |
113335874 ps |
| T959 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.4096164896 |
|
|
Jul 28 05:39:50 PM PDT 24 |
Jul 28 05:39:52 PM PDT 24 |
32165191 ps |
| T141 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3955056554 |
|
|
Jul 28 05:39:48 PM PDT 24 |
Jul 28 05:39:50 PM PDT 24 |
185810590 ps |
| T97 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1228687390 |
|
|
Jul 28 05:39:46 PM PDT 24 |
Jul 28 05:39:48 PM PDT 24 |
215009446 ps |
| T98 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1127135065 |
|
|
Jul 28 05:39:57 PM PDT 24 |
Jul 28 05:40:00 PM PDT 24 |
1505236184 ps |
| T960 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3419644180 |
|
|
Jul 28 05:39:47 PM PDT 24 |
Jul 28 05:39:49 PM PDT 24 |
123816974 ps |
| T961 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1372221759 |
|
|
Jul 28 05:39:53 PM PDT 24 |
Jul 28 05:39:56 PM PDT 24 |
678155245 ps |
| T962 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.443773070 |
|
|
Jul 28 05:39:46 PM PDT 24 |
Jul 28 05:39:47 PM PDT 24 |
66857702 ps |
| T963 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.160345548 |
|
|
Jul 28 05:39:47 PM PDT 24 |
Jul 28 05:39:48 PM PDT 24 |
24116600 ps |
| T964 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3947206468 |
|
|
Jul 28 05:39:43 PM PDT 24 |
Jul 28 05:39:46 PM PDT 24 |
3006716028 ps |
| T965 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1794218879 |
|
|
Jul 28 05:39:37 PM PDT 24 |
Jul 28 05:39:39 PM PDT 24 |
308740331 ps |
| T966 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.375260579 |
|
|
Jul 28 05:39:46 PM PDT 24 |
Jul 28 05:39:47 PM PDT 24 |
108240392 ps |
| T967 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1504248177 |
|
|
Jul 28 05:39:46 PM PDT 24 |
Jul 28 05:39:47 PM PDT 24 |
53260372 ps |
| T99 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3664913256 |
|
|
Jul 28 05:39:41 PM PDT 24 |
Jul 28 05:39:42 PM PDT 24 |
43164701 ps |
| T968 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3774699085 |
|
|
Jul 28 05:39:52 PM PDT 24 |
Jul 28 05:39:53 PM PDT 24 |
33258033 ps |
| T969 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2702021571 |
|
|
Jul 28 05:39:48 PM PDT 24 |
Jul 28 05:39:49 PM PDT 24 |
15042049 ps |
| T970 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3907869116 |
|
|
Jul 28 05:40:08 PM PDT 24 |
Jul 28 05:40:10 PM PDT 24 |
266848881 ps |
| T971 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.648899166 |
|
|
Jul 28 05:39:54 PM PDT 24 |
Jul 28 05:39:55 PM PDT 24 |
44565557 ps |
| T138 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.774895625 |
|
|
Jul 28 05:39:50 PM PDT 24 |
Jul 28 05:39:53 PM PDT 24 |
253116390 ps |
| T972 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1715175551 |
|
|
Jul 28 05:39:47 PM PDT 24 |
Jul 28 05:39:48 PM PDT 24 |
18199053 ps |
| T142 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2333685181 |
|
|
Jul 28 05:39:43 PM PDT 24 |
Jul 28 05:39:45 PM PDT 24 |
107200982 ps |
| T973 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.715792459 |
|
|
Jul 28 05:39:49 PM PDT 24 |
Jul 28 05:39:53 PM PDT 24 |
569508282 ps |
| T974 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1418865672 |
|
|
Jul 28 05:39:50 PM PDT 24 |
Jul 28 05:39:52 PM PDT 24 |
785925673 ps |
| T975 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3214676888 |
|
|
Jul 28 05:39:42 PM PDT 24 |
Jul 28 05:39:43 PM PDT 24 |
50548859 ps |
| T976 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3470570 |
|
|
Jul 28 05:39:55 PM PDT 24 |
Jul 28 05:40:00 PM PDT 24 |
326162134 ps |
| T977 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.903000352 |
|
|
Jul 28 05:40:01 PM PDT 24 |
Jul 28 05:40:04 PM PDT 24 |
43312446 ps |
| T978 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2734015812 |
|
|
Jul 28 05:40:00 PM PDT 24 |
Jul 28 05:40:01 PM PDT 24 |
16304222 ps |
| T979 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3624653652 |
|
|
Jul 28 05:39:47 PM PDT 24 |
Jul 28 05:39:49 PM PDT 24 |
93017294 ps |
| T980 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3618651019 |
|
|
Jul 28 05:39:54 PM PDT 24 |
Jul 28 05:39:55 PM PDT 24 |
13396065 ps |
| T981 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.867705764 |
|
|
Jul 28 05:39:44 PM PDT 24 |
Jul 28 05:39:46 PM PDT 24 |
272722811 ps |
| T982 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2356963740 |
|
|
Jul 28 05:39:47 PM PDT 24 |
Jul 28 05:39:49 PM PDT 24 |
367213958 ps |
| T105 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2150030704 |
|
|
Jul 28 05:39:45 PM PDT 24 |
Jul 28 05:39:46 PM PDT 24 |
34585074 ps |
| T983 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1357337961 |
|
|
Jul 28 05:39:51 PM PDT 24 |
Jul 28 05:39:53 PM PDT 24 |
2001191333 ps |
| T106 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3104673492 |
|
|
Jul 28 05:39:52 PM PDT 24 |
Jul 28 05:39:54 PM PDT 24 |
875473354 ps |
| T984 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2633349390 |
|
|
Jul 28 05:40:03 PM PDT 24 |
Jul 28 05:40:05 PM PDT 24 |
29654459 ps |
| T985 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3607662824 |
|
|
Jul 28 05:39:52 PM PDT 24 |
Jul 28 05:39:54 PM PDT 24 |
94822942 ps |
| T986 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.46871157 |
|
|
Jul 28 05:39:56 PM PDT 24 |
Jul 28 05:39:57 PM PDT 24 |
100761825 ps |
| T987 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.599861549 |
|
|
Jul 28 05:39:49 PM PDT 24 |
Jul 28 05:39:51 PM PDT 24 |
25492861 ps |
| T988 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1948710746 |
|
|
Jul 28 05:39:49 PM PDT 24 |
Jul 28 05:39:51 PM PDT 24 |
322265371 ps |
| T108 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3640289612 |
|
|
Jul 28 05:39:51 PM PDT 24 |
Jul 28 05:39:53 PM PDT 24 |
741976719 ps |
| T989 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1102755148 |
|
|
Jul 28 05:39:44 PM PDT 24 |
Jul 28 05:39:45 PM PDT 24 |
313186780 ps |
| T107 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3084910379 |
|
|
Jul 28 05:39:48 PM PDT 24 |
Jul 28 05:39:52 PM PDT 24 |
807051701 ps |
| T990 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3863451726 |
|
|
Jul 28 05:40:05 PM PDT 24 |
Jul 28 05:40:05 PM PDT 24 |
21785776 ps |
| T991 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.4106617733 |
|
|
Jul 28 05:39:41 PM PDT 24 |
Jul 28 05:39:42 PM PDT 24 |
19493048 ps |
| T992 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1012714748 |
|
|
Jul 28 05:40:00 PM PDT 24 |
Jul 28 05:40:01 PM PDT 24 |
164394019 ps |
| T993 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3869843263 |
|
|
Jul 28 05:39:52 PM PDT 24 |
Jul 28 05:39:53 PM PDT 24 |
33927729 ps |
| T994 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2207801716 |
|
|
Jul 28 05:39:43 PM PDT 24 |
Jul 28 05:39:44 PM PDT 24 |
40800075 ps |
| T995 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2840546130 |
|
|
Jul 28 05:39:53 PM PDT 24 |
Jul 28 05:39:55 PM PDT 24 |
159228960 ps |
| T109 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1195903454 |
|
|
Jul 28 05:39:49 PM PDT 24 |
Jul 28 05:39:53 PM PDT 24 |
1562556953 ps |
| T996 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3646458059 |
|
|
Jul 28 05:40:04 PM PDT 24 |
Jul 28 05:40:05 PM PDT 24 |
85133527 ps |
| T110 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.836910264 |
|
|
Jul 28 05:39:51 PM PDT 24 |
Jul 28 05:39:53 PM PDT 24 |
836055322 ps |
| T997 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2021000809 |
|
|
Jul 28 05:39:57 PM PDT 24 |
Jul 28 05:39:58 PM PDT 24 |
43720778 ps |
| T998 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2966426951 |
|
|
Jul 28 05:39:43 PM PDT 24 |
Jul 28 05:39:43 PM PDT 24 |
39913356 ps |
| T999 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2847293224 |
|
|
Jul 28 05:39:46 PM PDT 24 |
Jul 28 05:39:47 PM PDT 24 |
101513627 ps |
| T1000 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3424090587 |
|
|
Jul 28 05:39:43 PM PDT 24 |
Jul 28 05:39:46 PM PDT 24 |
56581907 ps |
| T1001 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3453601435 |
|
|
Jul 28 05:39:44 PM PDT 24 |
Jul 28 05:39:45 PM PDT 24 |
61553113 ps |
| T1002 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3624532837 |
|
|
Jul 28 05:39:42 PM PDT 24 |
Jul 28 05:39:45 PM PDT 24 |
2503175260 ps |
| T1003 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1419529298 |
|
|
Jul 28 05:39:51 PM PDT 24 |
Jul 28 05:39:52 PM PDT 24 |
18505369 ps |