| T800 |
/workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.3443291225 |
|
|
Jul 29 07:37:35 PM PDT 24 |
Jul 29 07:38:21 PM PDT 24 |
471386035 ps |
| T801 |
/workspace/coverage/default/11.sram_ctrl_executable.1577403515 |
|
|
Jul 29 07:36:57 PM PDT 24 |
Jul 29 07:40:28 PM PDT 24 |
3005526287 ps |
| T802 |
/workspace/coverage/default/11.sram_ctrl_bijection.2141512251 |
|
|
Jul 29 07:37:05 PM PDT 24 |
Jul 29 07:37:41 PM PDT 24 |
580360270 ps |
| T803 |
/workspace/coverage/default/26.sram_ctrl_mem_walk.4246406952 |
|
|
Jul 29 07:37:51 PM PDT 24 |
Jul 29 07:38:04 PM PDT 24 |
8876658368 ps |
| T804 |
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.396902519 |
|
|
Jul 29 07:39:47 PM PDT 24 |
Jul 29 08:01:17 PM PDT 24 |
5995268164 ps |
| T805 |
/workspace/coverage/default/29.sram_ctrl_alert_test.3880662366 |
|
|
Jul 29 07:38:12 PM PDT 24 |
Jul 29 07:38:13 PM PDT 24 |
13414503 ps |
| T806 |
/workspace/coverage/default/13.sram_ctrl_bijection.2991706101 |
|
|
Jul 29 07:37:05 PM PDT 24 |
Jul 29 07:38:44 PM PDT 24 |
75816592739 ps |
| T807 |
/workspace/coverage/default/49.sram_ctrl_stress_all.3290643627 |
|
|
Jul 29 07:39:59 PM PDT 24 |
Jul 29 08:00:16 PM PDT 24 |
156192405212 ps |
| T808 |
/workspace/coverage/default/17.sram_ctrl_executable.590701361 |
|
|
Jul 29 07:37:27 PM PDT 24 |
Jul 29 07:44:41 PM PDT 24 |
7474644498 ps |
| T809 |
/workspace/coverage/default/12.sram_ctrl_regwen.3182830797 |
|
|
Jul 29 07:37:07 PM PDT 24 |
Jul 29 07:46:45 PM PDT 24 |
39467400053 ps |
| T810 |
/workspace/coverage/default/42.sram_ctrl_smoke.3315265798 |
|
|
Jul 29 07:39:06 PM PDT 24 |
Jul 29 07:39:18 PM PDT 24 |
725396806 ps |
| T811 |
/workspace/coverage/default/4.sram_ctrl_executable.2562335983 |
|
|
Jul 29 07:36:49 PM PDT 24 |
Jul 29 07:41:22 PM PDT 24 |
3092536720 ps |
| T812 |
/workspace/coverage/default/9.sram_ctrl_regwen.2124238467 |
|
|
Jul 29 07:37:07 PM PDT 24 |
Jul 29 07:38:03 PM PDT 24 |
719856270 ps |
| T813 |
/workspace/coverage/default/4.sram_ctrl_bijection.3146932473 |
|
|
Jul 29 07:37:01 PM PDT 24 |
Jul 29 07:38:15 PM PDT 24 |
3471964239 ps |
| T814 |
/workspace/coverage/default/13.sram_ctrl_multiple_keys.240484159 |
|
|
Jul 29 07:37:15 PM PDT 24 |
Jul 29 07:47:07 PM PDT 24 |
4485294711 ps |
| T815 |
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.925626387 |
|
|
Jul 29 07:39:38 PM PDT 24 |
Jul 29 07:42:27 PM PDT 24 |
6504992711 ps |
| T816 |
/workspace/coverage/default/27.sram_ctrl_multiple_keys.1316237748 |
|
|
Jul 29 07:37:54 PM PDT 24 |
Jul 29 08:01:56 PM PDT 24 |
26313264694 ps |
| T817 |
/workspace/coverage/default/14.sram_ctrl_partial_access.3011120115 |
|
|
Jul 29 07:37:25 PM PDT 24 |
Jul 29 07:37:43 PM PDT 24 |
2138627872 ps |
| T818 |
/workspace/coverage/default/41.sram_ctrl_bijection.1275312134 |
|
|
Jul 29 07:39:05 PM PDT 24 |
Jul 29 07:39:50 PM PDT 24 |
822426571 ps |
| T819 |
/workspace/coverage/default/0.sram_ctrl_bijection.1546583235 |
|
|
Jul 29 07:36:51 PM PDT 24 |
Jul 29 07:37:12 PM PDT 24 |
3673467872 ps |
| T820 |
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.526117919 |
|
|
Jul 29 07:39:38 PM PDT 24 |
Jul 29 07:39:52 PM PDT 24 |
1507368443 ps |
| T821 |
/workspace/coverage/default/37.sram_ctrl_max_throughput.698594889 |
|
|
Jul 29 07:38:40 PM PDT 24 |
Jul 29 07:39:38 PM PDT 24 |
203684003 ps |
| T822 |
/workspace/coverage/default/4.sram_ctrl_smoke.396698593 |
|
|
Jul 29 07:36:54 PM PDT 24 |
Jul 29 07:37:06 PM PDT 24 |
189869176 ps |
| T823 |
/workspace/coverage/default/34.sram_ctrl_partial_access.1608332191 |
|
|
Jul 29 07:38:29 PM PDT 24 |
Jul 29 07:38:34 PM PDT 24 |
1041926153 ps |
| T824 |
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.310258550 |
|
|
Jul 29 07:37:07 PM PDT 24 |
Jul 29 07:43:57 PM PDT 24 |
61442085125 ps |
| T825 |
/workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.608536857 |
|
|
Jul 29 07:38:20 PM PDT 24 |
Jul 29 07:38:45 PM PDT 24 |
954615296 ps |
| T826 |
/workspace/coverage/default/35.sram_ctrl_alert_test.290541383 |
|
|
Jul 29 07:38:38 PM PDT 24 |
Jul 29 07:38:39 PM PDT 24 |
14318059 ps |
| T827 |
/workspace/coverage/default/28.sram_ctrl_partial_access_b2b.3479139230 |
|
|
Jul 29 07:37:59 PM PDT 24 |
Jul 29 07:43:48 PM PDT 24 |
53742901174 ps |
| T828 |
/workspace/coverage/default/39.sram_ctrl_partial_access.2380286852 |
|
|
Jul 29 07:38:50 PM PDT 24 |
Jul 29 07:38:58 PM PDT 24 |
752941434 ps |
| T829 |
/workspace/coverage/default/15.sram_ctrl_executable.624157848 |
|
|
Jul 29 07:37:17 PM PDT 24 |
Jul 29 07:51:05 PM PDT 24 |
8007035300 ps |
| T830 |
/workspace/coverage/default/5.sram_ctrl_multiple_keys.1079272378 |
|
|
Jul 29 07:37:05 PM PDT 24 |
Jul 29 07:53:43 PM PDT 24 |
2653758140 ps |
| T831 |
/workspace/coverage/default/24.sram_ctrl_multiple_keys.74252005 |
|
|
Jul 29 07:37:42 PM PDT 24 |
Jul 29 07:51:47 PM PDT 24 |
11453948830 ps |
| T832 |
/workspace/coverage/default/27.sram_ctrl_mem_walk.3171993464 |
|
|
Jul 29 07:37:52 PM PDT 24 |
Jul 29 07:38:01 PM PDT 24 |
517348349 ps |
| T25 |
/workspace/coverage/default/0.sram_ctrl_sec_cm.2519501248 |
|
|
Jul 29 07:36:46 PM PDT 24 |
Jul 29 07:36:49 PM PDT 24 |
370463857 ps |
| T833 |
/workspace/coverage/default/15.sram_ctrl_ram_cfg.3830612254 |
|
|
Jul 29 07:37:35 PM PDT 24 |
Jul 29 07:37:36 PM PDT 24 |
47522746 ps |
| T834 |
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2289827911 |
|
|
Jul 29 07:36:48 PM PDT 24 |
Jul 29 07:43:53 PM PDT 24 |
16208360314 ps |
| T835 |
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.907492244 |
|
|
Jul 29 07:39:40 PM PDT 24 |
Jul 29 07:49:50 PM PDT 24 |
7182376640 ps |
| T836 |
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.2386634817 |
|
|
Jul 29 07:36:51 PM PDT 24 |
Jul 29 07:51:52 PM PDT 24 |
11011267225 ps |
| T837 |
/workspace/coverage/default/1.sram_ctrl_alert_test.3341718965 |
|
|
Jul 29 07:36:59 PM PDT 24 |
Jul 29 07:37:00 PM PDT 24 |
12834671 ps |
| T838 |
/workspace/coverage/default/10.sram_ctrl_bijection.1574817043 |
|
|
Jul 29 07:37:05 PM PDT 24 |
Jul 29 07:37:28 PM PDT 24 |
3796121758 ps |
| T839 |
/workspace/coverage/default/15.sram_ctrl_access_during_key_req.3339354521 |
|
|
Jul 29 07:37:23 PM PDT 24 |
Jul 29 07:42:56 PM PDT 24 |
30985214226 ps |
| T840 |
/workspace/coverage/default/28.sram_ctrl_regwen.633039137 |
|
|
Jul 29 07:37:53 PM PDT 24 |
Jul 29 07:49:09 PM PDT 24 |
62606776691 ps |
| T841 |
/workspace/coverage/default/39.sram_ctrl_stress_pipeline.438870482 |
|
|
Jul 29 07:38:50 PM PDT 24 |
Jul 29 07:43:49 PM PDT 24 |
10521249202 ps |
| T842 |
/workspace/coverage/default/14.sram_ctrl_lc_escalation.2925693158 |
|
|
Jul 29 07:37:17 PM PDT 24 |
Jul 29 07:37:24 PM PDT 24 |
583925304 ps |
| T843 |
/workspace/coverage/default/0.sram_ctrl_smoke.3704613138 |
|
|
Jul 29 07:36:41 PM PDT 24 |
Jul 29 07:36:49 PM PDT 24 |
586073639 ps |
| T844 |
/workspace/coverage/default/37.sram_ctrl_mem_partial_access.3885932100 |
|
|
Jul 29 07:38:45 PM PDT 24 |
Jul 29 07:38:49 PM PDT 24 |
67331987 ps |
| T845 |
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.432666713 |
|
|
Jul 29 07:39:14 PM PDT 24 |
Jul 29 07:40:26 PM PDT 24 |
126978867 ps |
| T846 |
/workspace/coverage/default/45.sram_ctrl_multiple_keys.4176972675 |
|
|
Jul 29 07:39:39 PM PDT 24 |
Jul 29 08:05:06 PM PDT 24 |
53566007608 ps |
| T847 |
/workspace/coverage/default/47.sram_ctrl_lc_escalation.3836476349 |
|
|
Jul 29 07:39:47 PM PDT 24 |
Jul 29 07:39:53 PM PDT 24 |
656922551 ps |
| T848 |
/workspace/coverage/default/32.sram_ctrl_smoke.587055519 |
|
|
Jul 29 07:38:20 PM PDT 24 |
Jul 29 07:38:38 PM PDT 24 |
1100943710 ps |
| T849 |
/workspace/coverage/default/12.sram_ctrl_stress_all.1468228654 |
|
|
Jul 29 07:37:16 PM PDT 24 |
Jul 29 08:21:09 PM PDT 24 |
14796287046 ps |
| T850 |
/workspace/coverage/default/30.sram_ctrl_alert_test.721032353 |
|
|
Jul 29 07:38:23 PM PDT 24 |
Jul 29 07:38:24 PM PDT 24 |
57771652 ps |
| T851 |
/workspace/coverage/default/23.sram_ctrl_ram_cfg.3621166348 |
|
|
Jul 29 07:37:43 PM PDT 24 |
Jul 29 07:37:44 PM PDT 24 |
63038340 ps |
| T852 |
/workspace/coverage/default/15.sram_ctrl_mem_walk.1021617959 |
|
|
Jul 29 07:37:25 PM PDT 24 |
Jul 29 07:37:36 PM PDT 24 |
741830277 ps |
| T853 |
/workspace/coverage/default/30.sram_ctrl_lc_escalation.1568282351 |
|
|
Jul 29 07:38:13 PM PDT 24 |
Jul 29 07:38:17 PM PDT 24 |
302179122 ps |
| T854 |
/workspace/coverage/default/20.sram_ctrl_lc_escalation.3273991123 |
|
|
Jul 29 07:37:40 PM PDT 24 |
Jul 29 07:37:46 PM PDT 24 |
691585983 ps |
| T116 |
/workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.4040611191 |
|
|
Jul 29 07:37:57 PM PDT 24 |
Jul 29 07:38:07 PM PDT 24 |
308739680 ps |
| T855 |
/workspace/coverage/default/1.sram_ctrl_bijection.131122148 |
|
|
Jul 29 07:36:44 PM PDT 24 |
Jul 29 07:37:16 PM PDT 24 |
509284422 ps |
| T856 |
/workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.604044985 |
|
|
Jul 29 07:37:47 PM PDT 24 |
Jul 29 07:38:26 PM PDT 24 |
104785011 ps |
| T857 |
/workspace/coverage/default/33.sram_ctrl_multiple_keys.1881363662 |
|
|
Jul 29 07:38:23 PM PDT 24 |
Jul 29 08:00:22 PM PDT 24 |
108679969267 ps |
| T858 |
/workspace/coverage/default/2.sram_ctrl_executable.307413472 |
|
|
Jul 29 07:37:02 PM PDT 24 |
Jul 29 07:50:19 PM PDT 24 |
4536326650 ps |
| T859 |
/workspace/coverage/default/38.sram_ctrl_bijection.4176716730 |
|
|
Jul 29 07:38:43 PM PDT 24 |
Jul 29 07:39:37 PM PDT 24 |
3830027665 ps |
| T860 |
/workspace/coverage/default/16.sram_ctrl_smoke.2812495854 |
|
|
Jul 29 07:37:12 PM PDT 24 |
Jul 29 07:37:20 PM PDT 24 |
244267209 ps |
| T861 |
/workspace/coverage/default/27.sram_ctrl_mem_partial_access.2710552083 |
|
|
Jul 29 07:37:58 PM PDT 24 |
Jul 29 07:38:00 PM PDT 24 |
82130853 ps |
| T862 |
/workspace/coverage/default/37.sram_ctrl_multiple_keys.963096497 |
|
|
Jul 29 07:38:37 PM PDT 24 |
Jul 29 07:49:44 PM PDT 24 |
35257001147 ps |
| T863 |
/workspace/coverage/default/6.sram_ctrl_ram_cfg.2597404894 |
|
|
Jul 29 07:36:55 PM PDT 24 |
Jul 29 07:36:56 PM PDT 24 |
48709898 ps |
| T864 |
/workspace/coverage/default/12.sram_ctrl_max_throughput.1412247009 |
|
|
Jul 29 07:37:12 PM PDT 24 |
Jul 29 07:39:23 PM PDT 24 |
188400084 ps |
| T865 |
/workspace/coverage/default/10.sram_ctrl_stress_all.1027816277 |
|
|
Jul 29 07:37:24 PM PDT 24 |
Jul 29 08:09:15 PM PDT 24 |
120823680924 ps |
| T866 |
/workspace/coverage/default/9.sram_ctrl_multiple_keys.1715333222 |
|
|
Jul 29 07:37:05 PM PDT 24 |
Jul 29 07:49:06 PM PDT 24 |
7322514309 ps |
| T867 |
/workspace/coverage/default/21.sram_ctrl_bijection.828009363 |
|
|
Jul 29 07:37:38 PM PDT 24 |
Jul 29 07:38:48 PM PDT 24 |
4567044778 ps |
| T868 |
/workspace/coverage/default/9.sram_ctrl_partial_access.2955625469 |
|
|
Jul 29 07:37:18 PM PDT 24 |
Jul 29 07:38:56 PM PDT 24 |
196839059 ps |
| T869 |
/workspace/coverage/default/22.sram_ctrl_regwen.3354679240 |
|
|
Jul 29 07:37:43 PM PDT 24 |
Jul 29 07:53:54 PM PDT 24 |
47688617109 ps |
| T870 |
/workspace/coverage/default/13.sram_ctrl_mem_walk.2240585407 |
|
|
Jul 29 07:37:05 PM PDT 24 |
Jul 29 07:37:12 PM PDT 24 |
235400426 ps |
| T871 |
/workspace/coverage/default/19.sram_ctrl_stress_all.2105118255 |
|
|
Jul 29 07:37:37 PM PDT 24 |
Jul 29 08:31:28 PM PDT 24 |
151336406934 ps |
| T872 |
/workspace/coverage/default/43.sram_ctrl_mem_walk.342069482 |
|
|
Jul 29 07:39:26 PM PDT 24 |
Jul 29 07:39:35 PM PDT 24 |
539366795 ps |
| T873 |
/workspace/coverage/default/1.sram_ctrl_multiple_keys.549119594 |
|
|
Jul 29 07:36:46 PM PDT 24 |
Jul 29 07:51:54 PM PDT 24 |
9544078042 ps |
| T874 |
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.4277014810 |
|
|
Jul 29 07:39:27 PM PDT 24 |
Jul 29 07:43:36 PM PDT 24 |
2591885953 ps |
| T875 |
/workspace/coverage/default/5.sram_ctrl_regwen.3876576895 |
|
|
Jul 29 07:36:59 PM PDT 24 |
Jul 29 07:47:46 PM PDT 24 |
11028688426 ps |
| T876 |
/workspace/coverage/default/35.sram_ctrl_stress_all.280246304 |
|
|
Jul 29 07:38:40 PM PDT 24 |
Jul 29 07:48:23 PM PDT 24 |
15228551926 ps |
| T877 |
/workspace/coverage/default/47.sram_ctrl_ram_cfg.1918928807 |
|
|
Jul 29 07:39:48 PM PDT 24 |
Jul 29 07:39:49 PM PDT 24 |
84817819 ps |
| T878 |
/workspace/coverage/default/12.sram_ctrl_mem_walk.3849743902 |
|
|
Jul 29 07:37:03 PM PDT 24 |
Jul 29 07:37:14 PM PDT 24 |
1831807201 ps |
| T879 |
/workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.3462814492 |
|
|
Jul 29 07:38:36 PM PDT 24 |
Jul 29 07:39:00 PM PDT 24 |
176041962 ps |
| T880 |
/workspace/coverage/default/46.sram_ctrl_alert_test.3978968353 |
|
|
Jul 29 07:39:35 PM PDT 24 |
Jul 29 07:39:36 PM PDT 24 |
23246291 ps |
| T881 |
/workspace/coverage/default/28.sram_ctrl_access_during_key_req.3455592635 |
|
|
Jul 29 07:37:52 PM PDT 24 |
Jul 29 07:51:01 PM PDT 24 |
3242563847 ps |
| T882 |
/workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.1182354981 |
|
|
Jul 29 07:37:36 PM PDT 24 |
Jul 29 07:39:52 PM PDT 24 |
1028908202 ps |
| T883 |
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.4217413014 |
|
|
Jul 29 07:39:15 PM PDT 24 |
Jul 29 07:46:32 PM PDT 24 |
86237164078 ps |
| T94 |
/workspace/coverage/default/4.sram_ctrl_mem_partial_access.394381087 |
|
|
Jul 29 07:36:57 PM PDT 24 |
Jul 29 07:37:01 PM PDT 24 |
869249627 ps |
| T884 |
/workspace/coverage/default/21.sram_ctrl_lc_escalation.4011825132 |
|
|
Jul 29 07:37:47 PM PDT 24 |
Jul 29 07:37:50 PM PDT 24 |
143559891 ps |
| T885 |
/workspace/coverage/default/37.sram_ctrl_ram_cfg.4095369804 |
|
|
Jul 29 07:38:42 PM PDT 24 |
Jul 29 07:38:43 PM PDT 24 |
99957611 ps |
| T886 |
/workspace/coverage/default/9.sram_ctrl_max_throughput.1053607855 |
|
|
Jul 29 07:37:23 PM PDT 24 |
Jul 29 07:37:41 PM PDT 24 |
83597543 ps |
| T887 |
/workspace/coverage/default/37.sram_ctrl_stress_pipeline.1181649876 |
|
|
Jul 29 07:38:41 PM PDT 24 |
Jul 29 07:40:43 PM PDT 24 |
5254656642 ps |
| T888 |
/workspace/coverage/default/36.sram_ctrl_alert_test.1210248227 |
|
|
Jul 29 07:38:38 PM PDT 24 |
Jul 29 07:38:39 PM PDT 24 |
31634383 ps |
| T889 |
/workspace/coverage/default/42.sram_ctrl_alert_test.2847868262 |
|
|
Jul 29 07:39:15 PM PDT 24 |
Jul 29 07:39:16 PM PDT 24 |
18837091 ps |
| T890 |
/workspace/coverage/default/5.sram_ctrl_ram_cfg.4136514336 |
|
|
Jul 29 07:36:59 PM PDT 24 |
Jul 29 07:37:00 PM PDT 24 |
88196003 ps |
| T891 |
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.2613742448 |
|
|
Jul 29 07:39:25 PM PDT 24 |
Jul 29 07:47:21 PM PDT 24 |
35227577434 ps |
| T892 |
/workspace/coverage/default/21.sram_ctrl_alert_test.3936888280 |
|
|
Jul 29 07:37:37 PM PDT 24 |
Jul 29 07:37:38 PM PDT 24 |
14916497 ps |
| T893 |
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.883251381 |
|
|
Jul 29 07:36:59 PM PDT 24 |
Jul 29 07:37:01 PM PDT 24 |
40106217 ps |
| T894 |
/workspace/coverage/default/1.sram_ctrl_ram_cfg.1311649922 |
|
|
Jul 29 07:36:59 PM PDT 24 |
Jul 29 07:37:01 PM PDT 24 |
28842085 ps |
| T895 |
/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.1807753028 |
|
|
Jul 29 07:37:39 PM PDT 24 |
Jul 29 07:41:30 PM PDT 24 |
20397057349 ps |
| T896 |
/workspace/coverage/default/38.sram_ctrl_executable.2922566768 |
|
|
Jul 29 07:38:40 PM PDT 24 |
Jul 29 07:44:45 PM PDT 24 |
45141251753 ps |
| T897 |
/workspace/coverage/default/30.sram_ctrl_stress_pipeline.4058765845 |
|
|
Jul 29 07:38:14 PM PDT 24 |
Jul 29 07:42:07 PM PDT 24 |
9495483190 ps |
| T898 |
/workspace/coverage/default/35.sram_ctrl_multiple_keys.3834058409 |
|
|
Jul 29 07:38:29 PM PDT 24 |
Jul 29 07:57:31 PM PDT 24 |
57918164931 ps |
| T899 |
/workspace/coverage/default/39.sram_ctrl_max_throughput.249257418 |
|
|
Jul 29 07:38:50 PM PDT 24 |
Jul 29 07:40:58 PM PDT 24 |
135622405 ps |
| T900 |
/workspace/coverage/default/15.sram_ctrl_partial_access.536028659 |
|
|
Jul 29 07:37:14 PM PDT 24 |
Jul 29 07:39:37 PM PDT 24 |
251036377 ps |
| T901 |
/workspace/coverage/default/14.sram_ctrl_mem_partial_access.3106306838 |
|
|
Jul 29 07:37:23 PM PDT 24 |
Jul 29 07:37:27 PM PDT 24 |
392627128 ps |
| T902 |
/workspace/coverage/default/42.sram_ctrl_regwen.1006837708 |
|
|
Jul 29 07:39:16 PM PDT 24 |
Jul 29 07:45:05 PM PDT 24 |
11914322865 ps |
| T903 |
/workspace/coverage/default/35.sram_ctrl_partial_access.2329544240 |
|
|
Jul 29 07:38:35 PM PDT 24 |
Jul 29 07:38:41 PM PDT 24 |
327424115 ps |
| T904 |
/workspace/coverage/default/4.sram_ctrl_multiple_keys.4179613375 |
|
|
Jul 29 07:36:52 PM PDT 24 |
Jul 29 07:41:13 PM PDT 24 |
7866374937 ps |
| T905 |
/workspace/coverage/default/1.sram_ctrl_mem_walk.2277558467 |
|
|
Jul 29 07:36:59 PM PDT 24 |
Jul 29 07:37:04 PM PDT 24 |
382840489 ps |
| T906 |
/workspace/coverage/default/17.sram_ctrl_stress_all.427458246 |
|
|
Jul 29 07:37:25 PM PDT 24 |
Jul 29 08:14:24 PM PDT 24 |
118619455949 ps |
| T907 |
/workspace/coverage/default/14.sram_ctrl_smoke.2317290730 |
|
|
Jul 29 07:37:09 PM PDT 24 |
Jul 29 07:37:14 PM PDT 24 |
339794154 ps |
| T908 |
/workspace/coverage/default/48.sram_ctrl_smoke.3376692930 |
|
|
Jul 29 07:39:52 PM PDT 24 |
Jul 29 07:40:05 PM PDT 24 |
2368982952 ps |
| T909 |
/workspace/coverage/default/7.sram_ctrl_alert_test.707218662 |
|
|
Jul 29 07:37:10 PM PDT 24 |
Jul 29 07:37:11 PM PDT 24 |
13867829 ps |
| T910 |
/workspace/coverage/default/24.sram_ctrl_partial_access.3638619308 |
|
|
Jul 29 07:37:43 PM PDT 24 |
Jul 29 07:38:01 PM PDT 24 |
3807835139 ps |
| T911 |
/workspace/coverage/default/16.sram_ctrl_partial_access_b2b.3863070782 |
|
|
Jul 29 07:37:22 PM PDT 24 |
Jul 29 07:40:38 PM PDT 24 |
2694112441 ps |
| T912 |
/workspace/coverage/default/47.sram_ctrl_executable.991870274 |
|
|
Jul 29 07:39:48 PM PDT 24 |
Jul 29 07:44:13 PM PDT 24 |
33213274644 ps |
| T913 |
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.2873547940 |
|
|
Jul 29 07:37:11 PM PDT 24 |
Jul 29 08:01:13 PM PDT 24 |
2985748307 ps |
| T914 |
/workspace/coverage/default/34.sram_ctrl_mem_walk.2015871137 |
|
|
Jul 29 07:38:35 PM PDT 24 |
Jul 29 07:38:47 PM PDT 24 |
4666246462 ps |
| T915 |
/workspace/coverage/default/24.sram_ctrl_access_during_key_req.1899909872 |
|
|
Jul 29 07:37:39 PM PDT 24 |
Jul 29 07:40:50 PM PDT 24 |
3549099327 ps |
| T916 |
/workspace/coverage/default/38.sram_ctrl_access_during_key_req.4263256483 |
|
|
Jul 29 07:38:39 PM PDT 24 |
Jul 29 07:55:32 PM PDT 24 |
7183180557 ps |
| T917 |
/workspace/coverage/default/30.sram_ctrl_ram_cfg.636146415 |
|
|
Jul 29 07:38:20 PM PDT 24 |
Jul 29 07:38:22 PM PDT 24 |
77882694 ps |
| T918 |
/workspace/coverage/default/17.sram_ctrl_bijection.1383359102 |
|
|
Jul 29 07:37:29 PM PDT 24 |
Jul 29 07:37:46 PM PDT 24 |
2823090469 ps |
| T919 |
/workspace/coverage/default/38.sram_ctrl_mem_partial_access.552188335 |
|
|
Jul 29 07:38:53 PM PDT 24 |
Jul 29 07:38:57 PM PDT 24 |
113858252 ps |
| T920 |
/workspace/coverage/default/38.sram_ctrl_multiple_keys.1131634328 |
|
|
Jul 29 07:38:44 PM PDT 24 |
Jul 29 07:41:40 PM PDT 24 |
1449096925 ps |
| T921 |
/workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.479963340 |
|
|
Jul 29 07:37:47 PM PDT 24 |
Jul 29 07:41:45 PM PDT 24 |
1124962857 ps |
| T922 |
/workspace/coverage/default/10.sram_ctrl_max_throughput.1560714898 |
|
|
Jul 29 07:37:03 PM PDT 24 |
Jul 29 07:38:33 PM PDT 24 |
533247810 ps |
| T923 |
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.1843252449 |
|
|
Jul 29 07:37:06 PM PDT 24 |
Jul 29 07:41:59 PM PDT 24 |
1393132316 ps |
| T924 |
/workspace/coverage/default/13.sram_ctrl_mem_partial_access.696199290 |
|
|
Jul 29 07:37:05 PM PDT 24 |
Jul 29 07:37:11 PM PDT 24 |
335417997 ps |
| T925 |
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.3550682649 |
|
|
Jul 29 07:39:28 PM PDT 24 |
Jul 29 07:39:30 PM PDT 24 |
107815423 ps |
| T926 |
/workspace/coverage/default/28.sram_ctrl_executable.3606155025 |
|
|
Jul 29 07:37:51 PM PDT 24 |
Jul 29 07:38:17 PM PDT 24 |
1472328946 ps |
| T927 |
/workspace/coverage/default/4.sram_ctrl_access_during_key_req.2220427921 |
|
|
Jul 29 07:37:00 PM PDT 24 |
Jul 29 07:51:35 PM PDT 24 |
3710627998 ps |
| T928 |
/workspace/coverage/default/46.sram_ctrl_max_throughput.224146342 |
|
|
Jul 29 07:39:36 PM PDT 24 |
Jul 29 07:40:31 PM PDT 24 |
113129469 ps |
| T929 |
/workspace/coverage/default/43.sram_ctrl_multiple_keys.648688039 |
|
|
Jul 29 07:39:15 PM PDT 24 |
Jul 29 08:05:23 PM PDT 24 |
35736159090 ps |
| T930 |
/workspace/coverage/default/29.sram_ctrl_multiple_keys.258615724 |
|
|
Jul 29 07:37:55 PM PDT 24 |
Jul 29 07:44:47 PM PDT 24 |
12779568164 ps |
| T931 |
/workspace/coverage/default/12.sram_ctrl_ram_cfg.3741976516 |
|
|
Jul 29 07:37:05 PM PDT 24 |
Jul 29 07:37:06 PM PDT 24 |
31696720 ps |
| T932 |
/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.3597454916 |
|
|
Jul 29 07:39:07 PM PDT 24 |
Jul 29 07:44:11 PM PDT 24 |
11495699576 ps |
| T933 |
/workspace/coverage/default/20.sram_ctrl_access_during_key_req.217057179 |
|
|
Jul 29 07:37:29 PM PDT 24 |
Jul 29 07:43:15 PM PDT 24 |
5352681882 ps |
| T934 |
/workspace/coverage/default/17.sram_ctrl_multiple_keys.2307529394 |
|
|
Jul 29 07:37:28 PM PDT 24 |
Jul 29 07:48:37 PM PDT 24 |
253966169233 ps |
| T117 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.4080901480 |
|
|
Jul 29 06:20:56 PM PDT 24 |
Jul 29 06:20:59 PM PDT 24 |
517835308 ps |
| T935 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1023980173 |
|
|
Jul 29 06:20:56 PM PDT 24 |
Jul 29 06:20:58 PM PDT 24 |
40596147 ps |
| T56 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2278506117 |
|
|
Jul 29 06:20:48 PM PDT 24 |
Jul 29 06:20:50 PM PDT 24 |
1241858203 ps |
| T57 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2469730959 |
|
|
Jul 29 06:20:52 PM PDT 24 |
Jul 29 06:20:54 PM PDT 24 |
617501080 ps |
| T60 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2027663967 |
|
|
Jul 29 06:20:41 PM PDT 24 |
Jul 29 06:20:42 PM PDT 24 |
42264326 ps |
| T118 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3449776279 |
|
|
Jul 29 06:20:44 PM PDT 24 |
Jul 29 06:20:47 PM PDT 24 |
1242754873 ps |
| T936 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2135326060 |
|
|
Jul 29 06:20:58 PM PDT 24 |
Jul 29 06:21:00 PM PDT 24 |
22708462 ps |
| T937 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1980490496 |
|
|
Jul 29 06:20:56 PM PDT 24 |
Jul 29 06:20:58 PM PDT 24 |
99026306 ps |
| T70 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1770793255 |
|
|
Jul 29 06:21:01 PM PDT 24 |
Jul 29 06:21:02 PM PDT 24 |
15482134 ps |
| T111 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.4235737315 |
|
|
Jul 29 06:20:37 PM PDT 24 |
Jul 29 06:20:38 PM PDT 24 |
53327092 ps |
| T101 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3902634594 |
|
|
Jul 29 06:20:49 PM PDT 24 |
Jul 29 06:20:51 PM PDT 24 |
286162332 ps |
| T102 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2774792628 |
|
|
Jul 29 06:20:52 PM PDT 24 |
Jul 29 06:20:53 PM PDT 24 |
31315991 ps |
| T71 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2420236181 |
|
|
Jul 29 06:20:46 PM PDT 24 |
Jul 29 06:20:47 PM PDT 24 |
24320186 ps |
| T72 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3257615942 |
|
|
Jul 29 06:20:50 PM PDT 24 |
Jul 29 06:20:54 PM PDT 24 |
779183095 ps |
| T938 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2067199110 |
|
|
Jul 29 06:20:52 PM PDT 24 |
Jul 29 06:20:55 PM PDT 24 |
53227290 ps |
| T58 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1521708571 |
|
|
Jul 29 06:20:53 PM PDT 24 |
Jul 29 06:20:54 PM PDT 24 |
93400911 ps |
| T73 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.319053567 |
|
|
Jul 29 06:21:01 PM PDT 24 |
Jul 29 06:21:02 PM PDT 24 |
35299896 ps |
| T74 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1462637667 |
|
|
Jul 29 06:20:48 PM PDT 24 |
Jul 29 06:20:49 PM PDT 24 |
46043148 ps |
| T939 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1277106892 |
|
|
Jul 29 06:20:52 PM PDT 24 |
Jul 29 06:20:53 PM PDT 24 |
30159419 ps |
| T75 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2055431289 |
|
|
Jul 29 06:20:48 PM PDT 24 |
Jul 29 06:20:49 PM PDT 24 |
17964357 ps |
| T76 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1965472779 |
|
|
Jul 29 06:20:40 PM PDT 24 |
Jul 29 06:20:41 PM PDT 24 |
20618557 ps |
| T940 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3311636058 |
|
|
Jul 29 06:20:51 PM PDT 24 |
Jul 29 06:20:52 PM PDT 24 |
13719187 ps |
| T941 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2429054290 |
|
|
Jul 29 06:20:55 PM PDT 24 |
Jul 29 06:20:57 PM PDT 24 |
36079534 ps |
| T124 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.836794094 |
|
|
Jul 29 06:20:57 PM PDT 24 |
Jul 29 06:20:59 PM PDT 24 |
321674274 ps |
| T77 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.188288472 |
|
|
Jul 29 06:20:50 PM PDT 24 |
Jul 29 06:20:52 PM PDT 24 |
266725031 ps |
| T103 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2633383786 |
|
|
Jul 29 06:20:51 PM PDT 24 |
Jul 29 06:20:52 PM PDT 24 |
13490868 ps |
| T78 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3776794401 |
|
|
Jul 29 06:21:03 PM PDT 24 |
Jul 29 06:21:04 PM PDT 24 |
80539016 ps |
| T942 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.193399139 |
|
|
Jul 29 06:21:00 PM PDT 24 |
Jul 29 06:21:01 PM PDT 24 |
61217560 ps |
| T943 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1687811205 |
|
|
Jul 29 06:20:50 PM PDT 24 |
Jul 29 06:20:52 PM PDT 24 |
47603013 ps |
| T104 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.384623383 |
|
|
Jul 29 06:20:47 PM PDT 24 |
Jul 29 06:20:48 PM PDT 24 |
30941576 ps |
| T944 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2712507879 |
|
|
Jul 29 06:21:03 PM PDT 24 |
Jul 29 06:21:05 PM PDT 24 |
81787890 ps |
| T945 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3283653371 |
|
|
Jul 29 06:20:47 PM PDT 24 |
Jul 29 06:20:48 PM PDT 24 |
32083952 ps |
| T105 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.720774800 |
|
|
Jul 29 06:20:51 PM PDT 24 |
Jul 29 06:20:52 PM PDT 24 |
28410345 ps |
| T106 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1567524290 |
|
|
Jul 29 06:20:49 PM PDT 24 |
Jul 29 06:20:50 PM PDT 24 |
68959995 ps |
| T946 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2014349341 |
|
|
Jul 29 06:20:49 PM PDT 24 |
Jul 29 06:20:50 PM PDT 24 |
14908479 ps |
| T947 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.4101106768 |
|
|
Jul 29 06:20:49 PM PDT 24 |
Jul 29 06:20:51 PM PDT 24 |
76369696 ps |
| T948 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3363001816 |
|
|
Jul 29 06:20:47 PM PDT 24 |
Jul 29 06:20:48 PM PDT 24 |
63946451 ps |
| T949 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2879253280 |
|
|
Jul 29 06:20:47 PM PDT 24 |
Jul 29 06:20:49 PM PDT 24 |
28455078 ps |
| T125 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2232798013 |
|
|
Jul 29 06:20:55 PM PDT 24 |
Jul 29 06:20:58 PM PDT 24 |
388563579 ps |
| T83 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1280304855 |
|
|
Jul 29 06:20:47 PM PDT 24 |
Jul 29 06:20:50 PM PDT 24 |
457939971 ps |
| T95 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1773534693 |
|
|
Jul 29 06:20:55 PM PDT 24 |
Jul 29 06:20:59 PM PDT 24 |
1551593350 ps |
| T950 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1536876326 |
|
|
Jul 29 06:21:01 PM PDT 24 |
Jul 29 06:21:02 PM PDT 24 |
14815558 ps |
| T951 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2712318470 |
|
|
Jul 29 06:20:42 PM PDT 24 |
Jul 29 06:20:43 PM PDT 24 |
45623884 ps |
| T952 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2413010294 |
|
|
Jul 29 06:20:50 PM PDT 24 |
Jul 29 06:20:51 PM PDT 24 |
36544690 ps |
| T84 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3063990604 |
|
|
Jul 29 06:21:02 PM PDT 24 |
Jul 29 06:21:03 PM PDT 24 |
27787144 ps |
| T129 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1732554255 |
|
|
Jul 29 06:20:52 PM PDT 24 |
Jul 29 06:20:54 PM PDT 24 |
646280528 ps |
| T953 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2803488108 |
|
|
Jul 29 06:20:45 PM PDT 24 |
Jul 29 06:20:46 PM PDT 24 |
127300085 ps |
| T954 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2906176031 |
|
|
Jul 29 06:20:51 PM PDT 24 |
Jul 29 06:20:53 PM PDT 24 |
235752434 ps |
| T955 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3084002302 |
|
|
Jul 29 06:20:52 PM PDT 24 |
Jul 29 06:20:53 PM PDT 24 |
53899506 ps |
| T956 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.773028100 |
|
|
Jul 29 06:20:47 PM PDT 24 |
Jul 29 06:20:48 PM PDT 24 |
112271312 ps |
| T957 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2021445313 |
|
|
Jul 29 06:20:52 PM PDT 24 |
Jul 29 06:20:56 PM PDT 24 |
46317550 ps |
| T85 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3474469121 |
|
|
Jul 29 06:20:48 PM PDT 24 |
Jul 29 06:20:49 PM PDT 24 |
37942587 ps |
| T958 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.230725848 |
|
|
Jul 29 06:20:55 PM PDT 24 |
Jul 29 06:20:56 PM PDT 24 |
21026700 ps |
| T959 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1590739797 |
|
|
Jul 29 06:20:50 PM PDT 24 |
Jul 29 06:20:53 PM PDT 24 |
285390511 ps |
| T86 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.649281454 |
|
|
Jul 29 06:21:01 PM PDT 24 |
Jul 29 06:21:03 PM PDT 24 |
470638673 ps |
| T87 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.767847669 |
|
|
Jul 29 06:20:51 PM PDT 24 |
Jul 29 06:20:53 PM PDT 24 |
314715557 ps |
| T960 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2457735251 |
|
|
Jul 29 06:20:47 PM PDT 24 |
Jul 29 06:20:49 PM PDT 24 |
63949108 ps |
| T961 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2273810729 |
|
|
Jul 29 06:21:01 PM PDT 24 |
Jul 29 06:21:02 PM PDT 24 |
80173660 ps |
| T134 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2940725461 |
|
|
Jul 29 06:20:45 PM PDT 24 |
Jul 29 06:20:47 PM PDT 24 |
820064159 ps |
| T962 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2644930878 |
|
|
Jul 29 06:20:50 PM PDT 24 |
Jul 29 06:20:51 PM PDT 24 |
107076242 ps |
| T963 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2463641994 |
|
|
Jul 29 06:20:46 PM PDT 24 |
Jul 29 06:20:48 PM PDT 24 |
100116238 ps |
| T964 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1307566408 |
|
|
Jul 29 06:20:57 PM PDT 24 |
Jul 29 06:20:59 PM PDT 24 |
86321277 ps |
| T965 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2030540600 |
|
|
Jul 29 06:20:49 PM PDT 24 |
Jul 29 06:20:50 PM PDT 24 |
44425085 ps |
| T966 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3430158494 |
|
|
Jul 29 06:20:58 PM PDT 24 |
Jul 29 06:21:00 PM PDT 24 |
31751772 ps |
| T130 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.893667482 |
|
|
Jul 29 06:20:55 PM PDT 24 |
Jul 29 06:20:58 PM PDT 24 |
738509847 ps |
| T88 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.592355970 |
|
|
Jul 29 06:21:05 PM PDT 24 |
Jul 29 06:21:05 PM PDT 24 |
28976236 ps |
| T967 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3592695619 |
|
|
Jul 29 06:20:46 PM PDT 24 |
Jul 29 06:20:47 PM PDT 24 |
27616255 ps |
| T968 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3789308778 |
|
|
Jul 29 06:20:54 PM PDT 24 |
Jul 29 06:20:55 PM PDT 24 |
21301679 ps |
| T100 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3552952996 |
|
|
Jul 29 06:20:51 PM PDT 24 |
Jul 29 06:20:52 PM PDT 24 |
14802711 ps |
| T96 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.4163867843 |
|
|
Jul 29 06:21:09 PM PDT 24 |
Jul 29 06:21:13 PM PDT 24 |
1627968183 ps |
| T969 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.313629912 |
|
|
Jul 29 06:20:47 PM PDT 24 |
Jul 29 06:20:51 PM PDT 24 |
356588941 ps |
| T970 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2353307471 |
|
|
Jul 29 06:20:51 PM PDT 24 |
Jul 29 06:20:52 PM PDT 24 |
44885375 ps |
| T97 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2440537110 |
|
|
Jul 29 06:20:49 PM PDT 24 |
Jul 29 06:20:53 PM PDT 24 |
2214225687 ps |
| T98 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.248495719 |
|
|
Jul 29 06:21:00 PM PDT 24 |
Jul 29 06:21:04 PM PDT 24 |
676136020 ps |
| T971 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2617173149 |
|
|
Jul 29 06:20:51 PM PDT 24 |
Jul 29 06:20:52 PM PDT 24 |
39952629 ps |
| T972 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2185172557 |
|
|
Jul 29 06:20:52 PM PDT 24 |
Jul 29 06:20:56 PM PDT 24 |
97012748 ps |
| T973 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3531963867 |
|
|
Jul 29 06:20:45 PM PDT 24 |
Jul 29 06:20:46 PM PDT 24 |
17653400 ps |
| T974 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.341428415 |
|
|
Jul 29 06:20:46 PM PDT 24 |
Jul 29 06:20:47 PM PDT 24 |
17366677 ps |
| T975 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.428067346 |
|
|
Jul 29 06:20:50 PM PDT 24 |
Jul 29 06:20:53 PM PDT 24 |
749943474 ps |
| T131 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3239556189 |
|
|
Jul 29 06:20:44 PM PDT 24 |
Jul 29 06:20:47 PM PDT 24 |
634939698 ps |
| T128 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3483016277 |
|
|
Jul 29 06:20:51 PM PDT 24 |
Jul 29 06:20:53 PM PDT 24 |
159511445 ps |
| T976 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3861481934 |
|
|
Jul 29 06:20:41 PM PDT 24 |
Jul 29 06:20:42 PM PDT 24 |
20543843 ps |
| T977 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2202730574 |
|
|
Jul 29 06:20:47 PM PDT 24 |
Jul 29 06:20:48 PM PDT 24 |
133437729 ps |
| T99 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3773752515 |
|
|
Jul 29 06:20:58 PM PDT 24 |
Jul 29 06:21:00 PM PDT 24 |
219082788 ps |
| T132 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2383838883 |
|
|
Jul 29 06:20:50 PM PDT 24 |
Jul 29 06:20:53 PM PDT 24 |
241099655 ps |
| T978 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.914358278 |
|
|
Jul 29 06:20:59 PM PDT 24 |
Jul 29 06:21:03 PM PDT 24 |
805963372 ps |
| T979 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3585557684 |
|
|
Jul 29 06:20:45 PM PDT 24 |
Jul 29 06:20:49 PM PDT 24 |
545432143 ps |
| T980 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3466663545 |
|
|
Jul 29 06:20:53 PM PDT 24 |
Jul 29 06:20:56 PM PDT 24 |
455993041 ps |
| T981 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.829715773 |
|
|
Jul 29 06:20:59 PM PDT 24 |
Jul 29 06:21:01 PM PDT 24 |
41592365 ps |
| T982 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2573540322 |
|
|
Jul 29 06:20:40 PM PDT 24 |
Jul 29 06:20:42 PM PDT 24 |
76540916 ps |
| T983 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3931662050 |
|
|
Jul 29 06:20:54 PM PDT 24 |
Jul 29 06:20:55 PM PDT 24 |
52690858 ps |
| T984 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1683680629 |
|
|
Jul 29 06:20:53 PM PDT 24 |
Jul 29 06:20:54 PM PDT 24 |
134639720 ps |
| T985 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2462960774 |
|
|
Jul 29 06:20:47 PM PDT 24 |
Jul 29 06:20:50 PM PDT 24 |
430816963 ps |
| T986 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3695208603 |
|
|
Jul 29 06:20:48 PM PDT 24 |
Jul 29 06:20:51 PM PDT 24 |
31823943 ps |
| T987 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2537975444 |
|
|
Jul 29 06:20:48 PM PDT 24 |
Jul 29 06:20:50 PM PDT 24 |
86374244 ps |
| T988 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.318713257 |
|
|
Jul 29 06:20:48 PM PDT 24 |
Jul 29 06:20:53 PM PDT 24 |
279365183 ps |
| T989 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3077499785 |
|
|
Jul 29 06:21:00 PM PDT 24 |
Jul 29 06:21:02 PM PDT 24 |
428950113 ps |
| T990 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.4039657506 |
|
|
Jul 29 06:20:56 PM PDT 24 |
Jul 29 06:20:57 PM PDT 24 |
56595155 ps |
| T991 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1125423842 |
|
|
Jul 29 06:20:50 PM PDT 24 |
Jul 29 06:20:54 PM PDT 24 |
82279207 ps |
| T992 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.4274881685 |
|
|
Jul 29 06:20:39 PM PDT 24 |
Jul 29 06:20:42 PM PDT 24 |
120904711 ps |
| T993 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3838346348 |
|
|
Jul 29 06:20:43 PM PDT 24 |
Jul 29 06:20:44 PM PDT 24 |
22946664 ps |
| T994 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3452147337 |
|
|
Jul 29 06:20:51 PM PDT 24 |
Jul 29 06:20:52 PM PDT 24 |
50093646 ps |
| T995 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2711472197 |
|
|
Jul 29 06:21:00 PM PDT 24 |
Jul 29 06:21:04 PM PDT 24 |
66804007 ps |
| T996 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3691763399 |
|
|
Jul 29 06:20:51 PM PDT 24 |
Jul 29 06:20:53 PM PDT 24 |
79266209 ps |
| T997 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.375420503 |
|
|
Jul 29 06:20:50 PM PDT 24 |
Jul 29 06:20:54 PM PDT 24 |
2854767063 ps |
| T135 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3180964119 |
|
|
Jul 29 06:20:48 PM PDT 24 |
Jul 29 06:20:50 PM PDT 24 |
208898864 ps |
| T126 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.518884555 |
|
|
Jul 29 06:20:50 PM PDT 24 |
Jul 29 06:20:52 PM PDT 24 |
483447741 ps |
| T998 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.342872055 |
|
|
Jul 29 06:20:48 PM PDT 24 |
Jul 29 06:20:50 PM PDT 24 |
493439267 ps |
| T999 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2478761179 |
|
|
Jul 29 06:20:48 PM PDT 24 |
Jul 29 06:20:50 PM PDT 24 |
202833894 ps |
| T1000 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2140424711 |
|
|
Jul 29 06:20:43 PM PDT 24 |
Jul 29 06:20:44 PM PDT 24 |
126584164 ps |
| T133 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2527049155 |
|
|
Jul 29 06:20:49 PM PDT 24 |
Jul 29 06:20:50 PM PDT 24 |
100347743 ps |
| T1001 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.556012744 |
|
|
Jul 29 06:20:50 PM PDT 24 |
Jul 29 06:20:51 PM PDT 24 |
59836201 ps |