Unified Coverage Report :: Module :: sram_ctrl

Module : sram_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.54	100.00	87.13	100.00		100.00	70.59

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	91.90	100.00	88.89	100.00		100.00	70.59

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.90	100.00	88.89	100.00		100.00	70.59

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.04	99.16	94.27	99.72	100.00	95.95	99.12

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
sram_ctrl_regs_csr_assert	100.00						100.00
tlul_assert_device_ram	100.00	100.00				100.00	100.00
tlul_assert_device_regs	100.00	100.00				100.00	100.00
u_lfsr	100.00			100.00
u_prim_alert_sender_parity	100.00			100.00
u_prim_count	100.00			100.00
u_prim_lc_sync	100.00	100.00				100.00	100.00
u_prim_ram_1p_scr	99.85	99.26	100.00	100.00		100.00	100.00
u_prim_sync_reqack_data	100.00	100.00	100.00			100.00	100.00
u_reg_regs	98.03	98.43	96.44	100.00		95.28	100.00
u_tlul_adapter_sram	97.56	99.10	93.51	98.44	100.00	94.29	100.00
u_tlul_data_integ_enc	100.00	100.00
u_tlul_lc_gate	96.79	100.00	100.00		100.00	96.43	87.50

Line Coverage for Module : sram_ctrl

	Line No.	Total	Covered	Percent
TOTAL		52	52	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	186	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	226	1	1	100.00
ALWAYS	230	3	3	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	279	1	1	100.00
CONT_ASSIGN	284	1	1	100.00
CONT_ASSIGN	288	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	294	1	1	100.00
CONT_ASSIGN	298	1	1	100.00
CONT_ASSIGN	299	1	1	100.00
ALWAYS	302	11	11	100.00
CONT_ASSIGN	346	1	1	100.00
CONT_ASSIGN	389	1	1	100.00
CONT_ASSIGN	466	1	1	100.00
CONT_ASSIGN	507	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	514	1	1	100.00
CONT_ASSIGN	515	1	1	100.00
CONT_ASSIGN	516	1	1	100.00
CONT_ASSIGN	517	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	529	1	1	100.00
CONT_ASSIGN	567	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv' or '../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
126	1	1
134	1	1
137	1	1
141	1	1
145	1	1
149	1	1
152	1	1
184	1	1
186	1	1
194	1	1
202	1	1
212	1	1
221	1	1
226	1	1
230	1	1
231	1	1
233	1	1
242	1	1
243	1	1
267	1	1
268	1	1
279	1	1
284	1	1
288	1	1
289	1	1
293	1	1
294	1	1
298	1	1
299	1	1
302	1	1
303	1	1
306	1	1
307	1	1
309	1	1
310	1	1
311	1	1
312	1	1
			MISSING_ELSE
317	1	1
318	1	1
319	1	1
			MISSING_ELSE
346	1	1
389	1	1
466	1	1
507	1	1
513	1	1
514	1	1
515	1	1
516	1	1
517	1	1
518	1	1
529	1	1
567	1	1

---

Cond Coverage for Module : sram_ctrl

	Total	Covered	Percent
Conditions	101	88	87.13
Logical	101	88	87.13
Non-Logical	0	0
Event	0	0

 LINE       134
 EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
             ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T9,T10

 LINE       152
 EXPRESSION (((|bus_integ_error)) | init_error | readback_error | sram_alert)
             ----------1---------   -----2----   -------3------   -----4----

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Not Covered
0	1	0	0	Covered	T14,T15,T16
1	0	0	0	Covered	T14,T15,T16

 LINE       194
 EXPRESSION 
 Number  Term
      1  reg2hw.status.escalated.q | 
      2  reg2hw.status.init_error.q | 
      3  reg2hw.status.bus_integ_error.q | 
      4  reg2hw.status.sram_alert.q | 
      5  reg2hw.status.readback_error.q)

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	1	Not Covered
0	0	0	1	0	Not Covered
0	0	1	0	0	Covered	T14,T15,T16
0	1	0	0	0	Covered	T14,T15,T16
1	0	0	0	0	Covered	T6,T7,T8

 LINE       202
 EXPRESSION (escalate | init_error | ((|bus_integ_error)) | sram_alert | readback_error | local_esc_reg)
             ----1---   -----2----   ----------3---------   -----4----   -------5------   ------6------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	0	1	Covered	T6,T7,T8
0	0	0	0	1	0	Not Covered
0	0	0	1	0	0	Not Covered
0	0	1	0	0	0	Covered	T14,T15,T16
0	1	0	0	0	0	Covered	T14,T15,T16
1	0	0	0	0	0	Covered	T6,T7,T8

 LINE       221
 EXPRESSION (reg2hw.ctrl.init.q && reg2hw.ctrl.init.qe && ((!init_q)))
             ---------1--------    ---------2---------    -----3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T11,T6
1	0	1	Covered	T1,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       226
 EXPRESSION (init_done ? 1'b0 : (init_trig ? 1'b1 : init_q))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       226
 SUB-EXPRESSION (init_trig ? 1'b1 : init_q)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       242
 EXPRESSION (init_q & ((~key_req_pending_q)))
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       243
 EXPRESSION ((init_cnt == 10'((Depth - 1))) & init_req)
             ---------------1--------------   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       243
 SUB-EXPRESSION (init_cnt == 10'((Depth - 1)))
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       267
 EXPRESSION (init_done & ((~init_trig)) & ((~local_esc)))
             ----1----   -------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T6,T7,T8
1	1	1	Covered	T1,T3,T4

 LINE       268
 EXPRESSION (init_done | init_trig | local_esc)
             ----1----   ----2----   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T6,T7,T8
0	1	0	Covered	T1,T3,T4
1	0	0	Covered	T1,T3,T4

 LINE       279
 EXPRESSION (reg2hw.ctrl.renew_scr_key.q && reg2hw.ctrl.renew_scr_key.qe && ((!key_req_pending_q)) && ((!init_q)))
             -------------1-------------    --------------2-------------    -----------3----------    -----4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T7,T17,T18
1	0	1	1	Covered	T1,T3,T4
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T3,T4

 LINE       284
 EXPRESSION (key_req ? 1'b1 : (key_ack ? 1'b0 : key_req_pending_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       284
 SUB-EXPRESSION (key_ack ? 1'b0 : key_req_pending_q)
                 ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       288
 EXPRESSION (key_ack & ((~key_req)) & ((~local_esc)))
             ---1---   ------2-----   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T6,T7,T8
1	1	1	Covered	T1,T3,T4

 LINE       289
 EXPRESSION (key_req | key_ack | local_esc)
             ---1---   ---2---   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T6,T7,T8
0	1	0	Covered	T1,T3,T4
1	0	0	Covered	T1,T3,T4

 LINE       293
 EXPRESSION ((key_ack & ((~local_esc))) ? MuBi4True : MuBi4False)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       293
 SUB-EXPRESSION (key_ack & ((~local_esc)))
                 ---1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T8
1	1	Covered	T1,T3,T4

 LINE       294
 EXPRESSION (key_ack | local_esc)
             ---1---   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T3,T4

 LINE       298
 EXPRESSION (key_seed_valid & ((~local_esc)))
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T6,T7,T8
1	1	Covered	T3,T4,T5

 LINE       299
 EXPRESSION (key_ack | local_esc)
             ---1---   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T3,T4

 LINE       507
 EXPRESSION (tlul_req | init_req)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       513
 EXPRESSION (key_valid & ((~init_req)))
             ----1----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       514
 EXPRESSION (tlul_we | init_req)
             ---1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       515
 EXPRESSION (((|bus_integ_error[2:1])) & ((~init_req)))
             ------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T14,T15,T16

 LINE       516
 EXPRESSION (init_req ? init_cnt : tlul_addr)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       517
 EXPRESSION (init_req ? lfsr_out_integ : tlul_wdata)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       518
 EXPRESSION (init_req ? ({sram_ctrl_pkg::DataWidth {1'b1}}) : tlul_wmask)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       529
 EXPRESSION (key_req_pending_q ? 1'b0 : (reg2hw.status.escalated.q ? (tl_gate_resp_pending & sram_compound_txn_in_progress) : 1'b1))
             --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       529
 SUB-EXPRESSION (reg2hw.status.escalated.q ? (tl_gate_resp_pending & sram_compound_txn_in_progress) : 1'b1)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T8

 LINE       529
 SUB-EXPRESSION (tl_gate_resp_pending & sram_compound_txn_in_progress)
                 ----------1---------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

---

Toggle Coverage for Module : sram_ctrl

	Total	Covered	Percent
Totals	62	62	100.00
Total Bits	1230	1230	100.00
Total Bits 0->1	615	615	100.00
Total Bits 1->0	615	615	100.00

Ports	62	62	100.00
Port Bits	1230	1230	100.00
Port Bits 0->1	615	615	100.00
Port Bits 1->0	615	615	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T5,T6,T7	Yes	T1,T2,T3	INPUT
clk_otp_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_otp_ni	Yes	Yes	T5,T6,T7	Yes	T1,T2,T3	INPUT
ram_tl_i.d_ready	Yes	Yes	T2,T3,T9	Yes	T1,T2,T3	INPUT
ram_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
ram_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
ram_tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T12	Yes	T4,T5,T12	INPUT
ram_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_data[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
ram_tl_i.a_mask[3:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
ram_tl_i.a_address[31:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
ram_tl_i.a_source[7:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
ram_tl_i.a_size[1:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
ram_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_opcode[2:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
ram_tl_i.a_valid	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
ram_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_error	Yes	Yes	T1,T2,T3	Yes	T4,T5,T6	OUTPUT
ram_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
ram_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,T3,T4	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_data[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
ram_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_source[7:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
ram_tl_o.d_size[1:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
ram_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_opcode[0]	Yes	Yes	*T1,*T3,*T4	Yes	T1,T3,T4	OUTPUT
ram_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_valid	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T2,T3,T9	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T2,T9,T4	Yes	T2,T3,T9	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T9	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.instr_type[3:0]	Yes	Yes	T3,T19,T7	Yes	T3,T19,T20	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T2,T3,T9	Yes	T2,T3,T9	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T3,T5,T19	Yes	T3,T5,T19	INPUT
regs_tl_i.a_address[31:0]	Yes	Yes	T3,T5,T19	Yes	T3,T5,T19	INPUT
regs_tl_i.a_source[7:0]	Yes	Yes	T3,T9,T5	Yes	T3,T9,T5	INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T2,T3,T9	Yes	T2,T3,T9	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T9	INPUT
regs_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_error	Yes	Yes	T21,T22,T23	Yes	T21,T22,T23	OUTPUT
regs_tl_o.d_user.data_intg[6:0]	Yes	Yes	T6,T7,T8	Yes	T6,T7,T8	OUTPUT
regs_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T2,*T9,*T4	Yes	T2,T3,T9	OUTPUT
regs_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T5,T6,T7	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_source[7:0]	Yes	Yes	T3,T9,T5	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_size[1:0]	Yes	Yes	T2,T3,T9	Yes	T2,T3,T9	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T5,*T6,*T7	Yes	T5,T6,T7	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T2,T9,T10	Yes	T2,T9,T10	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T2,T9,T10	Yes	T2,T9,T10	OUTPUT
lc_escalate_en_i[3:0]	Yes	Yes	T6,T7,T8	Yes	T6,T7,T8	INPUT
lc_hw_debug_en_i[3:0]	Yes	Yes	T4,T5,T7	Yes	T4,T5,T7	INPUT
otp_en_sram_ifetch_i[7:0]	Yes	Yes	T4,T5,T7	Yes	T4,T5,T7	INPUT
sram_otp_key_o.req	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
sram_otp_key_i.seed_valid	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	INPUT
sram_otp_key_i.nonce[127:0]	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	INPUT
sram_otp_key_i.key[127:0]	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	INPUT
sram_otp_key_i.ack	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
cfg_i.rf_cfg.cfg[3:0]	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	INPUT
cfg_i.rf_cfg.cfg_en	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	INPUT
cfg_i.rf_cfg.test	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	INPUT
cfg_i.ram_cfg.cfg[3:0]	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	INPUT
cfg_i.ram_cfg.cfg_en	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	INPUT
cfg_i.ram_cfg.test	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	INPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : sram_ctrl

	Line No.	Total	Covered	Percent
Branches		24	24	100.00
TERNARY	226	3	3	100.00
TERNARY	284	3	3	100.00
TERNARY	293	2	2	100.00
TERNARY	516	2	2	100.00
TERNARY	517	2	2	100.00
TERNARY	518	2	2	100.00
TERNARY	529	3	3	100.00
IF	230	2	2	100.00
IF	302	5	5	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv' or '../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	226	(init_done) ? 
-2-:	226	(init_trig) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T4
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	284	(key_req) ? 
-2-:	284	(key_ack) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T4
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	293	((key_ack & (~local_esc))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	516	(init_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	517	(init_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	518	(init_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	529	(key_req_pending_q) ? 
-2-:	529	(reg2hw.status.escalated.q) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T4
0	1	Covered	T6,T7,T8
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	230	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	302	if ((!rst_ni))
-2-:	310	if (key_ack)
-3-:	317	if (local_esc)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	-	Covered	T1,T2,T3
0	-	1	Covered	T6,T7,T8
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : sram_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	12	70.59
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	12	70.59

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertOutKnown_A	316651429	316547296	0	0
FpvSecCmCntCheck_A	316651429	80	0	0
FpvSecCmLcGateFsmCheck_A	316651429	0	0	0
FpvSecCmRegWeOnehotCheck_A	316651429	80	0	0
FpvSecCmReqFifoRptrCheck_A	316651429	0	0	0
FpvSecCmReqFifoWptrCheck_A	316651429	0	0	0
FpvSecCmRspFifoRptrCheck_A	316651429	80	0	0
FpvSecCmRspFifoWptrCheck_A	316651429	80	0	0
FpvSecCmSramReqFifoRptrCheck_A	316651429	0	0	0
FpvSecCmSramReqFifoWptrCheck_A	316651429	0	0	0
NonceWidthsLessThanSource_A	891	891	0	0
RamTlOutKnown_A	316651429	316547296	0	0
RamTlOutPayLoadKnown_A	316651429	139519501	0	0
RamTlOutPayLoadKnown_AKnownEnable	316651429	316547296	0	0
RegsTlOutKnown_A	316651429	316547296	0	0
SramOtpKeyKnown_A	316651429	316547296	0	0
TlulGntIsCorrect_A	316651429	62870418	0	0

AlertOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316651429	316547296	0	0
T1	11164	11082	0	0
T2	1306	1242	0	0
T3	14515	14453	0	0
T4	163766	163697	0	0
T5	784616	784514	0	0
T9	879	825	0	0
T10	2046	1983	0	0
T11	275154	275075	0	0
T12	262323	262270	0	0
T13	226205	226139	0	0

FpvSecCmCntCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316651429	80	0	0
T14	21519	20	0	0
T15	0	20	0	0
T16	0	20	0	0
T27	0	10	0	0
T28	0	10	0	0
T29	519669	0	0	0
T30	3249	0	0	0
T31	89221	0	0	0
T32	8053	0	0	0
T33	25522	0	0	0
T34	12248	0	0	0
T35	47226	0	0	0
T36	310254	0	0	0
T37	28519	0	0	0

FpvSecCmLcGateFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316651429	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316651429	80	0	0
T14	21519	20	0	0
T15	0	20	0	0
T16	0	20	0	0
T27	0	10	0	0
T28	0	10	0	0
T29	519669	0	0	0
T30	3249	0	0	0
T31	89221	0	0	0
T32	8053	0	0	0
T33	25522	0	0	0
T34	12248	0	0	0
T35	47226	0	0	0
T36	310254	0	0	0
T37	28519	0	0	0

FpvSecCmReqFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316651429	0	0	0

FpvSecCmReqFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316651429	0	0	0

FpvSecCmRspFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316651429	80	0	0
T14	21519	20	0	0
T15	0	20	0	0
T16	0	20	0	0
T27	0	10	0	0
T28	0	10	0	0
T29	519669	0	0	0
T30	3249	0	0	0
T31	89221	0	0	0
T32	8053	0	0	0
T33	25522	0	0	0
T34	12248	0	0	0
T35	47226	0	0	0
T36	310254	0	0	0
T37	28519	0	0	0

FpvSecCmRspFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316651429	80	0	0
T14	21519	20	0	0
T15	0	20	0	0
T16	0	20	0	0
T27	0	10	0	0
T28	0	10	0	0
T29	519669	0	0	0
T30	3249	0	0	0
T31	89221	0	0	0
T32	8053	0	0	0
T33	25522	0	0	0
T34	12248	0	0	0
T35	47226	0	0	0
T36	310254	0	0	0
T37	28519	0	0	0

FpvSecCmSramReqFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316651429	0	0	0

FpvSecCmSramReqFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316651429	0	0	0

NonceWidthsLessThanSource_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	891	891	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

RamTlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316651429	316547296	0	0
T1	11164	11082	0	0
T2	1306	1242	0	0
T3	14515	14453	0	0
T4	163766	163697	0	0
T5	784616	784514	0	0
T9	879	825	0	0
T10	2046	1983	0	0
T11	275154	275075	0	0
T12	262323	262270	0	0
T13	226205	226139	0	0

RamTlOutPayLoadKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316651429	139519501	0	0
T1	11164	6890	0	0
T2	1306	0	0	0
T3	14515	5448	0	0
T4	163766	100630	0	0
T5	784616	498578	0	0
T9	879	0	0	0
T10	2046	0	0	0
T11	275154	38912	0	0
T12	262323	215571	0	0
T13	226205	182674	0	0
T19	0	9602	0	0
T38	0	9547	0	0
T39	0	9349	0	0

RamTlOutPayLoadKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	316651429	316547296	0	0
T1	11164	11082	0	0
T2	1306	1242	0	0
T3	14515	14453	0	0
T4	163766	163697	0	0
T5	784616	784514	0	0
T9	879	825	0	0
T10	2046	1983	0	0
T11	275154	275075	0	0
T12	262323	262270	0	0
T13	226205	226139	0	0

RegsTlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316651429	316547296	0	0
T1	11164	11082	0	0
T2	1306	1242	0	0
T3	14515	14453	0	0
T4	163766	163697	0	0
T5	784616	784514	0	0
T9	879	825	0	0
T10	2046	1983	0	0
T11	275154	275075	0	0
T12	262323	262270	0	0
T13	226205	226139	0	0

SramOtpKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316651429	316547296	0	0
T1	11164	11082	0	0
T2	1306	1242	0	0
T3	14515	14453	0	0
T4	163766	163697	0	0
T5	784616	784514	0	0
T9	879	825	0	0
T10	2046	1983	0	0
T11	275154	275075	0	0
T12	262323	262270	0	0
T13	226205	226139	0	0

TlulGntIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316651429	62870418	0	0
T1	11164	6890	0	0
T2	1306	0	0	0
T3	14515	3076	0	0
T4	163766	42133	0	0
T5	784616	239718	0	0
T9	879	0	0	0
T10	2046	0	0	0
T11	275154	38912	0	0
T12	262323	225454	0	0
T13	226205	190862	0	0
T19	0	10498	0	0
T38	0	9547	0	0
T39	0	13245	0	0

Line Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
TOTAL		52	52	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	186	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	226	1	1	100.00
ALWAYS	230	3	3	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	279	1	1	100.00
CONT_ASSIGN	284	1	1	100.00
CONT_ASSIGN	288	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	294	1	1	100.00
CONT_ASSIGN	298	1	1	100.00
CONT_ASSIGN	299	1	1	100.00
ALWAYS	302	11	11	100.00
CONT_ASSIGN	346	1	1	100.00
CONT_ASSIGN	389	1	1	100.00
CONT_ASSIGN	466	1	1	100.00
CONT_ASSIGN	507	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	514	1	1	100.00
CONT_ASSIGN	515	1	1	100.00
CONT_ASSIGN	516	1	1	100.00
CONT_ASSIGN	517	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	529	1	1	100.00
CONT_ASSIGN	567	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv' or '../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
126	1	1
134	1	1
137	1	1
141	1	1
145	1	1
149	1	1
152	1	1
184	1	1
186	1	1
194	1	1
202	1	1
212	1	1
221	1	1
226	1	1
230	1	1
231	1	1
233	1	1
242	1	1
243	1	1
267	1	1
268	1	1
279	1	1
284	1	1
288	1	1
289	1	1
293	1	1
294	1	1
298	1	1
299	1	1
302	1	1
303	1	1
306	1	1
307	1	1
309	1	1
310	1	1
311	1	1
312	1	1
			MISSING_ELSE
317	1	1
318	1	1
319	1	1
			MISSING_ELSE
346	1	1
389	1	1
466	1	1
507	1	1
513	1	1
514	1	1
515	1	1
516	1	1
517	1	1
518	1	1
529	1	1
567	1	1

---

Cond Coverage for Instance : tb.dut

	Total	Covered	Percent
Conditions	99	88	88.89
Logical	99	88	88.89
Non-Logical	0	0
Event	0	0

 LINE       134
 EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
             ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T9,T10

 LINE       152
 EXPRESSION (((|bus_integ_error)) | init_error | readback_error | sram_alert)
             ----------1---------   -----2----   -------3------   -----4----

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Not Covered
0	1	0	0	Covered	T14,T15,T16
1	0	0	0	Covered	T14,T15,T16

 LINE       194
 EXPRESSION 
 Number  Term
      1  reg2hw.status.escalated.q | 
      2  reg2hw.status.init_error.q | 
      3  reg2hw.status.bus_integ_error.q | 
      4  reg2hw.status.sram_alert.q | 
      5  reg2hw.status.readback_error.q)

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	1	Not Covered
0	0	0	1	0	Not Covered
0	0	1	0	0	Covered	T14,T15,T16
0	1	0	0	0	Covered	T14,T15,T16
1	0	0	0	0	Covered	T6,T7,T8

 LINE       202
 EXPRESSION (escalate | init_error | ((|bus_integ_error)) | sram_alert | readback_error | local_esc_reg)
             ----1---   -----2----   ----------3---------   -----4----   -------5------   ------6------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	0	1	Covered	T6,T7,T8
0	0	0	0	1	0	Not Covered
0	0	0	1	0	0	Not Covered
0	0	1	0	0	0	Covered	T14,T15,T16
0	1	0	0	0	0	Covered	T14,T15,T16
1	0	0	0	0	0	Covered	T6,T7,T8

 LINE       221
 EXPRESSION (reg2hw.ctrl.init.q && reg2hw.ctrl.init.qe && ((!init_q)))
             ---------1--------    ---------2---------    -----3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T11,T6
1	0	1	Covered	T1,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       226
 EXPRESSION (init_done ? 1'b0 : (init_trig ? 1'b1 : init_q))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       226
 SUB-EXPRESSION (init_trig ? 1'b1 : init_q)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       242
 EXPRESSION (init_q & ((~key_req_pending_q)))
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       243
 EXPRESSION ((init_cnt == 10'((Depth - 1))) & init_req)
             ---------------1--------------   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       243
 SUB-EXPRESSION (init_cnt == 10'((Depth - 1)))
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       267
 EXPRESSION (init_done & ((~init_trig)) & ((~local_esc)))
             ----1----   -------2------   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		[LOWRISK] we don't issue a new init when there is a unfinished init
1	1	0	Covered	T6,T7,T8
1	1	1	Covered	T1,T3,T4

 LINE       268
 EXPRESSION (init_done | init_trig | local_esc)
             ----1----   ----2----   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T6,T7,T8
0	1	0	Covered	T1,T3,T4
1	0	0	Covered	T1,T3,T4

 LINE       279
 EXPRESSION (reg2hw.ctrl.renew_scr_key.q && reg2hw.ctrl.renew_scr_key.qe && ((!key_req_pending_q)) && ((!init_q)))
             -------------1-------------    --------------2-------------    -----------3----------    -----4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T7,T17,T18
1	0	1	1	Covered	T1,T3,T4
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T3,T4

 LINE       284
 EXPRESSION (key_req ? 1'b1 : (key_ack ? 1'b0 : key_req_pending_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       284
 SUB-EXPRESSION (key_ack ? 1'b0 : key_req_pending_q)
                 ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       288
 EXPRESSION (key_ack & ((~key_req)) & ((~local_esc)))
             ---1---   ------2-----   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		[UNSUPPORTED] ACK can't come without REQ
1	1	0	Covered	T6,T7,T8
1	1	1	Covered	T1,T3,T4

 LINE       289
 EXPRESSION (key_req | key_ack | local_esc)
             ---1---   ---2---   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T6,T7,T8
0	1	0	Covered	T1,T3,T4
1	0	0	Covered	T1,T3,T4

 LINE       293
 EXPRESSION ((key_ack & ((~local_esc))) ? MuBi4True : MuBi4False)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       293
 SUB-EXPRESSION (key_ack & ((~local_esc)))
                 ---1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T8
1	1	Covered	T1,T3,T4

 LINE       294
 EXPRESSION (key_ack | local_esc)
             ---1---   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T3,T4

 LINE       298
 EXPRESSION (key_seed_valid & ((~local_esc)))
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T6,T7,T8
1	1	Covered	T3,T4,T5

 LINE       299
 EXPRESSION (key_ack | local_esc)
             ---1---   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T3,T4

 LINE       507
 EXPRESSION (tlul_req | init_req)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       513
 EXPRESSION (key_valid & ((~init_req)))
             ----1----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       514
 EXPRESSION (tlul_we | init_req)
             ---1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       515
 EXPRESSION (((|bus_integ_error[2:1])) & ((~init_req)))
             ------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T14,T15,T16

 LINE       516
 EXPRESSION (init_req ? init_cnt : tlul_addr)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       517
 EXPRESSION (init_req ? lfsr_out_integ : tlul_wdata)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       518
 EXPRESSION (init_req ? ({sram_ctrl_pkg::DataWidth {1'b1}}) : tlul_wmask)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       529
 EXPRESSION (key_req_pending_q ? 1'b0 : (reg2hw.status.escalated.q ? (tl_gate_resp_pending & sram_compound_txn_in_progress) : 1'b1))
             --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       529
 SUB-EXPRESSION (reg2hw.status.escalated.q ? (tl_gate_resp_pending & sram_compound_txn_in_progress) : 1'b1)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T8

 LINE       529
 SUB-EXPRESSION (tl_gate_resp_pending & sram_compound_txn_in_progress)
                 ----------1---------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

---

Toggle Coverage for Instance : tb.dut

	Total	Covered	Percent
Totals	62	62	100.00
Total Bits	1230	1230	100.00
Total Bits 0->1	615	615	100.00
Total Bits 1->0	615	615	100.00

Ports	62	62	100.00
Port Bits	1230	1230	100.00
Port Bits 0->1	615	615	100.00
Port Bits 1->0	615	615	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T5,T6,T7	Yes	T1,T2,T3	INPUT
clk_otp_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_otp_ni	Yes	Yes	T5,T6,T7	Yes	T1,T2,T3	INPUT
ram_tl_i.d_ready	Yes	Yes	T2,T3,T9	Yes	T1,T2,T3	INPUT
ram_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
ram_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
ram_tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T12	Yes	T4,T5,T12	INPUT
ram_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_data[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
ram_tl_i.a_mask[3:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
ram_tl_i.a_address[31:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
ram_tl_i.a_source[7:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
ram_tl_i.a_size[1:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
ram_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_opcode[2:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
ram_tl_i.a_valid	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
ram_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_error	Yes	Yes	T1,T2,T3	Yes	T4,T5,T6	OUTPUT
ram_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
ram_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,T3,T4	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_data[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
ram_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_source[7:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
ram_tl_o.d_size[1:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
ram_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_opcode[0]	Yes	Yes	*T1,*T3,*T4	Yes	T1,T3,T4	OUTPUT
ram_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_valid	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T2,T3,T9	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T2,T9,T4	Yes	T2,T3,T9	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T9	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.instr_type[3:0]	Yes	Yes	T3,T19,T7	Yes	T3,T19,T20	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T2,T3,T9	Yes	T2,T3,T9	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T3,T5,T19	Yes	T3,T5,T19	INPUT
regs_tl_i.a_address[31:0]	Yes	Yes	T3,T5,T19	Yes	T3,T5,T19	INPUT
regs_tl_i.a_source[7:0]	Yes	Yes	T3,T9,T5	Yes	T3,T9,T5	INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T2,T3,T9	Yes	T2,T3,T9	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T9	INPUT
regs_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_error	Yes	Yes	T21,T22,T23	Yes	T21,T22,T23	OUTPUT
regs_tl_o.d_user.data_intg[6:0]	Yes	Yes	T6,T7,T8	Yes	T6,T7,T8	OUTPUT
regs_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T2,*T9,*T4	Yes	T2,T3,T9	OUTPUT
regs_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T5,T6,T7	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_source[7:0]	Yes	Yes	T3,T9,T5	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_size[1:0]	Yes	Yes	T2,T3,T9	Yes	T2,T3,T9	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T5,*T6,*T7	Yes	T5,T6,T7	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T2,T9,T10	Yes	T2,T9,T10	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T2,T9,T10	Yes	T2,T9,T10	OUTPUT
lc_escalate_en_i[3:0]	Yes	Yes	T6,T7,T8	Yes	T6,T7,T8	INPUT
lc_hw_debug_en_i[3:0]	Yes	Yes	T4,T5,T7	Yes	T4,T5,T7	INPUT
otp_en_sram_ifetch_i[7:0]	Yes	Yes	T4,T5,T7	Yes	T4,T5,T7	INPUT
sram_otp_key_o.req	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
sram_otp_key_i.seed_valid	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	INPUT
sram_otp_key_i.nonce[127:0]	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	INPUT
sram_otp_key_i.key[127:0]	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	INPUT
sram_otp_key_i.ack	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
cfg_i.rf_cfg.cfg[3:0]	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	INPUT
cfg_i.rf_cfg.cfg_en	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	INPUT
cfg_i.rf_cfg.test	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	INPUT
cfg_i.ram_cfg.cfg[3:0]	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	INPUT
cfg_i.ram_cfg.cfg_en	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	INPUT
cfg_i.ram_cfg.test	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	INPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
Branches		24	24	100.00
TERNARY	226	3	3	100.00
TERNARY	284	3	3	100.00
TERNARY	293	2	2	100.00
TERNARY	516	2	2	100.00
TERNARY	517	2	2	100.00
TERNARY	518	2	2	100.00
TERNARY	529	3	3	100.00
IF	230	2	2	100.00
IF	302	5	5	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv' or '../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	226	(init_done) ? 
-2-:	226	(init_trig) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T4
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	284	(key_req) ? 
-2-:	284	(key_ack) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T4
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	293	((key_ack & (~local_esc))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	516	(init_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	517	(init_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	518	(init_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	529	(key_req_pending_q) ? 
-2-:	529	(reg2hw.status.escalated.q) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T4
0	1	Covered	T6,T7,T8
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	230	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	302	if ((!rst_ni))
-2-:	310	if (key_ack)
-3-:	317	if (local_esc)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	-	Covered	T1,T2,T3
0	-	1	Covered	T6,T7,T8
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	12	70.59
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	12	70.59

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertOutKnown_A	316651429	316547296	0	0
FpvSecCmCntCheck_A	316651429	80	0	0
FpvSecCmLcGateFsmCheck_A	316651429	0	0	0
FpvSecCmRegWeOnehotCheck_A	316651429	80	0	0
FpvSecCmReqFifoRptrCheck_A	316651429	0	0	0
FpvSecCmReqFifoWptrCheck_A	316651429	0	0	0
FpvSecCmRspFifoRptrCheck_A	316651429	80	0	0
FpvSecCmRspFifoWptrCheck_A	316651429	80	0	0
FpvSecCmSramReqFifoRptrCheck_A	316651429	0	0	0
FpvSecCmSramReqFifoWptrCheck_A	316651429	0	0	0
NonceWidthsLessThanSource_A	891	891	0	0
RamTlOutKnown_A	316651429	316547296	0	0
RamTlOutPayLoadKnown_A	316651429	139519501	0	0
RamTlOutPayLoadKnown_AKnownEnable	316651429	316547296	0	0
RegsTlOutKnown_A	316651429	316547296	0	0
SramOtpKeyKnown_A	316651429	316547296	0	0
TlulGntIsCorrect_A	316651429	62870418	0	0

AlertOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316651429	316547296	0	0
T1	11164	11082	0	0
T2	1306	1242	0	0
T3	14515	14453	0	0
T4	163766	163697	0	0
T5	784616	784514	0	0
T9	879	825	0	0
T10	2046	1983	0	0
T11	275154	275075	0	0
T12	262323	262270	0	0
T13	226205	226139	0	0

FpvSecCmCntCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316651429	80	0	0
T14	21519	20	0	0
T15	0	20	0	0
T16	0	20	0	0
T27	0	10	0	0
T28	0	10	0	0
T29	519669	0	0	0
T30	3249	0	0	0
T31	89221	0	0	0
T32	8053	0	0	0
T33	25522	0	0	0
T34	12248	0	0	0
T35	47226	0	0	0
T36	310254	0	0	0
T37	28519	0	0	0

FpvSecCmLcGateFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316651429	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316651429	80	0	0
T14	21519	20	0	0
T15	0	20	0	0
T16	0	20	0	0
T27	0	10	0	0
T28	0	10	0	0
T29	519669	0	0	0
T30	3249	0	0	0
T31	89221	0	0	0
T32	8053	0	0	0
T33	25522	0	0	0
T34	12248	0	0	0
T35	47226	0	0	0
T36	310254	0	0	0
T37	28519	0	0	0

FpvSecCmReqFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316651429	0	0	0

FpvSecCmReqFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316651429	0	0	0

FpvSecCmRspFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316651429	80	0	0
T14	21519	20	0	0
T15	0	20	0	0
T16	0	20	0	0
T27	0	10	0	0
T28	0	10	0	0
T29	519669	0	0	0
T30	3249	0	0	0
T31	89221	0	0	0
T32	8053	0	0	0
T33	25522	0	0	0
T34	12248	0	0	0
T35	47226	0	0	0
T36	310254	0	0	0
T37	28519	0	0	0

FpvSecCmRspFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316651429	80	0	0
T14	21519	20	0	0
T15	0	20	0	0
T16	0	20	0	0
T27	0	10	0	0
T28	0	10	0	0
T29	519669	0	0	0
T30	3249	0	0	0
T31	89221	0	0	0
T32	8053	0	0	0
T33	25522	0	0	0
T34	12248	0	0	0
T35	47226	0	0	0
T36	310254	0	0	0
T37	28519	0	0	0

FpvSecCmSramReqFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316651429	0	0	0

FpvSecCmSramReqFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316651429	0	0	0

NonceWidthsLessThanSource_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	891	891	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

RamTlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316651429	316547296	0	0
T1	11164	11082	0	0
T2	1306	1242	0	0
T3	14515	14453	0	0
T4	163766	163697	0	0
T5	784616	784514	0	0
T9	879	825	0	0
T10	2046	1983	0	0
T11	275154	275075	0	0
T12	262323	262270	0	0
T13	226205	226139	0	0

RamTlOutPayLoadKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316651429	139519501	0	0
T1	11164	6890	0	0
T2	1306	0	0	0
T3	14515	5448	0	0
T4	163766	100630	0	0
T5	784616	498578	0	0
T9	879	0	0	0
T10	2046	0	0	0
T11	275154	38912	0	0
T12	262323	215571	0	0
T13	226205	182674	0	0
T19	0	9602	0	0
T38	0	9547	0	0
T39	0	9349	0	0

RamTlOutPayLoadKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	316651429	316547296	0	0
T1	11164	11082	0	0
T2	1306	1242	0	0
T3	14515	14453	0	0
T4	163766	163697	0	0
T5	784616	784514	0	0
T9	879	825	0	0
T10	2046	1983	0	0
T11	275154	275075	0	0
T12	262323	262270	0	0
T13	226205	226139	0	0

RegsTlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316651429	316547296	0	0
T1	11164	11082	0	0
T2	1306	1242	0	0
T3	14515	14453	0	0
T4	163766	163697	0	0
T5	784616	784514	0	0
T9	879	825	0	0
T10	2046	1983	0	0
T11	275154	275075	0	0
T12	262323	262270	0	0
T13	226205	226139	0	0

SramOtpKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316651429	316547296	0	0
T1	11164	11082	0	0
T2	1306	1242	0	0
T3	14515	14453	0	0
T4	163766	163697	0	0
T5	784616	784514	0	0
T9	879	825	0	0
T10	2046	1983	0	0
T11	275154	275075	0	0
T12	262323	262270	0	0
T13	226205	226139	0	0

TlulGntIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316651429	62870418	0	0
T1	11164	6890	0	0
T2	1306	0	0	0
T3	14515	3076	0	0
T4	163766	42133	0	0
T5	784616	239718	0	0
T9	879	0	0	0
T10	2046	0	0	0
T11	275154	38912	0	0
T12	262323	225454	0	0
T13	226205	190862	0	0
T19	0	10498	0	0
T38	0	9547	0	0
T39	0	13245	0	0