Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	318040430	173374	0	0
ctrl_regwen_rd_A	318040430	4182	0	0
exec_rd_A	318040430	4071	0	0
exec_regwen_rd_A	318040430	3908	0	0
readback_rd_A	318040430	2343	0	0
readback_regwen_rd_A	318040430	2044	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318040430	173374	0	0
T21	131809	3607	0	0
T22	83321	1210	0	0
T23	0	6028	0	0
T41	168545	0	0	0
T42	505957	0	0	0
T43	287836	0	0	0
T45	796841	0	0	0
T46	0	3612	0	0
T47	0	6582	0	0
T54	0	5582	0	0
T56	0	2148	0	0
T57	15205	0	0	0
T58	142263	0	0	0
T59	15890	0	0	0
T60	6443	0	0	0
T62	0	1510	0	0
T72	0	3602	0	0
T73	0	6805	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318040430	4182	0	0
T21	131809	216	0	0
T22	83321	169	0	0
T41	168545	0	0	0
T42	505957	0	0	0
T43	287836	0	0	0
T45	796841	0	0	0
T47	0	577	0	0
T48	0	186	0	0
T57	15205	0	0	0
T58	142263	0	0	0
T59	15890	0	0	0
T60	6443	0	0	0
T72	0	123	0	0
T113	0	231	0	0
T114	0	28	0	0
T115	0	163	0	0
T116	0	40	0	0
T117	0	157	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318040430	4071	0	0
T21	131809	247	0	0
T22	83321	105	0	0
T41	168545	0	0	0
T42	505957	0	0	0
T43	287836	0	0	0
T45	796841	0	0	0
T47	0	487	0	0
T48	0	108	0	0
T57	15205	0	0	0
T58	142263	0	0	0
T59	15890	0	0	0
T60	6443	0	0	0
T72	0	145	0	0
T113	0	220	0	0
T114	0	53	0	0
T115	0	198	0	0
T116	0	101	0	0
T117	0	178	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318040430	3908	0	0
T21	131809	185	0	0
T22	83321	133	0	0
T41	168545	0	0	0
T42	505957	0	0	0
T43	287836	0	0	0
T45	796841	0	0	0
T47	0	485	0	0
T48	0	148	0	0
T57	15205	0	0	0
T58	142263	0	0	0
T59	15890	0	0	0
T60	6443	0	0	0
T72	0	137	0	0
T113	0	180	0	0
T114	0	68	0	0
T115	0	178	0	0
T116	0	54	0	0
T117	0	176	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318040430	2343	0	0
T21	131809	245	0	0
T22	83321	175	0	0
T41	168545	0	0	0
T42	505957	0	0	0
T43	287836	0	0	0
T45	796841	0	0	0
T47	0	373	0	0
T48	0	140	0	0
T57	15205	0	0	0
T58	142263	0	0	0
T59	15890	0	0	0
T60	6443	0	0	0
T72	0	115	0	0
T113	0	201	0	0
T114	0	36	0	0
T115	0	263	0	0
T116	0	12	0	0
T117	0	124	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318040430	2044	0	0
T21	131809	291	0	0
T22	83321	85	0	0
T41	168545	0	0	0
T42	505957	0	0	0
T43	287836	0	0	0
T45	796841	0	0	0
T47	0	390	0	0
T48	0	107	0	0
T57	15205	0	0	0
T58	142263	0	0	0
T59	15890	0	0	0
T60	6443	0	0	0
T72	0	110	0	0
T113	0	173	0	0
T114	0	36	0	0
T115	0	146	0	0
T116	0	66	0	0
T117	0	112	0	0