| T324 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_partial_access.871750695 |
|
|
Aug 25 08:14:01 AM UTC 24 |
Aug 25 08:14:17 AM UTC 24 |
1086445471 ps |
| T325 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_max_throughput.681319132 |
|
|
Aug 25 08:14:18 AM UTC 24 |
Aug 25 08:14:22 AM UTC 24 |
46314450 ps |
| T158 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_executable.1789892618 |
|
|
Aug 25 08:04:13 AM UTC 24 |
Aug 25 08:14:28 AM UTC 24 |
1723199874 ps |
| T326 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_lc_escalation.1388148884 |
|
|
Aug 25 08:14:29 AM UTC 24 |
Aug 25 08:14:37 AM UTC 24 |
1237922335 ps |
| T327 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_bijection.1013485738 |
|
|
Aug 25 08:13:48 AM UTC 24 |
Aug 25 08:14:41 AM UTC 24 |
2288516035 ps |
| T328 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_pipeline.2803094446 |
|
|
Aug 25 08:08:26 AM UTC 24 |
Aug 25 08:14:42 AM UTC 24 |
18090423477 ps |
| T151 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_regwen.2537266092 |
|
|
Aug 25 08:01:45 AM UTC 24 |
Aug 25 08:14:45 AM UTC 24 |
24982450610 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_ram_cfg.1793645442 |
|
|
Aug 25 08:14:46 AM UTC 24 |
Aug 25 08:14:48 AM UTC 24 |
28819252 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_executable.3947563438 |
|
|
Aug 25 07:59:44 AM UTC 24 |
Aug 25 08:14:58 AM UTC 24 |
6415007025 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_mem_walk.4206582871 |
|
|
Aug 25 08:14:49 AM UTC 24 |
Aug 25 08:14:59 AM UTC 24 |
356199877 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_mem_partial_access.1672679877 |
|
|
Aug 25 08:14:59 AM UTC 24 |
Aug 25 08:15:04 AM UTC 24 |
94115514 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_throughput_w_partial_write.477462365 |
|
|
Aug 25 08:14:23 AM UTC 24 |
Aug 25 08:15:15 AM UTC 24 |
254576789 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_alert_test.792137430 |
|
|
Aug 25 08:15:16 AM UTC 24 |
Aug 25 08:15:18 AM UTC 24 |
14288253 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_executable.2212329841 |
|
|
Aug 25 08:07:33 AM UTC 24 |
Aug 25 08:15:24 AM UTC 24 |
2044782977 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_smoke.3485709185 |
|
|
Aug 25 08:15:19 AM UTC 24 |
Aug 25 08:15:27 AM UTC 24 |
248981647 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_executable.1563114645 |
|
|
Aug 25 07:52:21 AM UTC 24 |
Aug 25 08:16:01 AM UTC 24 |
22587902202 ps |
| T338 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.3896917692 |
|
|
Aug 25 08:13:22 AM UTC 24 |
Aug 25 08:16:09 AM UTC 24 |
869038105 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_regwen.746353561 |
|
|
Aug 25 08:04:25 AM UTC 24 |
Aug 25 08:16:13 AM UTC 24 |
29102034165 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_bijection.2741615919 |
|
|
Aug 25 08:15:27 AM UTC 24 |
Aug 25 08:17:03 AM UTC 24 |
8279197917 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_regwen.1934808654 |
|
|
Aug 25 08:13:06 AM UTC 24 |
Aug 25 08:17:21 AM UTC 24 |
538056306 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_regwen.3525661361 |
|
|
Aug 25 07:55:35 AM UTC 24 |
Aug 25 08:17:24 AM UTC 24 |
13566705785 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_lc_escalation.1901776402 |
|
|
Aug 25 08:17:22 AM UTC 24 |
Aug 25 08:17:31 AM UTC 24 |
1923317288 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_pipeline.1159227699 |
|
|
Aug 25 08:13:51 AM UTC 24 |
Aug 25 08:17:32 AM UTC 24 |
3276341996 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_ram_cfg.3372187498 |
|
|
Aug 25 08:17:40 AM UTC 24 |
Aug 25 08:17:42 AM UTC 24 |
28016942 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_partial_access_b2b.364506105 |
|
|
Aug 25 08:10:54 AM UTC 24 |
Aug 25 08:17:48 AM UTC 24 |
39418593721 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_max_throughput.1269185838 |
|
|
Aug 25 08:16:14 AM UTC 24 |
Aug 25 08:17:48 AM UTC 24 |
544565767 ps |
| T159 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_executable.1413430382 |
|
|
Aug 25 08:09:11 AM UTC 24 |
Aug 25 08:17:50 AM UTC 24 |
12311869053 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_partial_access.645681720 |
|
|
Aug 25 08:16:02 AM UTC 24 |
Aug 25 08:17:56 AM UTC 24 |
397677616 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_throughput_w_partial_write.798845987 |
|
|
Aug 25 08:17:04 AM UTC 24 |
Aug 25 08:17:57 AM UTC 24 |
117204278 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_mem_partial_access.784071177 |
|
|
Aug 25 08:17:49 AM UTC 24 |
Aug 25 08:17:58 AM UTC 24 |
100362284 ps |
| T351 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_alert_test.889941155 |
|
|
Aug 25 08:17:56 AM UTC 24 |
Aug 25 08:17:58 AM UTC 24 |
33154650 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_pipeline.2692308625 |
|
|
Aug 25 08:10:26 AM UTC 24 |
Aug 25 08:18:00 AM UTC 24 |
31374630113 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_mem_walk.574997512 |
|
|
Aug 25 08:17:43 AM UTC 24 |
Aug 25 08:18:00 AM UTC 24 |
689673953 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_partial_access.3124986496 |
|
|
Aug 25 08:18:05 AM UTC 24 |
Aug 25 08:18:18 AM UTC 24 |
417473177 ps |
| T43 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.3388917786 |
|
|
Aug 25 08:15:00 AM UTC 24 |
Aug 25 08:18:26 AM UTC 24 |
6915574936 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_executable.594958615 |
|
|
Aug 25 08:01:33 AM UTC 24 |
Aug 25 08:18:27 AM UTC 24 |
11232163395 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_bijection.2733727734 |
|
|
Aug 25 08:18:05 AM UTC 24 |
Aug 25 08:18:34 AM UTC 24 |
354442870 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_multiple_keys.3302318979 |
|
|
Aug 25 08:04:56 AM UTC 24 |
Aug 25 08:18:37 AM UTC 24 |
3698542531 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_lc_escalation.1313574756 |
|
|
Aug 25 08:18:26 AM UTC 24 |
Aug 25 08:18:37 AM UTC 24 |
455424901 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_ram_cfg.1701358830 |
|
|
Aug 25 08:18:38 AM UTC 24 |
Aug 25 08:18:40 AM UTC 24 |
29455826 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_mem_walk.3185667924 |
|
|
Aug 25 08:18:41 AM UTC 24 |
Aug 25 08:18:49 AM UTC 24 |
464217484 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_mem_partial_access.3468217710 |
|
|
Aug 25 08:18:50 AM UTC 24 |
Aug 25 08:19:02 AM UTC 24 |
3822503674 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_regwen.4219561617 |
|
|
Aug 25 07:59:47 AM UTC 24 |
Aug 25 08:19:12 AM UTC 24 |
21318586235 ps |
| T160 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_all.2563466983 |
|
|
Aug 25 07:52:21 AM UTC 24 |
Aug 25 08:19:14 AM UTC 24 |
21238731818 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_pipeline.1614770678 |
|
|
Aug 25 08:12:02 AM UTC 24 |
Aug 25 08:19:17 AM UTC 24 |
14263358462 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_alert_test.1290349141 |
|
|
Aug 25 08:19:15 AM UTC 24 |
Aug 25 08:19:17 AM UTC 24 |
43476709 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.2990264409 |
|
|
Aug 25 07:57:29 AM UTC 24 |
Aug 25 08:19:23 AM UTC 24 |
21671049534 ps |
| T44 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.1273648426 |
|
|
Aug 25 08:19:03 AM UTC 24 |
Aug 25 08:19:31 AM UTC 24 |
2605994018 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_multiple_keys.182269814 |
|
|
Aug 25 07:52:32 AM UTC 24 |
Aug 25 08:19:33 AM UTC 24 |
67904061178 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_partial_access.707071418 |
|
|
Aug 25 08:19:34 AM UTC 24 |
Aug 25 08:19:37 AM UTC 24 |
63341049 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_throughput_w_partial_write.3692969846 |
|
|
Aug 25 08:18:18 AM UTC 24 |
Aug 25 08:19:46 AM UTC 24 |
295825003 ps |
| T128 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_bijection.2485734092 |
|
|
Aug 25 08:19:25 AM UTC 24 |
Aug 25 08:19:51 AM UTC 24 |
923543321 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.1970071513 |
|
|
Aug 25 08:09:22 AM UTC 24 |
Aug 25 08:19:57 AM UTC 24 |
2744922195 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_max_throughput.4179980319 |
|
|
Aug 25 08:19:47 AM UTC 24 |
Aug 25 08:19:58 AM UTC 24 |
58032770 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.847677443 |
|
|
Aug 25 08:17:49 AM UTC 24 |
Aug 25 08:20:00 AM UTC 24 |
2602107477 ps |
| T132 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_max_throughput.1085133993 |
|
|
Aug 25 08:18:11 AM UTC 24 |
Aug 25 08:20:12 AM UTC 24 |
520884506 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_lc_escalation.3451557563 |
|
|
Aug 25 08:19:57 AM UTC 24 |
Aug 25 08:20:14 AM UTC 24 |
3463775541 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_ram_cfg.741849245 |
|
|
Aug 25 08:20:15 AM UTC 24 |
Aug 25 08:20:17 AM UTC 24 |
60546729 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_mem_walk.2314120252 |
|
|
Aug 25 08:20:18 AM UTC 24 |
Aug 25 08:20:33 AM UTC 24 |
5532397001 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_partial_access_b2b.1734285470 |
|
|
Aug 25 08:12:35 AM UTC 24 |
Aug 25 08:20:39 AM UTC 24 |
16625490502 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_mem_partial_access.255256584 |
|
|
Aug 25 08:20:34 AM UTC 24 |
Aug 25 08:20:43 AM UTC 24 |
585587424 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_multiple_keys.460853820 |
|
|
Aug 25 08:11:58 AM UTC 24 |
Aug 25 08:20:56 AM UTC 24 |
8847827434 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_alert_test.1165970760 |
|
|
Aug 25 08:20:59 AM UTC 24 |
Aug 25 08:21:01 AM UTC 24 |
46208315 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.1893124187 |
|
|
Aug 25 08:20:39 AM UTC 24 |
Aug 25 08:21:10 AM UTC 24 |
666345586 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.1322256091 |
|
|
Aug 25 07:55:58 AM UTC 24 |
Aug 25 08:21:13 AM UTC 24 |
22520171347 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_smoke.2987092919 |
|
|
Aug 25 08:21:00 AM UTC 24 |
Aug 25 08:21:15 AM UTC 24 |
409658500 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_smoke.271539000 |
|
|
Aug 25 08:19:17 AM UTC 24 |
Aug 25 08:21:18 AM UTC 24 |
615121155 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_access_during_key_req.2722384723 |
|
|
Aug 25 08:05:43 AM UTC 24 |
Aug 25 08:21:18 AM UTC 24 |
17484188693 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_throughput_w_partial_write.2170592873 |
|
|
Aug 25 08:19:51 AM UTC 24 |
Aug 25 08:21:38 AM UTC 24 |
307984706 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_throughput_w_partial_write.14408433 |
|
|
Aug 25 08:21:38 AM UTC 24 |
Aug 25 08:21:42 AM UTC 24 |
47211985 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_max_throughput.1671480718 |
|
|
Aug 25 08:21:19 AM UTC 24 |
Aug 25 08:21:53 AM UTC 24 |
289411147 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_lc_escalation.3595513607 |
|
|
Aug 25 08:21:44 AM UTC 24 |
Aug 25 08:21:57 AM UTC 24 |
3492297730 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_multiple_keys.3566169449 |
|
|
Aug 25 08:03:00 AM UTC 24 |
Aug 25 08:21:57 AM UTC 24 |
25754906137 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_bijection.3177041265 |
|
|
Aug 25 08:21:11 AM UTC 24 |
Aug 25 08:22:01 AM UTC 24 |
1930563987 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_ram_cfg.1835351786 |
|
|
Aug 25 08:22:02 AM UTC 24 |
Aug 25 08:22:04 AM UTC 24 |
28307368 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_executable.4046694808 |
|
|
Aug 25 07:54:16 AM UTC 24 |
Aug 25 08:22:07 AM UTC 24 |
22396901439 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_regwen.710542629 |
|
|
Aug 25 07:56:48 AM UTC 24 |
Aug 25 08:22:13 AM UTC 24 |
68697223394 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_mem_partial_access.3871280970 |
|
|
Aug 25 08:22:08 AM UTC 24 |
Aug 25 08:22:14 AM UTC 24 |
380796755 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_mem_walk.2818729192 |
|
|
Aug 25 08:22:05 AM UTC 24 |
Aug 25 08:22:19 AM UTC 24 |
862307614 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_alert_test.1274957654 |
|
|
Aug 25 08:22:20 AM UTC 24 |
Aug 25 08:22:22 AM UTC 24 |
83712392 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_partial_access_b2b.1086265404 |
|
|
Aug 25 08:16:10 AM UTC 24 |
Aug 25 08:22:40 AM UTC 24 |
13110138848 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_partial_access.2880309481 |
|
|
Aug 25 08:21:16 AM UTC 24 |
Aug 25 08:22:52 AM UTC 24 |
895149363 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_all.2105494924 |
|
|
Aug 25 07:53:48 AM UTC 24 |
Aug 25 08:23:00 AM UTC 24 |
29902653517 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_pipeline.1522801457 |
|
|
Aug 25 08:15:56 AM UTC 24 |
Aug 25 08:23:09 AM UTC 24 |
20768319531 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_executable.1744007061 |
|
|
Aug 25 08:14:41 AM UTC 24 |
Aug 25 08:23:25 AM UTC 24 |
12372603431 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_access_during_key_req.425786568 |
|
|
Aug 25 08:07:33 AM UTC 24 |
Aug 25 08:23:32 AM UTC 24 |
12187562393 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_max_throughput.1644104477 |
|
|
Aug 25 08:23:33 AM UTC 24 |
Aug 25 08:23:41 AM UTC 24 |
54003142 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_regwen.3079970573 |
|
|
Aug 25 08:14:43 AM UTC 24 |
Aug 25 08:23:46 AM UTC 24 |
1601955626 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_throughput_w_partial_write.185624778 |
|
|
Aug 25 08:23:42 AM UTC 24 |
Aug 25 08:23:47 AM UTC 24 |
54321007 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_partial_access_b2b.1691755741 |
|
|
Aug 25 08:14:01 AM UTC 24 |
Aug 25 08:23:48 AM UTC 24 |
74199062814 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_regwen.3843096798 |
|
|
Aug 25 08:05:47 AM UTC 24 |
Aug 25 08:23:48 AM UTC 24 |
57216994278 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_partial_access.2871580862 |
|
|
Aug 25 08:23:09 AM UTC 24 |
Aug 25 08:23:49 AM UTC 24 |
760666645 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_ram_cfg.3462592389 |
|
|
Aug 25 08:23:50 AM UTC 24 |
Aug 25 08:23:52 AM UTC 24 |
79051514 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_bijection.1984588963 |
|
|
Aug 25 08:22:53 AM UTC 24 |
Aug 25 08:23:55 AM UTC 24 |
2864500375 ps |
| T403 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_lc_escalation.2326640318 |
|
|
Aug 25 08:23:47 AM UTC 24 |
Aug 25 08:23:58 AM UTC 24 |
1806157292 ps |
| T404 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_smoke.389830801 |
|
|
Aug 25 08:22:23 AM UTC 24 |
Aug 25 08:24:00 AM UTC 24 |
2962078860 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_pipeline.2837321127 |
|
|
Aug 25 08:18:05 AM UTC 24 |
Aug 25 08:24:00 AM UTC 24 |
5279091182 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_mem_walk.3990177723 |
|
|
Aug 25 08:23:53 AM UTC 24 |
Aug 25 08:24:02 AM UTC 24 |
242439328 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_mem_partial_access.845067619 |
|
|
Aug 25 08:23:56 AM UTC 24 |
Aug 25 08:24:02 AM UTC 24 |
758571812 ps |
| T408 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_regwen.106134467 |
|
|
Aug 25 08:07:33 AM UTC 24 |
Aug 25 08:24:02 AM UTC 24 |
17305425609 ps |
| T409 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_alert_test.1726786656 |
|
|
Aug 25 08:24:01 AM UTC 24 |
Aug 25 08:24:03 AM UTC 24 |
12903260 ps |
| T410 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_partial_access_b2b.2933293671 |
|
|
Aug 25 08:18:05 AM UTC 24 |
Aug 25 08:24:25 AM UTC 24 |
7430503759 ps |
| T411 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_partial_access.1380741008 |
|
|
Aug 25 08:24:25 AM UTC 24 |
Aug 25 08:24:30 AM UTC 24 |
86055638 ps |
| T412 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_smoke.3953488683 |
|
|
Aug 25 08:24:03 AM UTC 24 |
Aug 25 08:24:55 AM UTC 24 |
470389569 ps |
| T413 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_max_throughput.753728940 |
|
|
Aug 25 08:24:57 AM UTC 24 |
Aug 25 08:25:00 AM UTC 24 |
67614398 ps |
| T414 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_throughput_w_partial_write.3187587501 |
|
|
Aug 25 08:24:58 AM UTC 24 |
Aug 25 08:25:05 AM UTC 24 |
201132389 ps |
| T415 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_bijection.271280459 |
|
|
Aug 25 08:24:03 AM UTC 24 |
Aug 25 08:25:07 AM UTC 24 |
1434587000 ps |
| T416 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_lc_escalation.1611498854 |
|
|
Aug 25 08:25:01 AM UTC 24 |
Aug 25 08:25:10 AM UTC 24 |
1137521441 ps |
| T417 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_pipeline.3451436760 |
|
|
Aug 25 08:21:14 AM UTC 24 |
Aug 25 08:25:21 AM UTC 24 |
2125037475 ps |
| T418 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_ram_cfg.1467900685 |
|
|
Aug 25 08:25:21 AM UTC 24 |
Aug 25 08:25:24 AM UTC 24 |
52945296 ps |
| T154 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all.3233244814 |
|
|
Aug 25 07:58:36 AM UTC 24 |
Aug 25 08:25:37 AM UTC 24 |
10140241985 ps |
| T419 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_mem_walk.793969488 |
|
|
Aug 25 08:25:25 AM UTC 24 |
Aug 25 08:25:41 AM UTC 24 |
1926193418 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_mem_partial_access.4256106448 |
|
|
Aug 25 08:25:39 AM UTC 24 |
Aug 25 08:25:45 AM UTC 24 |
111474158 ps |
| T421 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_partial_access_b2b.1470467302 |
|
|
Aug 25 08:21:18 AM UTC 24 |
Aug 25 08:25:57 AM UTC 24 |
11594136364 ps |
| T422 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_alert_test.716820549 |
|
|
Aug 25 08:25:58 AM UTC 24 |
Aug 25 08:26:00 AM UTC 24 |
23135289 ps |
| T155 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_executable.746991694 |
|
|
Aug 25 07:52:47 AM UTC 24 |
Aug 25 08:26:04 AM UTC 24 |
23138708953 ps |
| T45 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.628795531 |
|
|
Aug 25 08:25:43 AM UTC 24 |
Aug 25 08:26:08 AM UTC 24 |
1619942164 ps |
| T423 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_executable.3441195529 |
|
|
Aug 25 08:05:44 AM UTC 24 |
Aug 25 08:26:14 AM UTC 24 |
52322354453 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_smoke.255225392 |
|
|
Aug 25 08:26:01 AM UTC 24 |
Aug 25 08:26:30 AM UTC 24 |
15533251763 ps |
| T425 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_pipeline.918062601 |
|
|
Aug 25 08:19:32 AM UTC 24 |
Aug 25 08:26:47 AM UTC 24 |
13562177486 ps |
| T426 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_partial_access.703970337 |
|
|
Aug 25 08:26:24 AM UTC 24 |
Aug 25 08:26:49 AM UTC 24 |
588951428 ps |
| T427 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_max_throughput.3452933698 |
|
|
Aug 25 08:26:48 AM UTC 24 |
Aug 25 08:26:58 AM UTC 24 |
172185822 ps |
| T156 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_regwen.3678530298 |
|
|
Aug 25 07:58:17 AM UTC 24 |
Aug 25 08:27:00 AM UTC 24 |
135047988304 ps |
| T428 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_throughput_w_partial_write.1916320005 |
|
|
Aug 25 08:26:49 AM UTC 24 |
Aug 25 08:27:05 AM UTC 24 |
175517119 ps |
| T429 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_regwen.3820796880 |
|
|
Aug 25 08:25:11 AM UTC 24 |
Aug 25 08:27:14 AM UTC 24 |
2337251670 ps |
| T430 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_lc_escalation.1370907797 |
|
|
Aug 25 08:26:59 AM UTC 24 |
Aug 25 08:27:16 AM UTC 24 |
10986109305 ps |
| T431 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_ram_cfg.3353803901 |
|
|
Aug 25 08:27:17 AM UTC 24 |
Aug 25 08:27:19 AM UTC 24 |
32553150 ps |
| T432 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_pipeline.1473565743 |
|
|
Aug 25 08:24:04 AM UTC 24 |
Aug 25 08:27:24 AM UTC 24 |
1497678607 ps |
| T433 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_bijection.2326150850 |
|
|
Aug 25 08:26:09 AM UTC 24 |
Aug 25 08:27:28 AM UTC 24 |
1788512628 ps |
| T434 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_mem_partial_access.1162007737 |
|
|
Aug 25 08:27:26 AM UTC 24 |
Aug 25 08:27:31 AM UTC 24 |
387755885 ps |
| T435 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_mem_walk.1538809386 |
|
|
Aug 25 08:27:20 AM UTC 24 |
Aug 25 08:27:32 AM UTC 24 |
140656112 ps |
| T436 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_smoke.148074395 |
|
|
Aug 25 08:27:36 AM UTC 24 |
Aug 25 08:27:47 AM UTC 24 |
197896645 ps |
| T437 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_alert_test.268162359 |
|
|
Aug 25 08:27:33 AM UTC 24 |
Aug 25 08:27:35 AM UTC 24 |
14032072 ps |
| T438 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.4040205024 |
|
|
Aug 25 08:06:25 AM UTC 24 |
Aug 25 08:27:52 AM UTC 24 |
9133738024 ps |
| T439 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_executable.4060246884 |
|
|
Aug 25 08:20:01 AM UTC 24 |
Aug 25 08:28:30 AM UTC 24 |
13587215031 ps |
| T440 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.2033645319 |
|
|
Aug 25 08:22:14 AM UTC 24 |
Aug 25 08:28:43 AM UTC 24 |
3109130315 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_access_during_key_req.47581698 |
|
|
Aug 25 08:11:10 AM UTC 24 |
Aug 25 08:28:44 AM UTC 24 |
6126785019 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_access_during_key_req.1794576799 |
|
|
Aug 25 08:13:00 AM UTC 24 |
Aug 25 08:28:53 AM UTC 24 |
3273561250 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_partial_access.901262751 |
|
|
Aug 25 08:28:44 AM UTC 24 |
Aug 25 08:29:02 AM UTC 24 |
2017481452 ps |
| T444 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_bijection.985024797 |
|
|
Aug 25 08:27:53 AM UTC 24 |
Aug 25 08:29:08 AM UTC 24 |
1963004524 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_throughput_w_partial_write.1889376708 |
|
|
Aug 25 08:29:02 AM UTC 24 |
Aug 25 08:29:11 AM UTC 24 |
227663090 ps |
| T446 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.2960822116 |
|
|
Aug 25 08:08:05 AM UTC 24 |
Aug 25 08:29:20 AM UTC 24 |
18820813837 ps |
| T447 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_lc_escalation.3173589969 |
|
|
Aug 25 08:29:09 AM UTC 24 |
Aug 25 08:29:22 AM UTC 24 |
808194253 ps |
| T448 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_max_throughput.2521646444 |
|
|
Aug 25 08:28:55 AM UTC 24 |
Aug 25 08:29:23 AM UTC 24 |
78156438 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.73683229 |
|
|
Aug 25 07:53:52 AM UTC 24 |
Aug 25 08:29:23 AM UTC 24 |
33295375663 ps |
| T450 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_access_during_key_req.1557300103 |
|
|
Aug 25 07:54:11 AM UTC 24 |
Aug 25 08:29:25 AM UTC 24 |
4078824800 ps |
| T451 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_ram_cfg.4078725010 |
|
|
Aug 25 08:29:24 AM UTC 24 |
Aug 25 08:29:26 AM UTC 24 |
105305097 ps |
| T452 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_pipeline.3737020245 |
|
|
Aug 25 08:23:01 AM UTC 24 |
Aug 25 08:29:29 AM UTC 24 |
3194690461 ps |
| T453 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_mem_partial_access.1267783260 |
|
|
Aug 25 08:29:26 AM UTC 24 |
Aug 25 08:29:31 AM UTC 24 |
175555037 ps |
| T454 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_mem_walk.870523681 |
|
|
Aug 25 08:29:24 AM UTC 24 |
Aug 25 08:29:33 AM UTC 24 |
454982372 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_alert_test.1402392056 |
|
|
Aug 25 08:29:32 AM UTC 24 |
Aug 25 08:29:34 AM UTC 24 |
99873359 ps |
| T456 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_regwen.1349935092 |
|
|
Aug 25 08:17:33 AM UTC 24 |
Aug 25 08:29:36 AM UTC 24 |
10391081307 ps |
| T457 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all.109132442 |
|
|
Aug 25 07:52:19 AM UTC 24 |
Aug 25 08:29:45 AM UTC 24 |
150672562556 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_executable.3166078324 |
|
|
Aug 25 08:27:05 AM UTC 24 |
Aug 25 08:29:50 AM UTC 24 |
2835069250 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_smoke.3796159031 |
|
|
Aug 25 08:29:33 AM UTC 24 |
Aug 25 08:29:55 AM UTC 24 |
3728180777 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_access_during_key_req.1666073934 |
|
|
Aug 25 08:17:25 AM UTC 24 |
Aug 25 08:30:10 AM UTC 24 |
2698548735 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_executable.3710100873 |
|
|
Aug 25 08:17:32 AM UTC 24 |
Aug 25 08:30:16 AM UTC 24 |
26312041221 ps |
| T462 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_all.3186809761 |
|
|
Aug 25 08:09:22 AM UTC 24 |
Aug 25 08:30:24 AM UTC 24 |
20584557686 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_lc_escalation.3416621502 |
|
|
Aug 25 08:30:25 AM UTC 24 |
Aug 25 08:30:31 AM UTC 24 |
935632720 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_partial_access_b2b.1259956312 |
|
|
Aug 25 08:19:38 AM UTC 24 |
Aug 25 08:30:33 AM UTC 24 |
23969767895 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_max_throughput.4291137965 |
|
|
Aug 25 08:30:11 AM UTC 24 |
Aug 25 08:30:48 AM UTC 24 |
100916837 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_partial_access_b2b.4218549207 |
|
|
Aug 25 08:23:26 AM UTC 24 |
Aug 25 08:30:50 AM UTC 24 |
4386838773 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_ram_cfg.76786356 |
|
|
Aug 25 08:30:51 AM UTC 24 |
Aug 25 08:30:53 AM UTC 24 |
40290220 ps |
| T468 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_throughput_w_partial_write.4156771771 |
|
|
Aug 25 08:30:17 AM UTC 24 |
Aug 25 08:30:55 AM UTC 24 |
102187418 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_mem_walk.2975850471 |
|
|
Aug 25 08:30:54 AM UTC 24 |
Aug 25 08:31:03 AM UTC 24 |
342491239 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_mem_partial_access.2745644387 |
|
|
Aug 25 08:30:55 AM UTC 24 |
Aug 25 08:31:04 AM UTC 24 |
182754993 ps |
| T471 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_access_during_key_req.2124045807 |
|
|
Aug 25 08:19:59 AM UTC 24 |
Aug 25 08:31:18 AM UTC 24 |
20932332469 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_alert_test.2336992930 |
|
|
Aug 25 08:31:19 AM UTC 24 |
Aug 25 08:31:21 AM UTC 24 |
79700663 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_bijection.1587235824 |
|
|
Aug 25 08:29:37 AM UTC 24 |
Aug 25 08:31:26 AM UTC 24 |
4687206301 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_access_during_key_req.2622682192 |
|
|
Aug 25 08:14:38 AM UTC 24 |
Aug 25 08:31:42 AM UTC 24 |
13036181822 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_access_during_key_req.3864685721 |
|
|
Aug 25 08:25:06 AM UTC 24 |
Aug 25 08:31:45 AM UTC 24 |
7809168205 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_multiple_keys.1632479544 |
|
|
Aug 25 08:13:46 AM UTC 24 |
Aug 25 08:31:55 AM UTC 24 |
10412323724 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_pipeline.3680254160 |
|
|
Aug 25 08:26:15 AM UTC 24 |
Aug 25 08:32:01 AM UTC 24 |
9339800507 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_executable.3866979895 |
|
|
Aug 25 08:13:00 AM UTC 24 |
Aug 25 08:32:06 AM UTC 24 |
21481349205 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_access_during_key_req.232291661 |
|
|
Aug 25 08:18:28 AM UTC 24 |
Aug 25 08:32:15 AM UTC 24 |
3716430941 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_partial_access.3641661584 |
|
|
Aug 25 08:29:51 AM UTC 24 |
Aug 25 08:32:16 AM UTC 24 |
448996731 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_lc_escalation.3894533716 |
|
|
Aug 25 08:32:17 AM UTC 24 |
Aug 25 08:32:22 AM UTC 24 |
387183270 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_bijection.942511814 |
|
|
Aug 25 08:31:43 AM UTC 24 |
Aug 25 08:32:35 AM UTC 24 |
2143291237 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_executable.1886007644 |
|
|
Aug 25 08:21:58 AM UTC 24 |
Aug 25 08:32:39 AM UTC 24 |
1100374470 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_throughput_w_partial_write.2745987106 |
|
|
Aug 25 08:32:16 AM UTC 24 |
Aug 25 08:32:51 AM UTC 24 |
366872951 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_ram_cfg.3836117172 |
|
|
Aug 25 08:32:52 AM UTC 24 |
Aug 25 08:32:55 AM UTC 24 |
139645400 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_partial_access.3713934820 |
|
|
Aug 25 08:31:55 AM UTC 24 |
Aug 25 08:33:08 AM UTC 24 |
1860058280 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_multiple_keys.3129860093 |
|
|
Aug 25 08:09:58 AM UTC 24 |
Aug 25 08:33:11 AM UTC 24 |
250421859951 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_mem_walk.3079876851 |
|
|
Aug 25 08:32:56 AM UTC 24 |
Aug 25 08:33:12 AM UTC 24 |
1928866703 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_mem_partial_access.1798350920 |
|
|
Aug 25 08:33:09 AM UTC 24 |
Aug 25 08:33:14 AM UTC 24 |
227666831 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_alert_test.3228006527 |
|
|
Aug 25 08:33:15 AM UTC 24 |
Aug 25 08:33:17 AM UTC 24 |
19332714 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_max_throughput.2737615265 |
|
|
Aug 25 08:32:08 AM UTC 24 |
Aug 25 08:33:30 AM UTC 24 |
502793992 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_smoke.2595594016 |
|
|
Aug 25 08:33:19 AM UTC 24 |
Aug 25 08:33:41 AM UTC 24 |
903754831 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_regwen.3695528748 |
|
|
Aug 25 08:09:11 AM UTC 24 |
Aug 25 08:33:49 AM UTC 24 |
18391094691 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_smoke.233503671 |
|
|
Aug 25 08:31:22 AM UTC 24 |
Aug 25 08:33:51 AM UTC 24 |
2588311773 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_pipeline.400353297 |
|
|
Aug 25 08:28:31 AM UTC 24 |
Aug 25 08:33:56 AM UTC 24 |
2579633294 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.4255230220 |
|
|
Aug 25 08:31:04 AM UTC 24 |
Aug 25 08:33:58 AM UTC 24 |
6454550103 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.793524824 |
|
|
Aug 25 08:29:27 AM UTC 24 |
Aug 25 08:34:04 AM UTC 24 |
3600212070 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_throughput_w_partial_write.270637231 |
|
|
Aug 25 08:34:05 AM UTC 24 |
Aug 25 08:34:16 AM UTC 24 |
253849004 ps |
| T46 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.2975977634 |
|
|
Aug 25 08:33:12 AM UTC 24 |
Aug 25 08:34:16 AM UTC 24 |
4174620773 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_lc_escalation.3452575709 |
|
|
Aug 25 08:34:17 AM UTC 24 |
Aug 25 08:34:28 AM UTC 24 |
619195233 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_executable.312456883 |
|
|
Aug 25 08:23:49 AM UTC 24 |
Aug 25 08:34:31 AM UTC 24 |
20315543687 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_regwen.571234028 |
|
|
Aug 25 08:20:13 AM UTC 24 |
Aug 25 08:34:41 AM UTC 24 |
7071622496 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_pipeline.3729161257 |
|
|
Aug 25 08:29:45 AM UTC 24 |
Aug 25 08:34:44 AM UTC 24 |
2920375399 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_ram_cfg.2343013831 |
|
|
Aug 25 08:34:42 AM UTC 24 |
Aug 25 08:34:44 AM UTC 24 |
87244124 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_mem_partial_access.275891992 |
|
|
Aug 25 08:34:45 AM UTC 24 |
Aug 25 08:34:51 AM UTC 24 |
346484210 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_mem_walk.3406810194 |
|
|
Aug 25 08:34:45 AM UTC 24 |
Aug 25 08:34:54 AM UTC 24 |
1497621377 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_partial_access_b2b.386761197 |
|
|
Aug 25 08:26:31 AM UTC 24 |
Aug 25 08:34:59 AM UTC 24 |
20261719133 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_alert_test.2375542511 |
|
|
Aug 25 08:35:01 AM UTC 24 |
Aug 25 08:35:02 AM UTC 24 |
28523917 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.2529551823 |
|
|
Aug 25 08:23:59 AM UTC 24 |
Aug 25 08:35:03 AM UTC 24 |
7839574902 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_multiple_keys.1949056742 |
|
|
Aug 25 08:22:41 AM UTC 24 |
Aug 25 08:35:17 AM UTC 24 |
16747767860 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_bijection.3321929195 |
|
|
Aug 25 08:33:42 AM UTC 24 |
Aug 25 08:35:19 AM UTC 24 |
12145119574 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_partial_access_b2b.140328347 |
|
|
Aug 25 08:29:56 AM UTC 24 |
Aug 25 08:35:21 AM UTC 24 |
11388488398 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_smoke.904488620 |
|
|
Aug 25 08:35:04 AM UTC 24 |
Aug 25 08:35:29 AM UTC 24 |
306169867 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_partial_access.3932574817 |
|
|
Aug 25 08:35:22 AM UTC 24 |
Aug 25 08:35:32 AM UTC 24 |
1426755777 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_max_throughput.1217132888 |
|
|
Aug 25 08:35:33 AM UTC 24 |
Aug 25 08:35:39 AM UTC 24 |
55805744 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_partial_access_b2b.1576404980 |
|
|
Aug 25 08:24:30 AM UTC 24 |
Aug 25 08:35:41 AM UTC 24 |
121524435765 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_lc_escalation.3778073862 |
|
|
Aug 25 08:35:42 AM UTC 24 |
Aug 25 08:35:53 AM UTC 24 |
674485541 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_max_throughput.1793895788 |
|
|
Aug 25 08:33:59 AM UTC 24 |
Aug 25 08:35:53 AM UTC 24 |
1288256578 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_partial_access.3790164043 |
|
|
Aug 25 08:33:52 AM UTC 24 |
Aug 25 08:36:01 AM UTC 24 |
696947278 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_multiple_keys.3692162560 |
|
|
Aug 25 08:19:18 AM UTC 24 |
Aug 25 08:36:14 AM UTC 24 |
131265325212 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_pipeline.1658857019 |
|
|
Aug 25 08:31:46 AM UTC 24 |
Aug 25 08:36:15 AM UTC 24 |
3749005266 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_ram_cfg.1949093035 |
|
|
Aug 25 08:36:15 AM UTC 24 |
Aug 25 08:36:18 AM UTC 24 |
31446833 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_mem_partial_access.2081508701 |
|
|
Aug 25 08:36:19 AM UTC 24 |
Aug 25 08:36:27 AM UTC 24 |
655028847 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_mem_walk.1050449142 |
|
|
Aug 25 08:36:17 AM UTC 24 |
Aug 25 08:36:28 AM UTC 24 |
232767317 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_throughput_w_partial_write.3249391134 |
|
|
Aug 25 08:35:40 AM UTC 24 |
Aug 25 08:36:31 AM UTC 24 |
117473980 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_alert_test.2028932259 |
|
|
Aug 25 08:36:32 AM UTC 24 |
Aug 25 08:36:34 AM UTC 24 |
35240854 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_all.2528667679 |
|
|
Aug 25 08:27:32 AM UTC 24 |
Aug 25 08:36:51 AM UTC 24 |
14834231097 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_partial_access_b2b.3607922342 |
|
|
Aug 25 08:28:45 AM UTC 24 |
Aug 25 08:36:56 AM UTC 24 |
55740413176 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_smoke.3784510097 |
|
|
Aug 25 08:36:35 AM UTC 24 |
Aug 25 08:36:57 AM UTC 24 |
1899349396 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_access_during_key_req.2166610119 |
|
|
Aug 25 08:21:54 AM UTC 24 |
Aug 25 08:37:04 AM UTC 24 |
16201058181 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_bijection.1688989424 |
|
|
Aug 25 08:35:18 AM UTC 24 |
Aug 25 08:37:06 AM UTC 24 |
3193693055 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_access_during_key_req.1037001405 |
|
|
Aug 25 08:23:48 AM UTC 24 |
Aug 25 08:37:30 AM UTC 24 |
5589468873 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.108964828 |
|
|
Aug 25 08:36:28 AM UTC 24 |
Aug 25 08:37:40 AM UTC 24 |
2081509257 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_regwen.1643990551 |
|
|
Aug 25 08:23:49 AM UTC 24 |
Aug 25 08:37:43 AM UTC 24 |
5845301021 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.1901058487 |
|
|
Aug 25 08:34:51 AM UTC 24 |
Aug 25 08:37:49 AM UTC 24 |
2215190572 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_throughput_w_partial_write.3007266834 |
|
|
Aug 25 08:37:40 AM UTC 24 |
Aug 25 08:37:49 AM UTC 24 |
433456524 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_lc_escalation.1095782876 |
|
|
Aug 25 08:37:45 AM UTC 24 |
Aug 25 08:37:50 AM UTC 24 |
378970734 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_executable.2806602739 |
|
|
Aug 25 08:25:08 AM UTC 24 |
Aug 25 08:37:57 AM UTC 24 |
18456324897 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_ram_cfg.1136384287 |
|
|
Aug 25 08:37:58 AM UTC 24 |
Aug 25 08:38:00 AM UTC 24 |
115846761 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.485093094 |
|
|
Aug 25 07:58:02 AM UTC 24 |
Aug 25 08:38:02 AM UTC 24 |
22637410481 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_mem_walk.1319515463 |
|
|
Aug 25 08:38:01 AM UTC 24 |
Aug 25 08:38:10 AM UTC 24 |
892813403 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_mem_partial_access.560534097 |
|
|
Aug 25 08:38:04 AM UTC 24 |
Aug 25 08:38:12 AM UTC 24 |
250883199 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_partial_access_b2b.766813846 |
|
|
Aug 25 08:32:02 AM UTC 24 |
Aug 25 08:38:21 AM UTC 24 |
36259939074 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_bijection.2249559747 |
|
|
Aug 25 08:36:57 AM UTC 24 |
Aug 25 08:38:22 AM UTC 24 |
22834863672 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_pipeline.2402596547 |
|
|
Aug 25 08:33:50 AM UTC 24 |
Aug 25 08:38:23 AM UTC 24 |
2107133656 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_alert_test.3888569761 |
|
|
Aug 25 08:38:22 AM UTC 24 |
Aug 25 08:38:24 AM UTC 24 |
14375956 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_partial_access.1632901989 |
|
|
Aug 25 08:37:05 AM UTC 24 |
Aug 25 08:38:26 AM UTC 24 |
3032928640 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_smoke.1711328025 |
|
|
Aug 25 08:38:23 AM UTC 24 |
Aug 25 08:38:30 AM UTC 24 |
47942907 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_regwen.1539683356 |
|
|
Aug 25 08:11:22 AM UTC 24 |
Aug 25 08:38:31 AM UTC 24 |
25838536577 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_partial_access.2565335928 |
|
|
Aug 25 08:38:31 AM UTC 24 |
Aug 25 08:38:42 AM UTC 24 |
153725223 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_access_during_key_req.723975772 |
|
|
Aug 25 08:29:11 AM UTC 24 |
Aug 25 08:39:04 AM UTC 24 |
5862508156 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.2551959349 |
|
|
Aug 25 08:38:11 AM UTC 24 |
Aug 25 08:39:11 AM UTC 24 |
2796586710 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_bijection.256889818 |
|
|
Aug 25 08:38:25 AM UTC 24 |
Aug 25 08:39:14 AM UTC 24 |
2173051383 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_lc_escalation.3429883094 |
|
|
Aug 25 08:39:13 AM UTC 24 |
Aug 25 08:39:17 AM UTC 24 |
595544039 ps |