| T552 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_throughput_w_partial_write.1292398630 |
|
|
Aug 25 08:39:04 AM UTC 24 |
Aug 25 08:39:17 AM UTC 24 |
148333039 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_access_during_key_req.735200991 |
|
|
Aug 25 08:35:54 AM UTC 24 |
Aug 25 08:39:21 AM UTC 24 |
463350858 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_ram_cfg.2232337406 |
|
|
Aug 25 08:39:21 AM UTC 24 |
Aug 25 08:39:23 AM UTC 24 |
60314333 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_max_throughput.2906492194 |
|
|
Aug 25 08:37:31 AM UTC 24 |
Aug 25 08:39:27 AM UTC 24 |
137782952 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_mem_partial_access.2329551883 |
|
|
Aug 25 08:39:28 AM UTC 24 |
Aug 25 08:39:32 AM UTC 24 |
47978094 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_executable.2477143988 |
|
|
Aug 25 08:11:12 AM UTC 24 |
Aug 25 08:39:33 AM UTC 24 |
67796249018 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_mem_walk.2595358386 |
|
|
Aug 25 08:39:24 AM UTC 24 |
Aug 25 08:39:34 AM UTC 24 |
1399690193 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_alert_test.536389477 |
|
|
Aug 25 08:39:34 AM UTC 24 |
Aug 25 08:39:36 AM UTC 24 |
43657377 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_smoke.1142514746 |
|
|
Aug 25 08:39:35 AM UTC 24 |
Aug 25 08:39:51 AM UTC 24 |
139523961 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_access_during_key_req.2853860934 |
|
|
Aug 25 08:39:15 AM UTC 24 |
Aug 25 08:39:59 AM UTC 24 |
895761113 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_multiple_keys.410659204 |
|
|
Aug 25 08:15:25 AM UTC 24 |
Aug 25 08:40:02 AM UTC 24 |
12238815061 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_max_throughput.1829092659 |
|
|
Aug 25 08:38:43 AM UTC 24 |
Aug 25 08:40:10 AM UTC 24 |
210290792 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_pipeline.3045391445 |
|
|
Aug 25 08:35:20 AM UTC 24 |
Aug 25 08:40:17 AM UTC 24 |
9246245635 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_partial_access.2011689018 |
|
|
Aug 25 08:40:03 AM UTC 24 |
Aug 25 08:40:18 AM UTC 24 |
2047612181 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_bijection.2633616913 |
|
|
Aug 25 08:39:51 AM UTC 24 |
Aug 25 08:40:25 AM UTC 24 |
4328517359 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_lc_escalation.348457403 |
|
|
Aug 25 08:40:26 AM UTC 24 |
Aug 25 08:40:40 AM UTC 24 |
1684156215 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_throughput_w_partial_write.2715320037 |
|
|
Aug 25 08:40:19 AM UTC 24 |
Aug 25 08:40:52 AM UTC 24 |
405891407 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.250057319 |
|
|
Aug 25 08:27:29 AM UTC 24 |
Aug 25 08:40:53 AM UTC 24 |
3788750342 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_partial_access_b2b.3006863773 |
|
|
Aug 25 08:35:29 AM UTC 24 |
Aug 25 08:41:25 AM UTC 24 |
38665136142 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_ram_cfg.991299062 |
|
|
Aug 25 08:41:26 AM UTC 24 |
Aug 25 08:41:28 AM UTC 24 |
197776119 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_multiple_keys.75278072 |
|
|
Aug 25 08:21:02 AM UTC 24 |
Aug 25 08:41:43 AM UTC 24 |
2473973337 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_max_throughput.2414458009 |
|
|
Aug 25 08:40:18 AM UTC 24 |
Aug 25 08:41:44 AM UTC 24 |
236831391 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_mem_walk.2701352921 |
|
|
Aug 25 08:41:29 AM UTC 24 |
Aug 25 08:41:45 AM UTC 24 |
185031781 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_mem_partial_access.3934113757 |
|
|
Aug 25 08:41:43 AM UTC 24 |
Aug 25 08:41:53 AM UTC 24 |
632894691 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_pipeline.3878683942 |
|
|
Aug 25 08:36:59 AM UTC 24 |
Aug 25 08:41:54 AM UTC 24 |
13787677623 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_alert_test.1680387445 |
|
|
Aug 25 08:41:54 AM UTC 24 |
Aug 25 08:41:56 AM UTC 24 |
18787898 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_multiple_keys.3504546154 |
|
|
Aug 25 08:26:05 AM UTC 24 |
Aug 25 08:42:05 AM UTC 24 |
34825796549 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_regwen.1389502675 |
|
|
Aug 25 08:18:38 AM UTC 24 |
Aug 25 08:42:11 AM UTC 24 |
41923131552 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_all.2218263299 |
|
|
Aug 25 08:25:46 AM UTC 24 |
Aug 25 08:42:15 AM UTC 24 |
27793040349 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_smoke.1459586955 |
|
|
Aug 25 08:41:55 AM UTC 24 |
Aug 25 08:42:16 AM UTC 24 |
660951457 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_executable.4115562016 |
|
|
Aug 25 08:29:21 AM UTC 24 |
Aug 25 08:42:23 AM UTC 24 |
37129838929 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_max_throughput.2269004370 |
|
|
Aug 25 08:42:24 AM UTC 24 |
Aug 25 08:42:35 AM UTC 24 |
65528836 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_access_during_key_req.1696222514 |
|
|
Aug 25 08:32:23 AM UTC 24 |
Aug 25 08:42:40 AM UTC 24 |
13939037782 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_regwen.1801585524 |
|
|
Aug 25 08:27:15 AM UTC 24 |
Aug 25 08:42:46 AM UTC 24 |
50367203381 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_throughput_w_partial_write.2736706071 |
|
|
Aug 25 08:42:36 AM UTC 24 |
Aug 25 08:42:50 AM UTC 24 |
304406061 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_lc_escalation.2306385788 |
|
|
Aug 25 08:42:41 AM UTC 24 |
Aug 25 08:42:54 AM UTC 24 |
2489977748 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_regwen.1817858096 |
|
|
Aug 25 08:29:22 AM UTC 24 |
Aug 25 08:43:03 AM UTC 24 |
9313816775 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_ram_cfg.189947400 |
|
|
Aug 25 08:43:04 AM UTC 24 |
Aug 25 08:43:06 AM UTC 24 |
143021024 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_bijection.2699421738 |
|
|
Aug 25 08:42:06 AM UTC 24 |
Aug 25 08:43:08 AM UTC 24 |
3955324472 ps |
| T95 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_mem_partial_access.1412226965 |
|
|
Aug 25 08:43:10 AM UTC 24 |
Aug 25 08:43:16 AM UTC 24 |
443230882 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_mem_walk.2403677 |
|
|
Aug 25 08:43:07 AM UTC 24 |
Aug 25 08:43:18 AM UTC 24 |
898439314 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_multiple_keys.3424760970 |
|
|
Aug 25 08:38:24 AM UTC 24 |
Aug 25 08:43:22 AM UTC 24 |
2914243157 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_alert_test.425036088 |
|
|
Aug 25 08:43:23 AM UTC 24 |
Aug 25 08:43:25 AM UTC 24 |
19695639 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_partial_access.2760167648 |
|
|
Aug 25 08:42:17 AM UTC 24 |
Aug 25 08:43:36 AM UTC 24 |
1239272967 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_multiple_keys.1332242224 |
|
|
Aug 25 08:31:28 AM UTC 24 |
Aug 25 08:43:36 AM UTC 24 |
24994594797 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_partial_access_b2b.1510157728 |
|
|
Aug 25 08:33:56 AM UTC 24 |
Aug 25 08:44:05 AM UTC 24 |
6064662217 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_bijection.2996830833 |
|
|
Aug 25 08:43:37 AM UTC 24 |
Aug 25 08:44:10 AM UTC 24 |
12691612011 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_multiple_keys.2530265690 |
|
|
Aug 25 08:39:37 AM UTC 24 |
Aug 25 08:44:32 AM UTC 24 |
708092403 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_partial_access.4197834179 |
|
|
Aug 25 08:44:11 AM UTC 24 |
Aug 25 08:44:32 AM UTC 24 |
285534966 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_regwen.477991868 |
|
|
Aug 25 08:30:49 AM UTC 24 |
Aug 25 08:44:36 AM UTC 24 |
10698702054 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.1686218497 |
|
|
Aug 25 08:43:17 AM UTC 24 |
Aug 25 08:44:38 AM UTC 24 |
5595159557 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_lc_escalation.1983694529 |
|
|
Aug 25 08:44:39 AM UTC 24 |
Aug 25 08:44:43 AM UTC 24 |
551205089 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_max_throughput.4185045660 |
|
|
Aug 25 08:44:33 AM UTC 24 |
Aug 25 08:44:54 AM UTC 24 |
289852431 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_smoke.3932485855 |
|
|
Aug 25 08:43:26 AM UTC 24 |
Aug 25 08:45:10 AM UTC 24 |
2646466103 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_regwen.2550216869 |
|
|
Aug 25 08:37:51 AM UTC 24 |
Aug 25 08:45:33 AM UTC 24 |
890813709 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_ram_cfg.1352575566 |
|
|
Aug 25 08:45:33 AM UTC 24 |
Aug 25 08:45:36 AM UTC 24 |
26977422 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_mem_walk.3196230110 |
|
|
Aug 25 08:45:37 AM UTC 24 |
Aug 25 08:45:45 AM UTC 24 |
457592249 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_mem_partial_access.3749627178 |
|
|
Aug 25 08:45:46 AM UTC 24 |
Aug 25 08:45:53 AM UTC 24 |
68651417 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_pipeline.331306772 |
|
|
Aug 25 08:40:00 AM UTC 24 |
Aug 25 08:46:01 AM UTC 24 |
18965593756 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_throughput_w_partial_write.912085764 |
|
|
Aug 25 08:44:36 AM UTC 24 |
Aug 25 08:46:11 AM UTC 24 |
184218729 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_alert_test.1596570892 |
|
|
Aug 25 08:46:11 AM UTC 24 |
Aug 25 08:46:14 AM UTC 24 |
46748718 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_regwen.849431527 |
|
|
Aug 25 08:42:55 AM UTC 24 |
Aug 25 08:46:22 AM UTC 24 |
876000656 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_multiple_keys.4053227581 |
|
|
Aug 25 08:18:04 AM UTC 24 |
Aug 25 08:46:25 AM UTC 24 |
79594639897 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_smoke.3638895331 |
|
|
Aug 25 08:46:15 AM UTC 24 |
Aug 25 08:46:25 AM UTC 24 |
1751091755 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_all.3642668423 |
|
|
Aug 25 08:20:44 AM UTC 24 |
Aug 25 08:46:47 AM UTC 24 |
9398798750 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_bijection.53045234 |
|
|
Aug 25 08:46:27 AM UTC 24 |
Aug 25 08:46:59 AM UTC 24 |
371757806 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_multiple_keys.621129504 |
|
|
Aug 25 08:35:04 AM UTC 24 |
Aug 25 08:47:00 AM UTC 24 |
19776791867 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_executable.2146410709 |
|
|
Aug 25 08:42:51 AM UTC 24 |
Aug 25 08:47:02 AM UTC 24 |
1752332159 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_max_throughput.544238004 |
|
|
Aug 25 08:47:00 AM UTC 24 |
Aug 25 08:47:03 AM UTC 24 |
49617904 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_lc_escalation.3257615908 |
|
|
Aug 25 08:47:05 AM UTC 24 |
Aug 25 08:47:13 AM UTC 24 |
439205266 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_partial_access.2311542927 |
|
|
Aug 25 08:46:48 AM UTC 24 |
Aug 25 08:47:17 AM UTC 24 |
1035613871 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_pipeline.2677925345 |
|
|
Aug 25 08:42:12 AM UTC 24 |
Aug 25 08:47:31 AM UTC 24 |
16478394358 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_pipeline.2164887477 |
|
|
Aug 25 08:44:06 AM UTC 24 |
Aug 25 08:47:35 AM UTC 24 |
1443850709 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_multiple_keys.1922282068 |
|
|
Aug 25 08:27:48 AM UTC 24 |
Aug 25 08:47:36 AM UTC 24 |
11573972143 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_ram_cfg.3975237757 |
|
|
Aug 25 08:47:35 AM UTC 24 |
Aug 25 08:47:37 AM UTC 24 |
169327465 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_mem_walk.3897744318 |
|
|
Aug 25 08:47:36 AM UTC 24 |
Aug 25 08:47:44 AM UTC 24 |
179849285 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_multiple_keys.4084889106 |
|
|
Aug 25 08:43:37 AM UTC 24 |
Aug 25 08:47:46 AM UTC 24 |
14556905775 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_mem_partial_access.1740106323 |
|
|
Aug 25 08:47:37 AM UTC 24 |
Aug 25 08:47:47 AM UTC 24 |
806956026 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_alert_test.97813786 |
|
|
Aug 25 08:47:47 AM UTC 24 |
Aug 25 08:47:49 AM UTC 24 |
26772736 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_smoke.3643817945 |
|
|
Aug 25 08:47:48 AM UTC 24 |
Aug 25 08:47:50 AM UTC 24 |
271628915 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_throughput_w_partial_write.738472955 |
|
|
Aug 25 08:47:02 AM UTC 24 |
Aug 25 08:48:30 AM UTC 24 |
487668927 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_access_during_key_req.4055846274 |
|
|
Aug 25 08:30:32 AM UTC 24 |
Aug 25 08:48:32 AM UTC 24 |
3054822510 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.4070848948 |
|
|
Aug 25 08:47:39 AM UTC 24 |
Aug 25 08:48:36 AM UTC 24 |
840328597 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_access_during_key_req.2486092892 |
|
|
Aug 25 08:42:46 AM UTC 24 |
Aug 25 08:48:39 AM UTC 24 |
1819974399 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_partial_access.990552661 |
|
|
Aug 25 08:48:33 AM UTC 24 |
Aug 25 08:48:52 AM UTC 24 |
442348211 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_executable.3836033819 |
|
|
Aug 25 08:32:35 AM UTC 24 |
Aug 25 08:48:57 AM UTC 24 |
9913024357 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_lc_escalation.3448580935 |
|
|
Aug 25 08:48:58 AM UTC 24 |
Aug 25 08:49:08 AM UTC 24 |
4788863983 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_bijection.2974794407 |
|
|
Aug 25 08:47:51 AM UTC 24 |
Aug 25 08:49:18 AM UTC 24 |
1239427239 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_pipeline.1144151280 |
|
|
Aug 25 08:38:27 AM UTC 24 |
Aug 25 08:49:20 AM UTC 24 |
4284773442 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.658229478 |
|
|
Aug 25 08:41:45 AM UTC 24 |
Aug 25 08:49:36 AM UTC 24 |
5644321268 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_throughput_w_partial_write.3177697143 |
|
|
Aug 25 08:48:52 AM UTC 24 |
Aug 25 08:49:38 AM UTC 24 |
441227627 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_ram_cfg.751935128 |
|
|
Aug 25 08:49:37 AM UTC 24 |
Aug 25 08:49:39 AM UTC 24 |
55587631 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_all.495401975 |
|
|
Aug 25 08:02:10 AM UTC 24 |
Aug 25 08:49:43 AM UTC 24 |
6685397353 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_max_throughput.229362313 |
|
|
Aug 25 08:48:40 AM UTC 24 |
Aug 25 08:49:44 AM UTC 24 |
213720723 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_mem_partial_access.3939584072 |
|
|
Aug 25 08:49:41 AM UTC 24 |
Aug 25 08:49:49 AM UTC 24 |
510208761 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_alert_test.3384274332 |
|
|
Aug 25 08:49:51 AM UTC 24 |
Aug 25 08:49:53 AM UTC 24 |
43142028 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_partial_access_b2b.3754073543 |
|
|
Aug 25 08:38:32 AM UTC 24 |
Aug 25 08:49:55 AM UTC 24 |
23085584044 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_executable.657279760 |
|
|
Aug 25 08:39:18 AM UTC 24 |
Aug 25 08:49:55 AM UTC 24 |
9716809746 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_partial_access_b2b.2027184839 |
|
|
Aug 25 08:40:11 AM UTC 24 |
Aug 25 08:49:56 AM UTC 24 |
5311656543 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_mem_walk.48802225 |
|
|
Aug 25 08:49:40 AM UTC 24 |
Aug 25 08:49:57 AM UTC 24 |
1314215897 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_smoke.4273931877 |
|
|
Aug 25 08:49:54 AM UTC 24 |
Aug 25 08:49:58 AM UTC 24 |
91829181 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_multiple_keys.22775988 |
|
|
Aug 25 08:41:57 AM UTC 24 |
Aug 25 08:50:02 AM UTC 24 |
4085258722 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.4095053854 |
|
|
Aug 25 08:49:44 AM UTC 24 |
Aug 25 08:50:02 AM UTC 24 |
401658823 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_access_during_key_req.2157119125 |
|
|
Aug 25 08:40:41 AM UTC 24 |
Aug 25 08:50:03 AM UTC 24 |
5324937896 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_lc_escalation.3229651718 |
|
|
Aug 25 08:50:05 AM UTC 24 |
Aug 25 08:50:11 AM UTC 24 |
539272056 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_alert_test.2685195453 |
|
|
Aug 25 09:06:03 AM UTC 24 |
Aug 25 09:06:05 AM UTC 24 |
32276746 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_throughput_w_partial_write.495118313 |
|
|
Aug 25 08:50:02 AM UTC 24 |
Aug 25 08:50:13 AM UTC 24 |
266991443 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_partial_access.1126608336 |
|
|
Aug 25 08:49:58 AM UTC 24 |
Aug 25 08:50:14 AM UTC 24 |
459616325 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_partial_access_b2b.1525725331 |
|
|
Aug 25 08:37:07 AM UTC 24 |
Aug 25 08:50:16 AM UTC 24 |
25656408101 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_ram_cfg.3749739503 |
|
|
Aug 25 08:50:17 AM UTC 24 |
Aug 25 08:50:19 AM UTC 24 |
84993995 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_mem_walk.852238563 |
|
|
Aug 25 08:50:20 AM UTC 24 |
Aug 25 08:50:29 AM UTC 24 |
1009678663 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_multiple_keys.2344372495 |
|
|
Aug 25 08:33:31 AM UTC 24 |
Aug 25 08:50:30 AM UTC 24 |
11114897149 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_access_during_key_req.2052557459 |
|
|
Aug 25 08:34:17 AM UTC 24 |
Aug 25 08:50:33 AM UTC 24 |
29371772082 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_mem_partial_access.764441725 |
|
|
Aug 25 08:50:30 AM UTC 24 |
Aug 25 08:50:38 AM UTC 24 |
227210283 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_alert_test.3999815926 |
|
|
Aug 25 08:50:39 AM UTC 24 |
Aug 25 08:50:41 AM UTC 24 |
29616336 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_max_throughput.578107107 |
|
|
Aug 25 08:50:02 AM UTC 24 |
Aug 25 08:50:44 AM UTC 24 |
100316859 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_access_during_key_req.3239510525 |
|
|
Aug 25 08:49:10 AM UTC 24 |
Aug 25 08:50:53 AM UTC 24 |
395099483 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_smoke.2606241657 |
|
|
Aug 25 08:50:42 AM UTC 24 |
Aug 25 08:50:55 AM UTC 24 |
157509992 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_bijection.3671795206 |
|
|
Aug 25 08:49:56 AM UTC 24 |
Aug 25 08:51:20 AM UTC 24 |
4104090687 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_regwen.1917614920 |
|
|
Aug 25 08:34:33 AM UTC 24 |
Aug 25 08:51:22 AM UTC 24 |
70163405819 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_executable.4236497932 |
|
|
Aug 25 08:18:35 AM UTC 24 |
Aug 25 08:51:32 AM UTC 24 |
93376632659 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_partial_access.1379273628 |
|
|
Aug 25 08:51:21 AM UTC 24 |
Aug 25 08:51:33 AM UTC 24 |
2277226723 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.720905963 |
|
|
Aug 25 08:39:32 AM UTC 24 |
Aug 25 08:51:34 AM UTC 24 |
44194749366 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_bijection.166065891 |
|
|
Aug 25 08:50:54 AM UTC 24 |
Aug 25 08:51:41 AM UTC 24 |
1888437221 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_lc_escalation.704187843 |
|
|
Aug 25 08:51:35 AM UTC 24 |
Aug 25 08:51:47 AM UTC 24 |
699340407 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_pipeline.3116791322 |
|
|
Aug 25 08:49:57 AM UTC 24 |
Aug 25 08:51:48 AM UTC 24 |
893435672 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_max_throughput.3127196833 |
|
|
Aug 25 08:51:32 AM UTC 24 |
Aug 25 08:52:04 AM UTC 24 |
624338192 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_ram_cfg.1295446417 |
|
|
Aug 25 08:52:05 AM UTC 24 |
Aug 25 08:52:07 AM UTC 24 |
82358555 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_throughput_w_partial_write.1147295415 |
|
|
Aug 25 08:51:34 AM UTC 24 |
Aug 25 08:52:12 AM UTC 24 |
580272069 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_mem_partial_access.1909129418 |
|
|
Aug 25 08:52:13 AM UTC 24 |
Aug 25 08:52:18 AM UTC 24 |
99323836 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_mem_walk.2373201757 |
|
|
Aug 25 08:52:08 AM UTC 24 |
Aug 25 08:52:22 AM UTC 24 |
1834577398 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_partial_access_b2b.120787947 |
|
|
Aug 25 08:42:17 AM UTC 24 |
Aug 25 08:52:46 AM UTC 24 |
90319738852 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_access_during_key_req.2559912376 |
|
|
Aug 25 08:47:14 AM UTC 24 |
Aug 25 08:52:48 AM UTC 24 |
8018567035 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all.4014590146 |
|
|
Aug 25 08:00:12 AM UTC 24 |
Aug 25 08:52:48 AM UTC 24 |
7397642246 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_alert_test.2230223350 |
|
|
Aug 25 08:52:48 AM UTC 24 |
Aug 25 08:52:50 AM UTC 24 |
37694022 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_smoke.3046208276 |
|
|
Aug 25 08:52:49 AM UTC 24 |
Aug 25 08:52:55 AM UTC 24 |
74846046 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_executable.4040165134 |
|
|
Aug 25 08:35:54 AM UTC 24 |
Aug 25 08:53:05 AM UTC 24 |
10266124484 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_bijection.2786560035 |
|
|
Aug 25 08:52:51 AM UTC 24 |
Aug 25 08:53:25 AM UTC 24 |
6704349245 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_partial_access_b2b.1722330995 |
|
|
Aug 25 08:49:58 AM UTC 24 |
Aug 25 08:53:32 AM UTC 24 |
5618437081 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_regwen.886961866 |
|
|
Aug 25 08:39:19 AM UTC 24 |
Aug 25 08:53:35 AM UTC 24 |
3245855203 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_throughput_w_partial_write.1494892174 |
|
|
Aug 25 08:53:34 AM UTC 24 |
Aug 25 08:53:42 AM UTC 24 |
58853794 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_lc_escalation.3064269407 |
|
|
Aug 25 08:53:35 AM UTC 24 |
Aug 25 08:53:50 AM UTC 24 |
1401146094 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_executable.1584376528 |
|
|
Aug 25 08:37:50 AM UTC 24 |
Aug 25 08:53:56 AM UTC 24 |
3290552627 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_multiple_keys.1048963984 |
|
|
Aug 25 08:46:23 AM UTC 24 |
Aug 25 08:53:59 AM UTC 24 |
41661478637 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_ram_cfg.2473007254 |
|
|
Aug 25 08:54:00 AM UTC 24 |
Aug 25 08:54:02 AM UTC 24 |
29348596 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_mem_walk.3373532022 |
|
|
Aug 25 08:54:03 AM UTC 24 |
Aug 25 08:54:10 AM UTC 24 |
294748505 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_mem_partial_access.2666384802 |
|
|
Aug 25 08:54:11 AM UTC 24 |
Aug 25 08:54:16 AM UTC 24 |
90673722 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_max_throughput.12209508 |
|
|
Aug 25 08:53:33 AM UTC 24 |
Aug 25 08:54:18 AM UTC 24 |
418321588 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_ram_cfg.3500947189 |
|
|
Aug 25 08:57:28 AM UTC 24 |
Aug 25 08:57:30 AM UTC 24 |
48152273 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_partial_access_b2b.1597907569 |
|
|
Aug 25 08:46:59 AM UTC 24 |
Aug 25 08:54:21 AM UTC 24 |
4207891564 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_partial_access.956919358 |
|
|
Aug 25 08:53:06 AM UTC 24 |
Aug 25 08:54:24 AM UTC 24 |
847065567 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.3921479767 |
|
|
Aug 25 08:54:17 AM UTC 24 |
Aug 25 08:54:24 AM UTC 24 |
123429919 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_alert_test.104935854 |
|
|
Aug 25 08:54:22 AM UTC 24 |
Aug 25 08:54:24 AM UTC 24 |
34272591 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_smoke.4240382016 |
|
|
Aug 25 08:54:25 AM UTC 24 |
Aug 25 08:54:27 AM UTC 24 |
419459192 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all.4097121184 |
|
|
Aug 25 07:57:09 AM UTC 24 |
Aug 25 08:54:28 AM UTC 24 |
18604219422 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_regwen.1029682317 |
|
|
Aug 25 08:32:39 AM UTC 24 |
Aug 25 08:54:28 AM UTC 24 |
10277766854 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_pipeline.1387306092 |
|
|
Aug 25 08:46:27 AM UTC 24 |
Aug 25 08:54:44 AM UTC 24 |
14871518200 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_max_throughput.3942006125 |
|
|
Aug 25 08:54:45 AM UTC 24 |
Aug 25 08:54:50 AM UTC 24 |
47239147 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_partial_access.2199817718 |
|
|
Aug 25 08:54:29 AM UTC 24 |
Aug 25 08:55:01 AM UTC 24 |
266650431 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_lc_escalation.1879580190 |
|
|
Aug 25 08:55:02 AM UTC 24 |
Aug 25 08:55:11 AM UTC 24 |
1317944149 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_access_during_key_req.1592077976 |
|
|
Aug 25 08:27:01 AM UTC 24 |
Aug 25 08:55:22 AM UTC 24 |
4219274034 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_multiple_keys.2302363066 |
|
|
Aug 25 08:24:03 AM UTC 24 |
Aug 25 08:55:30 AM UTC 24 |
5038382717 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_pipeline.388853555 |
|
|
Aug 25 08:48:31 AM UTC 24 |
Aug 25 08:55:30 AM UTC 24 |
10797247236 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_ram_cfg.1705180865 |
|
|
Aug 25 08:55:31 AM UTC 24 |
Aug 25 08:55:34 AM UTC 24 |
189722060 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.3507272076 |
|
|
Aug 25 08:50:32 AM UTC 24 |
Aug 25 08:55:41 AM UTC 24 |
8715133935 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_mem_walk.3430390910 |
|
|
Aug 25 08:55:34 AM UTC 24 |
Aug 25 08:55:48 AM UTC 24 |
353977144 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_mem_partial_access.2538862518 |
|
|
Aug 25 08:55:41 AM UTC 24 |
Aug 25 08:55:51 AM UTC 24 |
686789902 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_regwen.2883912395 |
|
|
Aug 25 08:47:32 AM UTC 24 |
Aug 25 08:55:54 AM UTC 24 |
15348398533 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_alert_test.615613413 |
|
|
Aug 25 08:55:55 AM UTC 24 |
Aug 25 08:55:57 AM UTC 24 |
16449235 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_smoke.2132115570 |
|
|
Aug 25 08:55:58 AM UTC 24 |
Aug 25 08:56:04 AM UTC 24 |
222918781 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all.1423673286 |
|
|
Aug 25 07:52:56 AM UTC 24 |
Aug 25 08:56:07 AM UTC 24 |
11829788933 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_bijection.294567587 |
|
|
Aug 25 08:54:26 AM UTC 24 |
Aug 25 08:56:14 AM UTC 24 |
3842859246 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_throughput_w_partial_write.845208166 |
|
|
Aug 25 08:54:51 AM UTC 24 |
Aug 25 08:56:21 AM UTC 24 |
558916259 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_all.3094589161 |
|
|
Aug 25 08:47:45 AM UTC 24 |
Aug 25 08:56:44 AM UTC 24 |
12583130623 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_bijection.1234467679 |
|
|
Aug 25 08:56:07 AM UTC 24 |
Aug 25 08:56:52 AM UTC 24 |
1801876278 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_max_throughput.2190539179 |
|
|
Aug 25 08:56:53 AM UTC 24 |
Aug 25 08:57:07 AM UTC 24 |
254574458 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_all.1312316147 |
|
|
Aug 25 07:52:35 AM UTC 24 |
Aug 25 08:57:08 AM UTC 24 |
161867726533 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_regwen.784468839 |
|
|
Aug 25 08:36:01 AM UTC 24 |
Aug 25 08:57:19 AM UTC 24 |
14156935332 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_throughput_w_partial_write.4279099818 |
|
|
Aug 25 08:57:07 AM UTC 24 |
Aug 25 08:57:21 AM UTC 24 |
183787008 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_partial_access_b2b.602504970 |
|
|
Aug 25 08:51:23 AM UTC 24 |
Aug 25 08:57:26 AM UTC 24 |
10009403416 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_lc_escalation.2425330599 |
|
|
Aug 25 08:57:08 AM UTC 24 |
Aug 25 08:57:27 AM UTC 24 |
944334525 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.512171011 |
|
|
Aug 25 08:55:49 AM UTC 24 |
Aug 25 08:57:34 AM UTC 24 |
394445110 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_mem_partial_access.942686145 |
|
|
Aug 25 08:57:34 AM UTC 24 |
Aug 25 08:57:44 AM UTC 24 |
661947274 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_mem_walk.831170003 |
|
|
Aug 25 08:57:31 AM UTC 24 |
Aug 25 08:57:44 AM UTC 24 |
146331837 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_pipeline.3312962456 |
|
|
Aug 25 08:52:55 AM UTC 24 |
Aug 25 08:57:49 AM UTC 24 |
4286307191 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_executable.334771087 |
|
|
Aug 25 08:30:35 AM UTC 24 |
Aug 25 08:57:49 AM UTC 24 |
4036766866 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_alert_test.1929734092 |
|
|
Aug 25 08:57:50 AM UTC 24 |
Aug 25 08:57:53 AM UTC 24 |
25999292 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.4002615397 |
|
|
Aug 25 08:57:45 AM UTC 24 |
Aug 25 08:57:53 AM UTC 24 |
160562239 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_multiple_keys.1023791098 |
|
|
Aug 25 08:52:49 AM UTC 24 |
Aug 25 08:58:04 AM UTC 24 |
938518484 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_partial_access.2724149515 |
|
|
Aug 25 08:56:22 AM UTC 24 |
Aug 25 08:58:18 AM UTC 24 |
218736242 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_bijection.1496924481 |
|
|
Aug 25 08:57:53 AM UTC 24 |
Aug 25 08:58:25 AM UTC 24 |
429447686 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_partial_access.2217570910 |
|
|
Aug 25 08:58:19 AM UTC 24 |
Aug 25 08:58:29 AM UTC 24 |
1224406728 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_executable.2746570314 |
|
|
Aug 25 08:40:53 AM UTC 24 |
Aug 25 08:58:34 AM UTC 24 |
36330879629 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_all.2623588756 |
|
|
Aug 25 08:04:49 AM UTC 24 |
Aug 25 08:58:34 AM UTC 24 |
19643252933 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_throughput_w_partial_write.4200472585 |
|
|
Aug 25 08:58:34 AM UTC 24 |
Aug 25 08:58:37 AM UTC 24 |
315265241 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_max_throughput.2288782736 |
|
|
Aug 25 08:58:30 AM UTC 24 |
Aug 25 08:58:39 AM UTC 24 |
269038303 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_smoke.3089687908 |
|
|
Aug 25 08:57:50 AM UTC 24 |
Aug 25 08:58:40 AM UTC 24 |
821322648 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_pipeline.3817019883 |
|
|
Aug 25 08:50:56 AM UTC 24 |
Aug 25 08:58:41 AM UTC 24 |
12534352173 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_ram_cfg.2116735387 |
|
|
Aug 25 08:58:41 AM UTC 24 |
Aug 25 08:58:43 AM UTC 24 |
102915479 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_lc_escalation.2670141291 |
|
|
Aug 25 08:58:35 AM UTC 24 |
Aug 25 08:58:47 AM UTC 24 |
3109606315 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_mem_walk.2909495153 |
|
|
Aug 25 08:58:44 AM UTC 24 |
Aug 25 08:58:53 AM UTC 24 |
216011977 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_mem_partial_access.2937082451 |
|
|
Aug 25 08:58:49 AM UTC 24 |
Aug 25 08:58:58 AM UTC 24 |
172715050 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_access_during_key_req.3469054378 |
|
|
Aug 25 08:44:44 AM UTC 24 |
Aug 25 08:59:05 AM UTC 24 |
13345220335 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_alert_test.508461114 |
|
|
Aug 25 08:59:06 AM UTC 24 |
Aug 25 08:59:09 AM UTC 24 |
110579253 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_access_during_key_req.3690536009 |
|
|
Aug 25 08:37:50 AM UTC 24 |
Aug 25 08:59:49 AM UTC 24 |
3181392158 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_all.2334353566 |
|
|
Aug 25 08:15:05 AM UTC 24 |
Aug 25 08:59:53 AM UTC 24 |
378598479241 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_pipeline.378814763 |
|
|
Aug 25 08:56:16 AM UTC 24 |
Aug 25 09:00:06 AM UTC 24 |
1872821215 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_regwen.861162412 |
|
|
Aug 25 08:51:50 AM UTC 24 |
Aug 25 09:00:17 AM UTC 24 |
34901713143 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_partial_access_b2b.3773296600 |
|
|
Aug 25 08:54:29 AM UTC 24 |
Aug 25 09:00:34 AM UTC 24 |
16937964064 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_regwen.317862546 |
|
|
Aug 25 08:57:27 AM UTC 24 |
Aug 25 09:00:45 AM UTC 24 |
8774856453 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_partial_access.3135248170 |
|
|
Aug 25 09:00:18 AM UTC 24 |
Aug 25 09:00:45 AM UTC 24 |
3660625669 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.14451352 |
|
|
Aug 25 08:58:54 AM UTC 24 |
Aug 25 09:00:50 AM UTC 24 |
676855735 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_partial_access_b2b.1463163818 |
|
|
Aug 25 08:44:33 AM UTC 24 |
Aug 25 09:00:51 AM UTC 24 |
24514275945 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_bijection.3770382979 |
|
|
Aug 25 08:59:54 AM UTC 24 |
Aug 25 09:00:51 AM UTC 24 |
2379789924 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_smoke.3351360552 |
|
|
Aug 25 08:59:10 AM UTC 24 |
Aug 25 09:00:53 AM UTC 24 |
160104170 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_access_during_key_req.152233763 |
|
|
Aug 25 08:53:43 AM UTC 24 |
Aug 25 09:00:58 AM UTC 24 |
6579280153 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_ram_cfg.1104587882 |
|
|
Aug 25 09:00:59 AM UTC 24 |
Aug 25 09:01:01 AM UTC 24 |
88210765 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_lc_escalation.687897078 |
|
|
Aug 25 09:00:52 AM UTC 24 |
Aug 25 09:01:02 AM UTC 24 |
1799994391 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_mem_partial_access.651679489 |
|
|
Aug 25 09:01:02 AM UTC 24 |
Aug 25 09:01:08 AM UTC 24 |
89824863 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_throughput_w_partial_write.1032409285 |
|
|
Aug 25 09:00:45 AM UTC 24 |
Aug 25 09:01:14 AM UTC 24 |
93176402 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_mem_walk.2632945866 |
|
|
Aug 25 09:01:02 AM UTC 24 |
Aug 25 09:01:15 AM UTC 24 |
522571325 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_access_during_key_req.1633766264 |
|
|
Aug 25 08:50:12 AM UTC 24 |
Aug 25 09:01:16 AM UTC 24 |
3130854137 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_alert_test.4004741877 |
|
|
Aug 25 09:01:16 AM UTC 24 |
Aug 25 09:01:18 AM UTC 24 |
39838838 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_max_throughput.3199730260 |
|
|
Aug 25 09:00:45 AM UTC 24 |
Aug 25 09:01:30 AM UTC 24 |
376259299 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_partial_access_b2b.2103284720 |
|
|
Aug 25 08:53:26 AM UTC 24 |
Aug 25 09:01:32 AM UTC 24 |
25592929379 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_smoke.27720365 |
|
|
Aug 25 09:01:17 AM UTC 24 |
Aug 25 09:01:33 AM UTC 24 |
199826707 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_pipeline.3641285831 |
|
|
Aug 25 08:54:29 AM UTC 24 |
Aug 25 09:01:57 AM UTC 24 |
30368997026 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_multiple_keys.1455451716 |
|
|
Aug 25 08:29:35 AM UTC 24 |
Aug 25 09:02:03 AM UTC 24 |
4661034489 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_bijection.3338439781 |
|
|
Aug 25 09:01:30 AM UTC 24 |
Aug 25 09:02:24 AM UTC 24 |
2483574910 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.2813632959 |
|
|
Aug 25 09:01:09 AM UTC 24 |
Aug 25 09:02:25 AM UTC 24 |
1637716797 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_executable.3148099402 |
|
|
Aug 25 08:55:23 AM UTC 24 |
Aug 25 09:02:37 AM UTC 24 |
1254813481 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_lc_escalation.4258547008 |
|
|
Aug 25 09:02:27 AM UTC 24 |
Aug 25 09:02:37 AM UTC 24 |
482637028 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_partial_access_b2b.1385585175 |
|
|
Aug 25 08:56:45 AM UTC 24 |
Aug 25 09:02:42 AM UTC 24 |
5606371788 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_throughput_w_partial_write.540182810 |
|
|
Aug 25 09:02:26 AM UTC 24 |
Aug 25 09:02:50 AM UTC 24 |
335533464 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_ram_cfg.1645530756 |
|
|
Aug 25 09:02:50 AM UTC 24 |
Aug 25 09:02:53 AM UTC 24 |
206712036 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_partial_access.3415840433 |
|
|
Aug 25 09:01:34 AM UTC 24 |
Aug 25 09:03:05 AM UTC 24 |
3398182863 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_mem_walk.775650622 |
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|
Aug 25 09:02:54 AM UTC 24 |
Aug 25 09:03:08 AM UTC 24 |
711187207 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_max_throughput.2113343023 |
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|
Aug 25 09:02:04 AM UTC 24 |
Aug 25 09:03:14 AM UTC 24 |
1542746438 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_mem_partial_access.2924182872 |
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|
Aug 25 09:03:06 AM UTC 24 |
Aug 25 09:03:15 AM UTC 24 |
177140908 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_alert_test.4193934365 |
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|
Aug 25 09:03:16 AM UTC 24 |
Aug 25 09:03:18 AM UTC 24 |
37119722 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_regwen.2114535700 |
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|
Aug 25 08:49:21 AM UTC 24 |
Aug 25 09:03:19 AM UTC 24 |
13148622600 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_smoke.3152616565 |
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|
Aug 25 09:03:20 AM UTC 24 |
Aug 25 09:03:27 AM UTC 24 |
138185380 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_executable.918049769 |
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|
Aug 25 08:34:29 AM UTC 24 |
Aug 25 09:03:28 AM UTC 24 |
4021038273 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_partial_access_b2b.3446485503 |
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|
Aug 25 08:48:37 AM UTC 24 |
Aug 25 09:03:37 AM UTC 24 |
110335078739 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_partial_access.671639605 |
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|
Aug 25 09:03:38 AM UTC 24 |
Aug 25 09:03:42 AM UTC 24 |
193148582 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_multiple_keys.534664372 |
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|
Aug 25 08:47:50 AM UTC 24 |
Aug 25 09:04:29 AM UTC 24 |
70408325206 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_bijection.597078466 |
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|
Aug 25 09:03:28 AM UTC 24 |
Aug 25 09:05:11 AM UTC 24 |
5169197636 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_all.691028152 |
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|
Aug 25 08:29:30 AM UTC 24 |
Aug 25 09:05:16 AM UTC 24 |
7069161968 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_multiple_keys.3681266932 |
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Aug 25 08:49:56 AM UTC 24 |
Aug 25 09:05:16 AM UTC 24 |
4778704690 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_lc_escalation.2549784847 |
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Aug 25 09:05:12 AM UTC 24 |
Aug 25 09:05:20 AM UTC 24 |
345113180 ps |