| T796 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_pipeline.4172022528 |
|
|
Aug 25 08:58:05 AM UTC 24 |
Aug 25 09:05:20 AM UTC 24 |
13314784519 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_ram_cfg.1843425683 |
|
|
Aug 25 09:05:22 AM UTC 24 |
Aug 25 09:05:24 AM UTC 24 |
47918888 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_mem_walk.371259409 |
|
|
Aug 25 09:05:25 AM UTC 24 |
Aug 25 09:05:43 AM UTC 24 |
2714477401 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_mem_partial_access.986672116 |
|
|
Aug 25 09:05:45 AM UTC 24 |
Aug 25 09:05:54 AM UTC 24 |
200924571 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_throughput_w_partial_write.3479316655 |
|
|
Aug 25 09:04:53 AM UTC 24 |
Aug 25 09:05:57 AM UTC 24 |
564555039 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_all.2691400002 |
|
|
Aug 25 08:13:26 AM UTC 24 |
Aug 25 09:06:02 AM UTC 24 |
181243931945 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_smoke.1057552679 |
|
|
Aug 25 09:06:06 AM UTC 24 |
Aug 25 09:06:10 AM UTC 24 |
103133107 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_max_throughput.2911581145 |
|
|
Aug 25 09:04:30 AM UTC 24 |
Aug 25 09:06:14 AM UTC 24 |
400766430 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_all.3400022478 |
|
|
Aug 25 08:22:15 AM UTC 24 |
Aug 25 09:06:46 AM UTC 24 |
440013568999 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_bijection.3026638399 |
|
|
Aug 25 09:06:15 AM UTC 24 |
Aug 25 09:06:49 AM UTC 24 |
3089386000 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_pipeline.2562989935 |
|
|
Aug 25 09:01:33 AM UTC 24 |
Aug 25 09:06:49 AM UTC 24 |
4886969746 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_regwen.594084181 |
|
|
Aug 25 09:05:21 AM UTC 24 |
Aug 25 09:06:55 AM UTC 24 |
2358608106 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_multiple_keys.3862695021 |
|
|
Aug 25 08:56:04 AM UTC 24 |
Aug 25 09:06:57 AM UTC 24 |
145400678947 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_max_throughput.1759066335 |
|
|
Aug 25 09:06:57 AM UTC 24 |
Aug 25 09:07:05 AM UTC 24 |
218574430 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_partial_access.2831805758 |
|
|
Aug 25 09:06:50 AM UTC 24 |
Aug 25 09:07:07 AM UTC 24 |
99440050 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_pipeline.3070329086 |
|
|
Aug 25 09:00:10 AM UTC 24 |
Aug 25 09:07:14 AM UTC 24 |
2969106390 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_executable.2978072605 |
|
|
Aug 25 08:51:48 AM UTC 24 |
Aug 25 09:07:14 AM UTC 24 |
1657275668 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_lc_escalation.2601035456 |
|
|
Aug 25 09:07:06 AM UTC 24 |
Aug 25 09:07:16 AM UTC 24 |
1644040739 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_executable.1746544649 |
|
|
Aug 25 08:50:14 AM UTC 24 |
Aug 25 09:07:18 AM UTC 24 |
2657469392 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_ram_cfg.1553295087 |
|
|
Aug 25 09:07:17 AM UTC 24 |
Aug 25 09:07:20 AM UTC 24 |
94394921 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_mem_walk.180975058 |
|
|
Aug 25 09:07:19 AM UTC 24 |
Aug 25 09:07:26 AM UTC 24 |
263911911 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_mem_partial_access.1967017652 |
|
|
Aug 25 09:07:21 AM UTC 24 |
Aug 25 09:07:28 AM UTC 24 |
90979710 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_executable.2308504197 |
|
|
Aug 25 09:00:52 AM UTC 24 |
Aug 25 09:07:31 AM UTC 24 |
29498875256 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_alert_test.2143505811 |
|
|
Aug 25 09:07:33 AM UTC 24 |
Aug 25 09:07:34 AM UTC 24 |
41199171 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_regwen.2869634129 |
|
|
Aug 25 08:40:54 AM UTC 24 |
Aug 25 09:07:45 AM UTC 24 |
4070746218 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_executable.3652583831 |
|
|
Aug 25 08:49:19 AM UTC 24 |
Aug 25 09:07:45 AM UTC 24 |
57536930662 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_smoke.3232118021 |
|
|
Aug 25 09:07:36 AM UTC 24 |
Aug 25 09:07:48 AM UTC 24 |
408344141 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_partial_access_b2b.198103632 |
|
|
Aug 25 08:58:26 AM UTC 24 |
Aug 25 09:08:09 AM UTC 24 |
6035813029 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_partial_access_b2b.3253990412 |
|
|
Aug 25 09:00:35 AM UTC 24 |
Aug 25 09:08:16 AM UTC 24 |
97357143561 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_regwen.1672292074 |
|
|
Aug 25 08:45:11 AM UTC 24 |
Aug 25 09:08:23 AM UTC 24 |
59408786248 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_multiple_keys.860022668 |
|
|
Aug 25 09:06:11 AM UTC 24 |
Aug 25 09:08:29 AM UTC 24 |
4089028312 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_throughput_w_partial_write.2975745121 |
|
|
Aug 25 09:06:58 AM UTC 24 |
Aug 25 09:08:35 AM UTC 24 |
153865175 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_lc_escalation.707695601 |
|
|
Aug 25 09:08:36 AM UTC 24 |
Aug 25 09:08:40 AM UTC 24 |
558442580 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_all.2425619447 |
|
|
Aug 25 08:31:04 AM UTC 24 |
Aug 25 09:08:52 AM UTC 24 |
13481794273 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_multiple_keys.2472002829 |
|
|
Aug 25 08:50:44 AM UTC 24 |
Aug 25 09:08:55 AM UTC 24 |
3531258661 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_bijection.886552056 |
|
|
Aug 25 09:07:46 AM UTC 24 |
Aug 25 09:09:00 AM UTC 24 |
2644131210 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_ram_cfg.2452266125 |
|
|
Aug 25 09:09:02 AM UTC 24 |
Aug 25 09:09:04 AM UTC 24 |
27534038 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_mem_walk.4248910139 |
|
|
Aug 25 09:09:05 AM UTC 24 |
Aug 25 09:09:22 AM UTC 24 |
850522964 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_mem_partial_access.3356821094 |
|
|
Aug 25 09:09:23 AM UTC 24 |
Aug 25 09:09:32 AM UTC 24 |
231164881 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_partial_access.1747023966 |
|
|
Aug 25 09:08:10 AM UTC 24 |
Aug 25 09:09:32 AM UTC 24 |
1535027453 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_regwen.4063446875 |
|
|
Aug 25 09:02:43 AM UTC 24 |
Aug 25 09:09:35 AM UTC 24 |
9980173420 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_alert_test.2449853598 |
|
|
Aug 25 09:09:36 AM UTC 24 |
Aug 25 09:09:39 AM UTC 24 |
21544047 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.2379280534 |
|
|
Aug 25 09:09:33 AM UTC 24 |
Aug 25 09:09:54 AM UTC 24 |
1448781421 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.1872506579 |
|
|
Aug 25 09:05:55 AM UTC 24 |
Aug 25 09:09:54 AM UTC 24 |
786116153 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_pipeline.1754361037 |
|
|
Aug 25 09:03:29 AM UTC 24 |
Aug 25 09:10:02 AM UTC 24 |
2828387387 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_smoke.733546903 |
|
|
Aug 25 09:09:40 AM UTC 24 |
Aug 25 09:10:04 AM UTC 24 |
3736882156 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_throughput_w_partial_write.905581954 |
|
|
Aug 25 09:08:30 AM UTC 24 |
Aug 25 09:10:17 AM UTC 24 |
569882330 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_max_throughput.2531344364 |
|
|
Aug 25 09:08:24 AM UTC 24 |
Aug 25 09:10:31 AM UTC 24 |
144210903 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_max_throughput.3310525652 |
|
|
Aug 25 09:10:18 AM UTC 24 |
Aug 25 09:10:32 AM UTC 24 |
97539661 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_partial_access.551039725 |
|
|
Aug 25 09:10:03 AM UTC 24 |
Aug 25 09:10:39 AM UTC 24 |
438675761 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_lc_escalation.1367056836 |
|
|
Aug 25 09:10:33 AM UTC 24 |
Aug 25 09:10:44 AM UTC 24 |
403272303 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_bijection.1456693801 |
|
|
Aug 25 09:09:55 AM UTC 24 |
Aug 25 09:10:50 AM UTC 24 |
2202062227 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_partial_access_b2b.4203767798 |
|
|
Aug 25 09:03:42 AM UTC 24 |
Aug 25 09:10:51 AM UTC 24 |
16849531883 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_executable.1603776451 |
|
|
Aug 25 08:53:51 AM UTC 24 |
Aug 25 09:10:53 AM UTC 24 |
12305314843 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_ram_cfg.571198636 |
|
|
Aug 25 09:10:52 AM UTC 24 |
Aug 25 09:10:54 AM UTC 24 |
79945806 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_throughput_w_partial_write.2222404859 |
|
|
Aug 25 09:10:32 AM UTC 24 |
Aug 25 09:11:00 AM UTC 24 |
422904426 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_mem_partial_access.903024414 |
|
|
Aug 25 09:10:55 AM UTC 24 |
Aug 25 09:11:04 AM UTC 24 |
154270274 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_mem_walk.2727550525 |
|
|
Aug 25 09:10:55 AM UTC 24 |
Aug 25 09:11:07 AM UTC 24 |
140044198 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_alert_test.2619002650 |
|
|
Aug 25 09:11:09 AM UTC 24 |
Aug 25 09:11:11 AM UTC 24 |
14325224 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_regwen.1821174148 |
|
|
Aug 25 08:50:15 AM UTC 24 |
Aug 25 09:11:22 AM UTC 24 |
13359921705 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_smoke.1305532392 |
|
|
Aug 25 09:11:12 AM UTC 24 |
Aug 25 09:11:28 AM UTC 24 |
188060724 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_regwen.2261814128 |
|
|
Aug 25 08:53:57 AM UTC 24 |
Aug 25 09:11:50 AM UTC 24 |
14456644141 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_pipeline.2394669985 |
|
|
Aug 25 09:07:49 AM UTC 24 |
Aug 25 09:11:52 AM UTC 24 |
10304154148 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_multiple_keys.4264611693 |
|
|
Aug 25 08:57:53 AM UTC 24 |
Aug 25 09:12:01 AM UTC 24 |
33899506356 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_partial_access.1563764712 |
|
|
Aug 25 09:11:53 AM UTC 24 |
Aug 25 09:12:07 AM UTC 24 |
2000925970 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_bijection.4121465238 |
|
|
Aug 25 09:11:29 AM UTC 24 |
Aug 25 09:12:11 AM UTC 24 |
1835510957 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_pipeline.2579675648 |
|
|
Aug 25 09:06:47 AM UTC 24 |
Aug 25 09:12:17 AM UTC 24 |
10177213177 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_access_during_key_req.4045804798 |
|
|
Aug 25 09:00:52 AM UTC 24 |
Aug 25 09:12:26 AM UTC 24 |
1550014221 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_lc_escalation.3531814057 |
|
|
Aug 25 09:12:18 AM UTC 24 |
Aug 25 09:12:29 AM UTC 24 |
480185010 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_throughput_w_partial_write.1155949938 |
|
|
Aug 25 09:12:12 AM UTC 24 |
Aug 25 09:12:34 AM UTC 24 |
82135164 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_multiple_keys.2318905081 |
|
|
Aug 25 08:59:50 AM UTC 24 |
Aug 25 09:13:02 AM UTC 24 |
19936624149 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_ram_cfg.3260208610 |
|
|
Aug 25 09:13:03 AM UTC 24 |
Aug 25 09:13:05 AM UTC 24 |
28636834 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_mem_walk.3523214098 |
|
|
Aug 25 09:13:07 AM UTC 24 |
Aug 25 09:13:15 AM UTC 24 |
244751654 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_mem_partial_access.4251577793 |
|
|
Aug 25 09:13:16 AM UTC 24 |
Aug 25 09:13:21 AM UTC 24 |
220992557 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_regwen.3305447640 |
|
|
Aug 25 08:58:41 AM UTC 24 |
Aug 25 09:13:23 AM UTC 24 |
6590575061 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_all.1906980941 |
|
|
Aug 25 08:46:02 AM UTC 24 |
Aug 25 09:13:24 AM UTC 24 |
34319088080 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_partial_access_b2b.637863750 |
|
|
Aug 25 09:01:58 AM UTC 24 |
Aug 25 09:13:27 AM UTC 24 |
100976911710 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_alert_test.260128128 |
|
|
Aug 25 09:13:25 AM UTC 24 |
Aug 25 09:13:27 AM UTC 24 |
64668525 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_max_throughput.3176591384 |
|
|
Aug 25 09:12:08 AM UTC 24 |
Aug 25 09:13:44 AM UTC 24 |
162644090 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_multiple_keys.3597040720 |
|
|
Aug 25 09:01:19 AM UTC 24 |
Aug 25 09:13:51 AM UTC 24 |
6085453394 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_regwen.210133234 |
|
|
Aug 25 09:08:57 AM UTC 24 |
Aug 25 09:13:52 AM UTC 24 |
10175984553 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_access_during_key_req.1363272243 |
|
|
Aug 25 09:08:41 AM UTC 24 |
Aug 25 09:13:55 AM UTC 24 |
9542407141 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_executable.3373627536 |
|
|
Aug 25 08:44:55 AM UTC 24 |
Aug 25 09:14:00 AM UTC 24 |
13520545394 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_all.860797565 |
|
|
Aug 25 08:08:06 AM UTC 24 |
Aug 25 09:14:12 AM UTC 24 |
38320346315 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_multiple_keys.2465995209 |
|
|
Aug 25 09:09:55 AM UTC 24 |
Aug 25 09:14:29 AM UTC 24 |
21434068021 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_executable.2458422102 |
|
|
Aug 25 09:02:38 AM UTC 24 |
Aug 25 09:14:34 AM UTC 24 |
33358481564 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_executable.2034424270 |
|
|
Aug 25 08:47:18 AM UTC 24 |
Aug 25 09:14:34 AM UTC 24 |
181288453777 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.4007764358 |
|
|
Aug 25 09:13:22 AM UTC 24 |
Aug 25 09:14:53 AM UTC 24 |
1872839143 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_access_during_key_req.787277013 |
|
|
Aug 25 08:58:38 AM UTC 24 |
Aug 25 09:15:01 AM UTC 24 |
2757198949 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.1537846754 |
|
|
Aug 25 09:11:01 AM UTC 24 |
Aug 25 09:15:04 AM UTC 24 |
3184819746 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_pipeline.751211727 |
|
|
Aug 25 09:10:00 AM UTC 24 |
Aug 25 09:15:55 AM UTC 24 |
11223324409 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_access_during_key_req.3479526869 |
|
|
Aug 25 09:10:39 AM UTC 24 |
Aug 25 09:16:20 AM UTC 24 |
1978987289 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_multiple_keys.280414091 |
|
|
Aug 25 09:03:20 AM UTC 24 |
Aug 25 09:17:01 AM UTC 24 |
48564834906 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_pipeline.1132474266 |
|
|
Aug 25 09:11:51 AM UTC 24 |
Aug 25 09:17:02 AM UTC 24 |
9572647243 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_partial_access_b2b.2953557464 |
|
|
Aug 25 09:06:50 AM UTC 24 |
Aug 25 09:17:22 AM UTC 24 |
11573734508 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_executable.488808488 |
|
|
Aug 25 08:57:22 AM UTC 24 |
Aug 25 09:17:27 AM UTC 24 |
19521816798 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_partial_access_b2b.1864601117 |
|
|
Aug 25 09:10:05 AM UTC 24 |
Aug 25 09:17:29 AM UTC 24 |
48670060736 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_multiple_keys.4083452321 |
|
|
Aug 25 08:54:26 AM UTC 24 |
Aug 25 09:17:30 AM UTC 24 |
120113026309 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_executable.454252766 |
|
|
Aug 25 09:05:18 AM UTC 24 |
Aug 25 09:17:32 AM UTC 24 |
28611607911 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_all.2110352697 |
|
|
Aug 25 08:49:44 AM UTC 24 |
Aug 25 09:17:41 AM UTC 24 |
8023758862 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_access_during_key_req.2178092723 |
|
|
Aug 25 08:51:42 AM UTC 24 |
Aug 25 09:17:51 AM UTC 24 |
4869629548 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_partial_access_b2b.1903393324 |
|
|
Aug 25 09:12:01 AM UTC 24 |
Aug 25 09:20:44 AM UTC 24 |
58761898655 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_regwen.3631308099 |
|
|
Aug 25 09:00:54 AM UTC 24 |
Aug 25 09:20:56 AM UTC 24 |
3874605805 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_access_during_key_req.1473781892 |
|
|
Aug 25 09:07:08 AM UTC 24 |
Aug 25 09:20:56 AM UTC 24 |
13354650413 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_access_during_key_req.3122796534 |
|
|
Aug 25 08:55:12 AM UTC 24 |
Aug 25 09:21:08 AM UTC 24 |
64685343866 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_all.1895571457 |
|
|
Aug 25 08:24:01 AM UTC 24 |
Aug 25 09:21:16 AM UTC 24 |
172725889457 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_all.1500605313 |
|
|
Aug 25 08:43:19 AM UTC 24 |
Aug 25 09:21:23 AM UTC 24 |
184570900293 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_executable.679545032 |
|
|
Aug 25 08:58:40 AM UTC 24 |
Aug 25 09:21:26 AM UTC 24 |
48721948085 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_multiple_keys.1946054443 |
|
|
Aug 25 09:07:46 AM UTC 24 |
Aug 25 09:21:50 AM UTC 24 |
5503349972 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_access_during_key_req.2396990152 |
|
|
Aug 25 08:57:21 AM UTC 24 |
Aug 25 09:21:56 AM UTC 24 |
4267631771 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_partial_access_b2b.3329030721 |
|
|
Aug 25 09:08:17 AM UTC 24 |
Aug 25 09:22:12 AM UTC 24 |
98019968858 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_regwen.1590199482 |
|
|
Aug 25 09:07:15 AM UTC 24 |
Aug 25 09:22:15 AM UTC 24 |
29932879843 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_all.3087183557 |
|
|
Aug 25 08:57:46 AM UTC 24 |
Aug 25 09:22:24 AM UTC 24 |
8110658584 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_regwen.721321038 |
|
|
Aug 25 08:55:31 AM UTC 24 |
Aug 25 09:23:38 AM UTC 24 |
12672799811 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_executable.3372369424 |
|
|
Aug 25 09:10:45 AM UTC 24 |
Aug 25 09:24:28 AM UTC 24 |
4114067686 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_executable.3020760303 |
|
|
Aug 25 09:12:31 AM UTC 24 |
Aug 25 09:24:49 AM UTC 24 |
2929320237 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_all.1272085294 |
|
|
Aug 25 09:07:28 AM UTC 24 |
Aug 25 09:25:38 AM UTC 24 |
105496258582 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_multiple_keys.1801024111 |
|
|
Aug 25 09:11:23 AM UTC 24 |
Aug 25 09:25:50 AM UTC 24 |
15007226623 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_all.2523674471 |
|
|
Aug 25 09:01:15 AM UTC 24 |
Aug 25 09:26:01 AM UTC 24 |
135860715693 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_all.1141627423 |
|
|
Aug 25 08:06:25 AM UTC 24 |
Aug 25 09:26:13 AM UTC 24 |
151428346284 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_all.2602660959 |
|
|
Aug 25 08:39:33 AM UTC 24 |
Aug 25 09:26:18 AM UTC 24 |
116872868340 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_access_during_key_req.688414365 |
|
|
Aug 25 09:12:26 AM UTC 24 |
Aug 25 09:26:26 AM UTC 24 |
3498910041 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_access_during_key_req.1532782162 |
|
|
Aug 25 09:02:38 AM UTC 24 |
Aug 25 09:26:40 AM UTC 24 |
14734454448 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_all.2664369795 |
|
|
Aug 25 08:36:28 AM UTC 24 |
Aug 25 09:28:07 AM UTC 24 |
7604704479 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_regwen.603073906 |
|
|
Aug 25 09:12:35 AM UTC 24 |
Aug 25 09:29:37 AM UTC 24 |
16421275355 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_executable.1944542867 |
|
|
Aug 25 09:08:53 AM UTC 24 |
Aug 25 09:31:21 AM UTC 24 |
62729518891 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_regwen.166287146 |
|
|
Aug 25 09:10:51 AM UTC 24 |
Aug 25 09:34:05 AM UTC 24 |
121281531344 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_access_during_key_req.588821318 |
|
|
Aug 25 09:05:17 AM UTC 24 |
Aug 25 09:34:41 AM UTC 24 |
8635284985 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_executable.1764558015 |
|
|
Aug 25 09:07:15 AM UTC 24 |
Aug 25 09:36:04 AM UTC 24 |
3681801854 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_all.1900365900 |
|
|
Aug 25 09:09:33 AM UTC 24 |
Aug 25 09:36:04 AM UTC 24 |
90250142583 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_all.3810535343 |
|
|
Aug 25 09:11:05 AM UTC 24 |
Aug 25 09:36:10 AM UTC 24 |
28793692599 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_all.1522570985 |
|
|
Aug 25 08:54:19 AM UTC 24 |
Aug 25 09:37:49 AM UTC 24 |
51601312016 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_all.431273982 |
|
|
Aug 25 08:58:59 AM UTC 24 |
Aug 25 09:38:51 AM UTC 24 |
10883489802 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_all.102797509 |
|
|
Aug 25 08:52:23 AM UTC 24 |
Aug 25 09:39:30 AM UTC 24 |
67050301755 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_all.4259241281 |
|
|
Aug 25 08:17:50 AM UTC 24 |
Aug 25 09:41:34 AM UTC 24 |
55605856567 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_all.2627685206 |
|
|
Aug 25 09:13:23 AM UTC 24 |
Aug 25 09:44:44 AM UTC 24 |
14985180614 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_all.4054017894 |
|
|
Aug 25 08:38:13 AM UTC 24 |
Aug 25 09:48:34 AM UTC 24 |
101567570206 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_all.4272039294 |
|
|
Aug 25 08:34:55 AM UTC 24 |
Aug 25 09:50:02 AM UTC 24 |
37407776697 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all.630560130 |
|
|
Aug 25 07:55:52 AM UTC 24 |
Aug 25 09:50:29 AM UTC 24 |
158473588145 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_all.953993954 |
|
|
Aug 25 08:11:47 AM UTC 24 |
Aug 25 09:52:07 AM UTC 24 |
117305423874 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_all.3096847148 |
|
|
Aug 25 08:19:13 AM UTC 24 |
Aug 25 09:53:10 AM UTC 24 |
49281241139 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_all.1491878949 |
|
|
Aug 25 08:33:13 AM UTC 24 |
Aug 25 10:06:32 AM UTC 24 |
15392680525 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_all.386553842 |
|
|
Aug 25 08:50:34 AM UTC 24 |
Aug 25 10:13:52 AM UTC 24 |
134722121709 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_all.2804011818 |
|
|
Aug 25 09:03:15 AM UTC 24 |
Aug 25 10:16:37 AM UTC 24 |
21898481874 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_all.3949847713 |
|
|
Aug 25 09:05:58 AM UTC 24 |
Aug 25 10:20:06 AM UTC 24 |
54253943474 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_all.1742277582 |
|
|
Aug 25 08:41:47 AM UTC 24 |
Aug 25 10:30:25 AM UTC 24 |
17504748953 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_all.780772037 |
|
|
Aug 25 08:55:52 AM UTC 24 |
Aug 25 10:42:18 AM UTC 24 |
79375094459 ps |
| T60 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.4141026773 |
|
|
Aug 25 05:54:22 AM UTC 24 |
Aug 25 05:54:24 AM UTC 24 |
49928808 ps |
| T61 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.814645489 |
|
|
Aug 25 05:54:22 AM UTC 24 |
Aug 25 05:54:25 AM UTC 24 |
13824551 ps |
| T62 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.659251241 |
|
|
Aug 25 05:54:22 AM UTC 24 |
Aug 25 05:54:25 AM UTC 24 |
35011512 ps |
| T107 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2629922743 |
|
|
Aug 25 05:54:23 AM UTC 24 |
Aug 25 05:54:25 AM UTC 24 |
54129706 ps |
| T149 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1487573149 |
|
|
Aug 25 05:54:22 AM UTC 24 |
Aug 25 05:54:25 AM UTC 24 |
126611873 ps |
| T56 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.439171443 |
|
|
Aug 25 05:54:21 AM UTC 24 |
Aug 25 05:54:26 AM UTC 24 |
514888060 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.875542273 |
|
|
Aug 25 05:54:23 AM UTC 24 |
Aug 25 05:54:26 AM UTC 24 |
92893311 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2471425325 |
|
|
Aug 25 05:54:21 AM UTC 24 |
Aug 25 05:54:26 AM UTC 24 |
81422864 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2745257927 |
|
|
Aug 25 05:54:24 AM UTC 24 |
Aug 25 05:54:26 AM UTC 24 |
18671967 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.261485921 |
|
|
Aug 25 05:54:21 AM UTC 24 |
Aug 25 05:54:27 AM UTC 24 |
369145535 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3315397194 |
|
|
Aug 25 05:54:25 AM UTC 24 |
Aug 25 05:54:28 AM UTC 24 |
35160411 ps |
| T78 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3923945360 |
|
|
Aug 25 05:54:25 AM UTC 24 |
Aug 25 05:54:28 AM UTC 24 |
15417991 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.511641752 |
|
|
Aug 25 05:54:25 AM UTC 24 |
Aug 25 05:54:28 AM UTC 24 |
36511731 ps |
| T57 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.272569641 |
|
|
Aug 25 05:54:24 AM UTC 24 |
Aug 25 05:54:28 AM UTC 24 |
116486793 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2062550929 |
|
|
Aug 25 05:54:25 AM UTC 24 |
Aug 25 05:54:28 AM UTC 24 |
37757998 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2371457458 |
|
|
Aug 25 05:54:24 AM UTC 24 |
Aug 25 05:54:28 AM UTC 24 |
264592305 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.383998720 |
|
|
Aug 25 05:54:27 AM UTC 24 |
Aug 25 05:54:29 AM UTC 24 |
23318525 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.12097524 |
|
|
Aug 25 05:54:27 AM UTC 24 |
Aug 25 05:54:29 AM UTC 24 |
12182621 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3398530693 |
|
|
Aug 25 05:54:27 AM UTC 24 |
Aug 25 05:54:29 AM UTC 24 |
12054808 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2040378505 |
|
|
Aug 25 05:54:27 AM UTC 24 |
Aug 25 05:54:29 AM UTC 24 |
17227719 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3878093930 |
|
|
Aug 25 05:54:25 AM UTC 24 |
Aug 25 05:54:29 AM UTC 24 |
538838843 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2841732164 |
|
|
Aug 25 05:54:26 AM UTC 24 |
Aug 25 05:54:30 AM UTC 24 |
111976562 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1899606606 |
|
|
Aug 25 05:54:28 AM UTC 24 |
Aug 25 05:54:30 AM UTC 24 |
106755541 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3382589997 |
|
|
Aug 25 05:54:28 AM UTC 24 |
Aug 25 05:54:30 AM UTC 24 |
12760961 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3733158559 |
|
|
Aug 25 05:54:27 AM UTC 24 |
Aug 25 05:54:31 AM UTC 24 |
31260725 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2725122920 |
|
|
Aug 25 05:54:27 AM UTC 24 |
Aug 25 05:54:31 AM UTC 24 |
163053913 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1893525392 |
|
|
Aug 25 05:54:28 AM UTC 24 |
Aug 25 05:54:31 AM UTC 24 |
14866744 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3585964183 |
|
|
Aug 25 05:54:24 AM UTC 24 |
Aug 25 05:54:31 AM UTC 24 |
825268924 ps |
| T82 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2344944235 |
|
|
Aug 25 05:54:28 AM UTC 24 |
Aug 25 05:54:31 AM UTC 24 |
44003751 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1191726428 |
|
|
Aug 25 05:54:30 AM UTC 24 |
Aug 25 05:54:32 AM UTC 24 |
32685343 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.583565199 |
|
|
Aug 25 05:54:27 AM UTC 24 |
Aug 25 05:54:32 AM UTC 24 |
58593414 ps |
| T58 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2115181268 |
|
|
Aug 25 05:54:28 AM UTC 24 |
Aug 25 05:54:32 AM UTC 24 |
143219317 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3862157774 |
|
|
Aug 25 05:54:30 AM UTC 24 |
Aug 25 05:54:32 AM UTC 24 |
81398138 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.90556528 |
|
|
Aug 25 05:54:30 AM UTC 24 |
Aug 25 05:54:32 AM UTC 24 |
17636986 ps |
| T137 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.717155149 |
|
|
Aug 25 05:54:27 AM UTC 24 |
Aug 25 05:54:32 AM UTC 24 |
719780713 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2978885282 |
|
|
Aug 25 05:54:26 AM UTC 24 |
Aug 25 05:54:33 AM UTC 24 |
1664342552 ps |
| T85 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3080732344 |
|
|
Aug 25 05:54:27 AM UTC 24 |
Aug 25 05:54:33 AM UTC 24 |
775138188 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3966386031 |
|
|
Aug 25 05:54:31 AM UTC 24 |
Aug 25 05:54:33 AM UTC 24 |
14099949 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1216165144 |
|
|
Aug 25 05:54:34 AM UTC 24 |
Aug 25 05:54:39 AM UTC 24 |
29947765 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3378444339 |
|
|
Aug 25 05:54:35 AM UTC 24 |
Aug 25 05:54:39 AM UTC 24 |
257213111 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.651645862 |
|
|
Aug 25 05:54:31 AM UTC 24 |
Aug 25 05:54:33 AM UTC 24 |
16315202 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3757670611 |
|
|
Aug 25 05:54:32 AM UTC 24 |
Aug 25 05:54:34 AM UTC 24 |
27278179 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2573654895 |
|
|
Aug 25 05:54:30 AM UTC 24 |
Aug 25 05:54:34 AM UTC 24 |
30894289 ps |
| T86 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1957438117 |
|
|
Aug 25 05:54:30 AM UTC 24 |
Aug 25 05:54:34 AM UTC 24 |
160386379 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2691005888 |
|
|
Aug 25 05:54:30 AM UTC 24 |
Aug 25 05:54:35 AM UTC 24 |
623314574 ps |
| T87 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3530318639 |
|
|
Aug 25 05:54:30 AM UTC 24 |
Aug 25 05:54:35 AM UTC 24 |
246706996 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.597905596 |
|
|
Aug 25 05:54:33 AM UTC 24 |
Aug 25 05:54:35 AM UTC 24 |
71028093 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_rw.89938852 |
|
|
Aug 25 05:54:33 AM UTC 24 |
Aug 25 05:54:35 AM UTC 24 |
14196262 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1996504094 |
|
|
Aug 25 05:54:33 AM UTC 24 |
Aug 25 05:54:35 AM UTC 24 |
58553217 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3273142986 |
|
|
Aug 25 05:54:31 AM UTC 24 |
Aug 25 05:54:35 AM UTC 24 |
523843954 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2904562719 |
|
|
Aug 25 05:54:33 AM UTC 24 |
Aug 25 05:54:36 AM UTC 24 |
62233773 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1013430069 |
|
|
Aug 25 05:54:33 AM UTC 24 |
Aug 25 05:54:36 AM UTC 24 |
70722831 ps |
| T136 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.632361996 |
|
|
Aug 25 05:54:31 AM UTC 24 |
Aug 25 05:54:36 AM UTC 24 |
807728032 ps |
| T88 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_rw.704212282 |
|
|
Aug 25 05:54:34 AM UTC 24 |
Aug 25 05:54:37 AM UTC 24 |
14223384 ps |
| T143 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1115247300 |
|
|
Aug 25 05:54:33 AM UTC 24 |
Aug 25 05:54:37 AM UTC 24 |
406054905 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.754187674 |
|
|
Aug 25 05:54:31 AM UTC 24 |
Aug 25 05:54:37 AM UTC 24 |
51445529 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.83500857 |
|
|
Aug 25 05:54:34 AM UTC 24 |
Aug 25 05:54:37 AM UTC 24 |
83868284 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.4190237409 |
|
|
Aug 25 05:54:33 AM UTC 24 |
Aug 25 05:54:37 AM UTC 24 |
919573207 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_errors.603713858 |
|
|
Aug 25 05:54:31 AM UTC 24 |
Aug 25 05:54:38 AM UTC 24 |
33285047 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3723945294 |
|
|
Aug 25 05:54:36 AM UTC 24 |
Aug 25 05:54:39 AM UTC 24 |
25719931 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1220588032 |
|
|
Aug 25 05:54:37 AM UTC 24 |
Aug 25 05:54:39 AM UTC 24 |
17662475 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.405971152 |
|
|
Aug 25 05:54:35 AM UTC 24 |
Aug 25 05:54:38 AM UTC 24 |
359235066 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2427997614 |
|
|
Aug 25 05:54:36 AM UTC 24 |
Aug 25 05:54:38 AM UTC 24 |
25423442 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.693566442 |
|
|
Aug 25 05:54:36 AM UTC 24 |
Aug 25 05:54:38 AM UTC 24 |
30226773 ps |
| T139 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2043376934 |
|
|
Aug 25 05:54:34 AM UTC 24 |
Aug 25 05:54:38 AM UTC 24 |
698257800 ps |
| T141 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1775742929 |
|
|
Aug 25 05:54:36 AM UTC 24 |
Aug 25 05:54:39 AM UTC 24 |
119195354 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2365328899 |
|
|
Aug 25 05:54:37 AM UTC 24 |
Aug 25 05:54:40 AM UTC 24 |
20698529 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2274808512 |
|
|
Aug 25 05:54:37 AM UTC 24 |
Aug 25 05:54:40 AM UTC 24 |
380895954 ps |
| T89 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2019179061 |
|
|
Aug 25 05:54:34 AM UTC 24 |
Aug 25 05:54:40 AM UTC 24 |
781199633 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1550410133 |
|
|
Aug 25 05:54:33 AM UTC 24 |
Aug 25 05:54:40 AM UTC 24 |
124187388 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_errors.4126231210 |
|
|
Aug 25 05:54:36 AM UTC 24 |
Aug 25 05:54:40 AM UTC 24 |
193071448 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.234401298 |
|
|
Aug 25 05:54:39 AM UTC 24 |
Aug 25 05:54:41 AM UTC 24 |
41877047 ps |
| T99 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.929062343 |
|
|
Aug 25 05:54:36 AM UTC 24 |
Aug 25 05:54:41 AM UTC 24 |
241368360 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.399938785 |
|
|
Aug 25 05:54:38 AM UTC 24 |
Aug 25 05:54:41 AM UTC 24 |
46661160 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3600059446 |
|
|
Aug 25 05:54:39 AM UTC 24 |
Aug 25 05:54:41 AM UTC 24 |
12814558 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2616763751 |
|
|
Aug 25 05:54:35 AM UTC 24 |
Aug 25 05:54:42 AM UTC 24 |
55576757 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.4106707195 |
|
|
Aug 25 05:54:39 AM UTC 24 |
Aug 25 05:54:42 AM UTC 24 |
123823742 ps |
| T140 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2274644390 |
|
|
Aug 25 05:54:37 AM UTC 24 |
Aug 25 05:54:42 AM UTC 24 |
775736980 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1056355878 |
|
|
Aug 25 05:54:40 AM UTC 24 |
Aug 25 05:54:42 AM UTC 24 |
32926476 ps |
| T96 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.952081663 |
|
|
Aug 25 05:54:40 AM UTC 24 |
Aug 25 05:54:42 AM UTC 24 |
92194951 ps |
| T147 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2326861869 |
|
|
Aug 25 05:54:39 AM UTC 24 |
Aug 25 05:54:42 AM UTC 24 |
120814829 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2431106451 |
|
|
Aug 25 05:54:40 AM UTC 24 |
Aug 25 05:54:43 AM UTC 24 |
26117762 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.198077053 |
|
|
Aug 25 05:54:40 AM UTC 24 |
Aug 25 05:54:43 AM UTC 24 |
35233934 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.559718620 |
|
|
Aug 25 05:54:39 AM UTC 24 |
Aug 25 05:54:43 AM UTC 24 |
235835817 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1728980058 |
|
|
Aug 25 05:54:42 AM UTC 24 |
Aug 25 05:54:44 AM UTC 24 |
50979692 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2831490717 |
|
|
Aug 25 05:54:42 AM UTC 24 |
Aug 25 05:54:44 AM UTC 24 |
13121433 ps |
| T100 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2991811520 |
|
|
Aug 25 05:54:42 AM UTC 24 |
Aug 25 05:54:44 AM UTC 24 |
18323060 ps |
| T145 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.285366087 |
|
|
Aug 25 05:54:40 AM UTC 24 |
Aug 25 05:54:44 AM UTC 24 |
148258837 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2292441032 |
|
|
Aug 25 05:54:42 AM UTC 24 |
Aug 25 05:54:44 AM UTC 24 |
24065763 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1316584768 |
|
|
Aug 25 05:54:40 AM UTC 24 |
Aug 25 05:54:45 AM UTC 24 |
28865549 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1841989617 |
|
|
Aug 25 05:54:37 AM UTC 24 |
Aug 25 05:54:45 AM UTC 24 |
129983119 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3974292292 |
|
|
Aug 25 05:54:42 AM UTC 24 |
Aug 25 05:54:45 AM UTC 24 |
147764431 ps |
| T97 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.606982832 |
|
|
Aug 25 05:54:37 AM UTC 24 |
Aug 25 05:54:45 AM UTC 24 |
785919197 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3531406814 |
|
|
Aug 25 05:54:40 AM UTC 24 |
Aug 25 05:54:45 AM UTC 24 |
222526744 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1393707305 |
|
|
Aug 25 05:54:40 AM UTC 24 |
Aug 25 05:54:45 AM UTC 24 |
49407399 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1671478612 |
|
|
Aug 25 05:54:43 AM UTC 24 |
Aug 25 05:54:45 AM UTC 24 |
14713684 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3056911403 |
|
|
Aug 25 05:54:43 AM UTC 24 |
Aug 25 05:54:46 AM UTC 24 |
21111098 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3427248880 |
|
|
Aug 25 05:54:40 AM UTC 24 |
Aug 25 05:54:46 AM UTC 24 |
51040422 ps |
| T142 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1584038746 |
|
|
Aug 25 05:54:42 AM UTC 24 |
Aug 25 05:54:46 AM UTC 24 |
2697244173 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3400126228 |
|
|
Aug 25 05:54:39 AM UTC 24 |
Aug 25 05:54:46 AM UTC 24 |
133838645 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2657137690 |
|
|
Aug 25 05:54:42 AM UTC 24 |
Aug 25 05:54:46 AM UTC 24 |
63427127 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3330733313 |
|
|
Aug 25 05:54:43 AM UTC 24 |
Aug 25 05:54:46 AM UTC 24 |
98674854 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3455104208 |
|
|
Aug 25 05:54:43 AM UTC 24 |
Aug 25 05:54:46 AM UTC 24 |
51256381 ps |