| T313 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_executable.2492411520 |
|
|
Aug 28 10:56:26 PM UTC 24 |
Aug 28 11:18:34 PM UTC 24 |
50306490328 ps |
| T314 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_lc_escalation.3521903451 |
|
|
Aug 28 11:18:26 PM UTC 24 |
Aug 28 11:18:36 PM UTC 24 |
487461605 ps |
| T315 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_bijection.2855749910 |
|
|
Aug 28 11:17:18 PM UTC 24 |
Aug 28 11:18:46 PM UTC 24 |
3342638083 ps |
| T316 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_ram_cfg.4019764522 |
|
|
Aug 28 11:18:46 PM UTC 24 |
Aug 28 11:18:48 PM UTC 24 |
85949122 ps |
| T317 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_mem_walk.1069954559 |
|
|
Aug 28 11:18:47 PM UTC 24 |
Aug 28 11:18:55 PM UTC 24 |
182974117 ps |
| T318 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_mem_partial_access.2842454502 |
|
|
Aug 28 11:18:49 PM UTC 24 |
Aug 28 11:18:58 PM UTC 24 |
1124391685 ps |
| T319 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.876132986 |
|
|
Aug 28 10:57:58 PM UTC 24 |
Aug 28 11:19:04 PM UTC 24 |
16535443685 ps |
| T320 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.659087185 |
|
|
Aug 28 11:13:45 PM UTC 24 |
Aug 28 11:19:04 PM UTC 24 |
4377164702 ps |
| T321 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_alert_test.1474319036 |
|
|
Aug 28 11:19:06 PM UTC 24 |
Aug 28 11:19:08 PM UTC 24 |
21693686 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_pipeline.2961558225 |
|
|
Aug 28 11:15:36 PM UTC 24 |
Aug 28 11:19:17 PM UTC 24 |
7004986545 ps |
| T323 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_partial_access_b2b.965939865 |
|
|
Aug 28 11:12:32 PM UTC 24 |
Aug 28 11:19:32 PM UTC 24 |
12580159094 ps |
| T324 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_smoke.2739019031 |
|
|
Aug 28 11:19:06 PM UTC 24 |
Aug 28 11:19:41 PM UTC 24 |
651138739 ps |
| T325 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_partial_access_b2b.3499742093 |
|
|
Aug 28 11:14:19 PM UTC 24 |
Aug 28 11:19:52 PM UTC 24 |
19566052570 ps |
| T326 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_access_during_key_req.3212230523 |
|
|
Aug 28 11:08:31 PM UTC 24 |
Aug 28 11:19:58 PM UTC 24 |
10433608485 ps |
| T327 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_regwen.2594084904 |
|
|
Aug 28 11:09:34 PM UTC 24 |
Aug 28 11:20:07 PM UTC 24 |
10169195078 ps |
| T328 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_partial_access.2766417203 |
|
|
Aug 28 11:19:42 PM UTC 24 |
Aug 28 11:20:08 PM UTC 24 |
5997279433 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_lc_escalation.1637197355 |
|
|
Aug 28 11:20:08 PM UTC 24 |
Aug 28 11:20:14 PM UTC 24 |
400908469 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_multiple_keys.2447624285 |
|
|
Aug 28 11:15:34 PM UTC 24 |
Aug 28 11:20:19 PM UTC 24 |
1148739912 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_all.71153282 |
|
|
Aug 28 10:58:39 PM UTC 24 |
Aug 28 11:20:26 PM UTC 24 |
21664492475 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_access_during_key_req.3139644334 |
|
|
Aug 28 11:11:16 PM UTC 24 |
Aug 28 11:20:28 PM UTC 24 |
6910928276 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.1577332337 |
|
|
Aug 28 10:59:18 PM UTC 24 |
Aug 28 11:20:28 PM UTC 24 |
11302057931 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_ram_cfg.2930397422 |
|
|
Aug 28 11:20:27 PM UTC 24 |
Aug 28 11:20:29 PM UTC 24 |
88715887 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_mem_partial_access.4013873430 |
|
|
Aug 28 11:20:28 PM UTC 24 |
Aug 28 11:20:33 PM UTC 24 |
46590177 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.3417973164 |
|
|
Aug 28 11:18:55 PM UTC 24 |
Aug 28 11:20:46 PM UTC 24 |
4966475702 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_mem_walk.499349676 |
|
|
Aug 28 11:20:28 PM UTC 24 |
Aug 28 11:20:46 PM UTC 24 |
2724049856 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_alert_test.923069934 |
|
|
Aug 28 11:20:47 PM UTC 24 |
Aug 28 11:20:49 PM UTC 24 |
13636180 ps |
| T338 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_max_throughput.3870331018 |
|
|
Aug 28 11:19:58 PM UTC 24 |
Aug 28 11:20:55 PM UTC 24 |
150956795 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_bijection.4256485431 |
|
|
Aug 28 11:19:18 PM UTC 24 |
Aug 28 11:21:03 PM UTC 24 |
19802136725 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_partial_access_b2b.461122212 |
|
|
Aug 28 11:17:34 PM UTC 24 |
Aug 28 11:21:09 PM UTC 24 |
2664506725 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_regwen.3765175664 |
|
|
Aug 28 11:07:10 PM UTC 24 |
Aug 28 11:21:10 PM UTC 24 |
35151064051 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_pipeline.3663659918 |
|
|
Aug 28 11:17:21 PM UTC 24 |
Aug 28 11:21:13 PM UTC 24 |
1960179870 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_executable.1101086463 |
|
|
Aug 28 10:58:20 PM UTC 24 |
Aug 28 11:21:20 PM UTC 24 |
23481123420 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_max_throughput.2449372474 |
|
|
Aug 28 11:21:14 PM UTC 24 |
Aug 28 11:21:23 PM UTC 24 |
222224071 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_access_during_key_req.3577341746 |
|
|
Aug 28 11:06:31 PM UTC 24 |
Aug 28 11:21:23 PM UTC 24 |
9505354303 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_throughput_w_partial_write.1629173440 |
|
|
Aug 28 11:20:02 PM UTC 24 |
Aug 28 11:21:24 PM UTC 24 |
171565335 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_partial_access_b2b.771059042 |
|
|
Aug 28 11:15:51 PM UTC 24 |
Aug 28 11:21:25 PM UTC 24 |
10501720903 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.191899833 |
|
|
Aug 28 11:03:55 PM UTC 24 |
Aug 28 11:21:26 PM UTC 24 |
4513069557 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_multiple_keys.435255334 |
|
|
Aug 28 11:04:48 PM UTC 24 |
Aug 28 11:21:27 PM UTC 24 |
13774282936 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_ram_cfg.2151134144 |
|
|
Aug 28 11:21:27 PM UTC 24 |
Aug 28 11:21:30 PM UTC 24 |
28984682 ps |
| T351 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_lc_escalation.3642639318 |
|
|
Aug 28 11:21:25 PM UTC 24 |
Aug 28 11:21:30 PM UTC 24 |
607922036 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_all.556250845 |
|
|
Aug 28 11:18:59 PM UTC 24 |
Aug 28 11:21:31 PM UTC 24 |
5340717521 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_mem_partial_access.2852283530 |
|
|
Aug 28 11:21:30 PM UTC 24 |
Aug 28 11:21:35 PM UTC 24 |
226273621 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_partial_access.3014830440 |
|
|
Aug 28 11:21:09 PM UTC 24 |
Aug 28 11:21:36 PM UTC 24 |
3684481076 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_mem_walk.3103193058 |
|
|
Aug 28 11:21:27 PM UTC 24 |
Aug 28 11:21:36 PM UTC 24 |
242902942 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_smoke.826719873 |
|
|
Aug 28 11:20:47 PM UTC 24 |
Aug 28 11:21:37 PM UTC 24 |
1056874470 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_bijection.152435589 |
|
|
Aug 28 11:20:56 PM UTC 24 |
Aug 28 11:21:37 PM UTC 24 |
1831829544 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_alert_test.2568165744 |
|
|
Aug 28 11:21:37 PM UTC 24 |
Aug 28 11:21:39 PM UTC 24 |
44131265 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_multiple_keys.1347897176 |
|
|
Aug 28 11:12:04 PM UTC 24 |
Aug 28 11:21:39 PM UTC 24 |
3222926936 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_partial_access.3092852415 |
|
|
Aug 28 11:21:40 PM UTC 24 |
Aug 28 11:21:54 PM UTC 24 |
1244874750 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.1689817507 |
|
|
Aug 28 11:21:32 PM UTC 24 |
Aug 28 11:22:22 PM UTC 24 |
7619749273 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_pipeline.1086608447 |
|
|
Aug 28 11:13:58 PM UTC 24 |
Aug 28 11:22:22 PM UTC 24 |
8060451100 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_regwen.1791850432 |
|
|
Aug 28 10:57:18 PM UTC 24 |
Aug 28 11:22:29 PM UTC 24 |
61154670423 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_access_during_key_req.1076183300 |
|
|
Aug 28 11:18:26 PM UTC 24 |
Aug 28 11:22:30 PM UTC 24 |
1356860855 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_lc_escalation.1681689165 |
|
|
Aug 28 11:22:22 PM UTC 24 |
Aug 28 11:22:33 PM UTC 24 |
552046111 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_ram_cfg.1030963445 |
|
|
Aug 28 11:22:35 PM UTC 24 |
Aug 28 11:22:37 PM UTC 24 |
98421545 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_access_during_key_req.4153999277 |
|
|
Aug 28 10:57:16 PM UTC 24 |
Aug 28 11:22:37 PM UTC 24 |
3920997294 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_executable.920247376 |
|
|
Aug 28 11:11:30 PM UTC 24 |
Aug 28 11:22:39 PM UTC 24 |
11786942850 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_mem_partial_access.3232240176 |
|
|
Aug 28 11:22:38 PM UTC 24 |
Aug 28 11:22:45 PM UTC 24 |
420730144 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_alert_test.1738443659 |
|
|
Aug 28 11:22:45 PM UTC 24 |
Aug 28 11:22:47 PM UTC 24 |
28525071 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_bijection.992045479 |
|
|
Aug 28 11:21:38 PM UTC 24 |
Aug 28 11:22:47 PM UTC 24 |
17044552397 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_regwen.2826249724 |
|
|
Aug 28 11:13:31 PM UTC 24 |
Aug 28 11:22:48 PM UTC 24 |
32337416320 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_throughput_w_partial_write.3170594247 |
|
|
Aug 28 11:21:22 PM UTC 24 |
Aug 28 11:22:49 PM UTC 24 |
577528620 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_throughput_w_partial_write.3779999002 |
|
|
Aug 28 11:22:01 PM UTC 24 |
Aug 28 11:22:50 PM UTC 24 |
272611678 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_mem_walk.3640088437 |
|
|
Aug 28 11:22:37 PM UTC 24 |
Aug 28 11:22:50 PM UTC 24 |
461343049 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_partial_access.2536138835 |
|
|
Aug 28 11:22:51 PM UTC 24 |
Aug 28 11:22:56 PM UTC 24 |
253327454 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_pipeline.3279974184 |
|
|
Aug 28 11:21:04 PM UTC 24 |
Aug 28 11:22:57 PM UTC 24 |
1792616532 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.2387375687 |
|
|
Aug 28 11:16:54 PM UTC 24 |
Aug 28 11:23:05 PM UTC 24 |
11159565095 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_lc_escalation.292105087 |
|
|
Aug 28 11:23:05 PM UTC 24 |
Aug 28 11:23:12 PM UTC 24 |
3092842306 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.3064401168 |
|
|
Aug 28 11:22:38 PM UTC 24 |
Aug 28 11:23:15 PM UTC 24 |
901046618 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_bijection.1313930140 |
|
|
Aug 28 11:22:48 PM UTC 24 |
Aug 28 11:23:16 PM UTC 24 |
20477087304 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_max_throughput.600855386 |
|
|
Aug 28 11:22:57 PM UTC 24 |
Aug 28 11:23:19 PM UTC 24 |
306305859 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_ram_cfg.1707230815 |
|
|
Aug 28 11:23:20 PM UTC 24 |
Aug 28 11:23:22 PM UTC 24 |
50106306 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_max_throughput.1668871737 |
|
|
Aug 28 11:22:00 PM UTC 24 |
Aug 28 11:23:22 PM UTC 24 |
137824939 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_executable.959139111 |
|
|
Aug 28 11:13:27 PM UTC 24 |
Aug 28 11:23:22 PM UTC 24 |
1708828575 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_mem_partial_access.2042741896 |
|
|
Aug 28 11:23:23 PM UTC 24 |
Aug 28 11:23:32 PM UTC 24 |
610989978 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_mem_walk.1162565666 |
|
|
Aug 28 11:23:23 PM UTC 24 |
Aug 28 11:23:32 PM UTC 24 |
99832883 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_alert_test.771990700 |
|
|
Aug 28 11:23:33 PM UTC 24 |
Aug 28 11:23:35 PM UTC 24 |
40253818 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_smoke.2576474903 |
|
|
Aug 28 11:21:37 PM UTC 24 |
Aug 28 11:23:37 PM UTC 24 |
292545237 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_smoke.2072121040 |
|
|
Aug 28 11:23:36 PM UTC 24 |
Aug 28 11:23:44 PM UTC 24 |
258616591 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_access_during_key_req.2708808210 |
|
|
Aug 28 11:09:17 PM UTC 24 |
Aug 28 11:23:46 PM UTC 24 |
6518347604 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_smoke.208137330 |
|
|
Aug 28 11:22:48 PM UTC 24 |
Aug 28 11:23:52 PM UTC 24 |
648668854 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_pipeline.2155673458 |
|
|
Aug 28 11:19:33 PM UTC 24 |
Aug 28 11:23:55 PM UTC 24 |
9784277633 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_bijection.3976063525 |
|
|
Aug 28 11:23:45 PM UTC 24 |
Aug 28 11:24:03 PM UTC 24 |
312870833 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_throughput_w_partial_write.2566207826 |
|
|
Aug 28 11:22:58 PM UTC 24 |
Aug 28 11:24:07 PM UTC 24 |
149399590 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_executable.1080675960 |
|
|
Aug 28 11:09:19 PM UTC 24 |
Aug 28 11:24:08 PM UTC 24 |
5592742240 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_throughput_w_partial_write.3507750779 |
|
|
Aug 28 11:24:08 PM UTC 24 |
Aug 28 11:24:11 PM UTC 24 |
41120382 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_lc_escalation.2946420039 |
|
|
Aug 28 11:24:08 PM UTC 24 |
Aug 28 11:24:19 PM UTC 24 |
1897142072 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_partial_access.1951272768 |
|
|
Aug 28 11:23:53 PM UTC 24 |
Aug 28 11:24:23 PM UTC 24 |
297565151 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_ram_cfg.1488319453 |
|
|
Aug 28 11:24:24 PM UTC 24 |
Aug 28 11:24:26 PM UTC 24 |
112980453 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_mem_walk.1007472261 |
|
|
Aug 28 11:24:27 PM UTC 24 |
Aug 28 11:24:34 PM UTC 24 |
297883486 ps |
| T89 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_mem_partial_access.3060627213 |
|
|
Aug 28 11:24:34 PM UTC 24 |
Aug 28 11:24:42 PM UTC 24 |
347123962 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_regwen.2744429341 |
|
|
Aug 28 10:58:28 PM UTC 24 |
Aug 28 11:24:45 PM UTC 24 |
46448575240 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_all.581677595 |
|
|
Aug 28 10:57:52 PM UTC 24 |
Aug 28 11:24:46 PM UTC 24 |
22203667047 ps |
| T403 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_alert_test.2334374876 |
|
|
Aug 28 11:24:48 PM UTC 24 |
Aug 28 11:24:50 PM UTC 24 |
10979082 ps |
| T404 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_multiple_keys.819482625 |
|
|
Aug 28 11:22:48 PM UTC 24 |
Aug 28 11:24:54 PM UTC 24 |
3266898587 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_all.1345746345 |
|
|
Aug 28 10:56:53 PM UTC 24 |
Aug 28 11:24:59 PM UTC 24 |
7629847491 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_smoke.1910599819 |
|
|
Aug 28 11:24:51 PM UTC 24 |
Aug 28 11:25:10 PM UTC 24 |
250257750 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_access_during_key_req.3951215226 |
|
|
Aug 28 11:16:19 PM UTC 24 |
Aug 28 11:25:12 PM UTC 24 |
10534958768 ps |
| T408 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.3508891254 |
|
|
Aug 28 11:23:24 PM UTC 24 |
Aug 28 11:25:13 PM UTC 24 |
1237667704 ps |
| T409 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_regwen.1718937176 |
|
|
Aug 28 11:08:33 PM UTC 24 |
Aug 28 11:25:20 PM UTC 24 |
16945625335 ps |
| T410 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_partial_access.2094209996 |
|
|
Aug 28 11:25:13 PM UTC 24 |
Aug 28 11:25:25 PM UTC 24 |
552998177 ps |
| T411 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_bijection.3416166673 |
|
|
Aug 28 11:25:00 PM UTC 24 |
Aug 28 11:25:33 PM UTC 24 |
6559851705 ps |
| T412 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_lc_escalation.4239975617 |
|
|
Aug 28 11:25:25 PM UTC 24 |
Aug 28 11:25:34 PM UTC 24 |
1468293447 ps |
| T413 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_max_throughput.1845300546 |
|
|
Aug 28 11:25:14 PM UTC 24 |
Aug 28 11:25:39 PM UTC 24 |
357294058 ps |
| T414 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_max_throughput.751235308 |
|
|
Aug 28 11:24:04 PM UTC 24 |
Aug 28 11:25:54 PM UTC 24 |
132947066 ps |
| T415 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_ram_cfg.3898884492 |
|
|
Aug 28 11:25:56 PM UTC 24 |
Aug 28 11:25:57 PM UTC 24 |
63522850 ps |
| T416 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_regwen.2706130457 |
|
|
Aug 28 11:18:37 PM UTC 24 |
Aug 28 11:26:01 PM UTC 24 |
15199446502 ps |
| T417 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_mem_partial_access.740236643 |
|
|
Aug 28 11:26:02 PM UTC 24 |
Aug 28 11:26:10 PM UTC 24 |
191365369 ps |
| T418 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_mem_walk.3314891200 |
|
|
Aug 28 11:25:59 PM UTC 24 |
Aug 28 11:26:12 PM UTC 24 |
177589395 ps |
| T419 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_executable.3372804113 |
|
|
Aug 28 11:15:07 PM UTC 24 |
Aug 28 11:26:24 PM UTC 24 |
24836427650 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_regwen.2385857618 |
|
|
Aug 28 11:23:18 PM UTC 24 |
Aug 28 11:26:26 PM UTC 24 |
980746778 ps |
| T421 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_alert_test.1444370630 |
|
|
Aug 28 11:26:25 PM UTC 24 |
Aug 28 11:26:27 PM UTC 24 |
23108190 ps |
| T422 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_access_during_key_req.2438080009 |
|
|
Aug 28 11:22:23 PM UTC 24 |
Aug 28 11:26:32 PM UTC 24 |
1979040746 ps |
| T423 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_smoke.3117086334 |
|
|
Aug 28 11:26:26 PM UTC 24 |
Aug 28 11:26:41 PM UTC 24 |
2148300160 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_partial_access.1449235402 |
|
|
Aug 28 11:26:42 PM UTC 24 |
Aug 28 11:26:45 PM UTC 24 |
115128879 ps |
| T425 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_partial_access_b2b.1091276650 |
|
|
Aug 28 11:21:10 PM UTC 24 |
Aug 28 11:26:57 PM UTC 24 |
7421173253 ps |
| T426 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_throughput_w_partial_write.1908833520 |
|
|
Aug 28 11:25:21 PM UTC 24 |
Aug 28 11:27:10 PM UTC 24 |
293719375 ps |
| T427 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_multiple_keys.2180502086 |
|
|
Aug 28 11:08:50 PM UTC 24 |
Aug 28 11:27:44 PM UTC 24 |
49056317910 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.456388247 |
|
|
Aug 28 11:26:11 PM UTC 24 |
Aug 28 11:27:46 PM UTC 24 |
1121849408 ps |
| T428 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_executable.1724281453 |
|
|
Aug 28 11:04:02 PM UTC 24 |
Aug 28 11:27:52 PM UTC 24 |
23978606634 ps |
| T429 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_lc_escalation.2300020584 |
|
|
Aug 28 11:27:46 PM UTC 24 |
Aug 28 11:27:54 PM UTC 24 |
1977946918 ps |
| T430 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_throughput_w_partial_write.1844395013 |
|
|
Aug 28 11:27:10 PM UTC 24 |
Aug 28 11:27:57 PM UTC 24 |
229943411 ps |
| T431 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_pipeline.998819208 |
|
|
Aug 28 11:21:38 PM UTC 24 |
Aug 28 11:27:59 PM UTC 24 |
3129521547 ps |
| T432 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all.2851475734 |
|
|
Aug 28 11:04:41 PM UTC 24 |
Aug 28 11:27:59 PM UTC 24 |
5933329190 ps |
| T433 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_ram_cfg.3339244408 |
|
|
Aug 28 11:27:58 PM UTC 24 |
Aug 28 11:28:00 PM UTC 24 |
32037597 ps |
| T434 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_mem_partial_access.1817758758 |
|
|
Aug 28 11:28:00 PM UTC 24 |
Aug 28 11:28:06 PM UTC 24 |
466331529 ps |
| T435 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_mem_walk.2682915626 |
|
|
Aug 28 11:28:00 PM UTC 24 |
Aug 28 11:28:09 PM UTC 24 |
389088509 ps |
| T436 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_alert_test.760665462 |
|
|
Aug 28 11:28:11 PM UTC 24 |
Aug 28 11:28:13 PM UTC 24 |
14570205 ps |
| T437 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_access_during_key_req.2129429193 |
|
|
Aug 28 11:12:59 PM UTC 24 |
Aug 28 11:28:13 PM UTC 24 |
5696348413 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.794651155 |
|
|
Aug 28 11:28:02 PM UTC 24 |
Aug 28 11:28:17 PM UTC 24 |
314219246 ps |
| T438 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_bijection.4091145506 |
|
|
Aug 28 11:26:32 PM UTC 24 |
Aug 28 11:28:30 PM UTC 24 |
6938349261 ps |
| T439 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_regwen.1073511243 |
|
|
Aug 28 11:22:31 PM UTC 24 |
Aug 28 11:28:37 PM UTC 24 |
31950655001 ps |
| T440 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_regwen.1102105280 |
|
|
Aug 28 11:16:34 PM UTC 24 |
Aug 28 11:28:48 PM UTC 24 |
43036436907 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_max_throughput.3599127779 |
|
|
Aug 28 11:26:58 PM UTC 24 |
Aug 28 11:28:48 PM UTC 24 |
306722554 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_partial_access_b2b.92320906 |
|
|
Aug 28 11:25:14 PM UTC 24 |
Aug 28 11:28:49 PM UTC 24 |
2791058913 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_smoke.1350671518 |
|
|
Aug 28 11:28:14 PM UTC 24 |
Aug 28 11:28:49 PM UTC 24 |
433727677 ps |
| T444 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_partial_access_b2b.3064923592 |
|
|
Aug 28 11:21:40 PM UTC 24 |
Aug 28 11:28:51 PM UTC 24 |
18422126735 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_bijection.2421958359 |
|
|
Aug 28 11:28:17 PM UTC 24 |
Aug 28 11:28:54 PM UTC 24 |
5264530784 ps |
| T446 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_partial_access.602941503 |
|
|
Aug 28 11:28:30 PM UTC 24 |
Aug 28 11:28:56 PM UTC 24 |
1094718438 ps |
| T447 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_lc_escalation.1825090332 |
|
|
Aug 28 11:28:50 PM UTC 24 |
Aug 28 11:28:57 PM UTC 24 |
394027526 ps |
| T448 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all.2281371684 |
|
|
Aug 28 11:02:44 PM UTC 24 |
Aug 28 11:28:57 PM UTC 24 |
44429722825 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_partial_access_b2b.2985717421 |
|
|
Aug 28 11:19:52 PM UTC 24 |
Aug 28 11:28:59 PM UTC 24 |
18854174099 ps |
| T450 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_ram_cfg.304544851 |
|
|
Aug 28 11:28:57 PM UTC 24 |
Aug 28 11:28:59 PM UTC 24 |
41807832 ps |
| T451 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_max_throughput.199730035 |
|
|
Aug 28 11:28:48 PM UTC 24 |
Aug 28 11:29:05 PM UTC 24 |
311497128 ps |
| T452 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_mem_partial_access.4083913915 |
|
|
Aug 28 11:28:58 PM UTC 24 |
Aug 28 11:29:07 PM UTC 24 |
352996423 ps |
| T453 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_alert_test.813140014 |
|
|
Aug 28 11:29:06 PM UTC 24 |
Aug 28 11:29:08 PM UTC 24 |
30089640 ps |
| T454 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_regwen.705303931 |
|
|
Aug 28 10:59:26 PM UTC 24 |
Aug 28 11:29:09 PM UTC 24 |
28170378676 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_smoke.4142491226 |
|
|
Aug 28 11:29:08 PM UTC 24 |
Aug 28 11:29:12 PM UTC 24 |
57898794 ps |
| T456 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_mem_walk.1560981843 |
|
|
Aug 28 11:28:58 PM UTC 24 |
Aug 28 11:29:13 PM UTC 24 |
596454355 ps |
| T457 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_throughput_w_partial_write.203604913 |
|
|
Aug 28 11:28:50 PM UTC 24 |
Aug 28 11:29:13 PM UTC 24 |
102174206 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_pipeline.3091865865 |
|
|
Aug 28 11:22:51 PM UTC 24 |
Aug 28 11:29:14 PM UTC 24 |
16862082791 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_partial_access.986033124 |
|
|
Aug 28 11:29:14 PM UTC 24 |
Aug 28 11:29:36 PM UTC 24 |
682862196 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_throughput_w_partial_write.374449590 |
|
|
Aug 28 11:29:37 PM UTC 24 |
Aug 28 11:29:39 PM UTC 24 |
36982314 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_lc_escalation.1792778808 |
|
|
Aug 28 11:29:40 PM UTC 24 |
Aug 28 11:29:50 PM UTC 24 |
1158404921 ps |
| T462 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_bijection.1886996138 |
|
|
Aug 28 11:29:09 PM UTC 24 |
Aug 28 11:30:02 PM UTC 24 |
743620549 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_multiple_keys.1542766288 |
|
|
Aug 28 11:13:52 PM UTC 24 |
Aug 28 11:30:03 PM UTC 24 |
13173481333 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_pipeline.1289035451 |
|
|
Aug 28 11:23:47 PM UTC 24 |
Aug 28 11:30:08 PM UTC 24 |
3053142092 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_partial_access_b2b.3762595113 |
|
|
Aug 28 11:22:52 PM UTC 24 |
Aug 28 11:30:09 PM UTC 24 |
52390439252 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_ram_cfg.1439191890 |
|
|
Aug 28 11:30:08 PM UTC 24 |
Aug 28 11:30:10 PM UTC 24 |
110470026 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_max_throughput.479650812 |
|
|
Aug 28 11:29:15 PM UTC 24 |
Aug 28 11:30:13 PM UTC 24 |
108456803 ps |
| T468 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_mem_walk.1944388474 |
|
|
Aug 28 11:30:10 PM UTC 24 |
Aug 28 11:30:20 PM UTC 24 |
389102375 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all.3388855876 |
|
|
Aug 28 10:57:21 PM UTC 24 |
Aug 28 11:30:20 PM UTC 24 |
6521729833 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_mem_partial_access.2808511102 |
|
|
Aug 28 11:30:12 PM UTC 24 |
Aug 28 11:30:20 PM UTC 24 |
150955192 ps |
| T471 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_alert_test.3748614722 |
|
|
Aug 28 11:30:21 PM UTC 24 |
Aug 28 11:30:23 PM UTC 24 |
34348305 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_smoke.4115894281 |
|
|
Aug 28 11:30:21 PM UTC 24 |
Aug 28 11:30:34 PM UTC 24 |
856394089 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_access_during_key_req.694425947 |
|
|
Aug 28 11:15:00 PM UTC 24 |
Aug 28 11:30:36 PM UTC 24 |
6653268914 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_pipeline.3945381110 |
|
|
Aug 28 11:25:11 PM UTC 24 |
Aug 28 11:30:41 PM UTC 24 |
25194838347 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_multiple_keys.2890195024 |
|
|
Aug 28 11:19:09 PM UTC 24 |
Aug 28 11:30:57 PM UTC 24 |
16959252743 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_pipeline.3169156389 |
|
|
Aug 28 11:26:35 PM UTC 24 |
Aug 28 11:31:02 PM UTC 24 |
4544518869 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_all.1528960428 |
|
|
Aug 28 11:15:29 PM UTC 24 |
Aug 28 11:31:07 PM UTC 24 |
91871880849 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_executable.1985787004 |
|
|
Aug 28 11:16:28 PM UTC 24 |
Aug 28 11:31:26 PM UTC 24 |
25499609122 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_lc_escalation.3733171266 |
|
|
Aug 28 11:31:27 PM UTC 24 |
Aug 28 11:31:37 PM UTC 24 |
908285205 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_max_throughput.1063432327 |
|
|
Aug 28 11:31:03 PM UTC 24 |
Aug 28 11:31:48 PM UTC 24 |
187377876 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_partial_access.847798055 |
|
|
Aug 28 11:30:41 PM UTC 24 |
Aug 28 11:32:01 PM UTC 24 |
761140737 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_bijection.795412342 |
|
|
Aug 28 11:30:34 PM UTC 24 |
Aug 28 11:32:07 PM UTC 24 |
3497713751 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_access_during_key_req.3670370050 |
|
|
Aug 28 11:21:25 PM UTC 24 |
Aug 28 11:32:07 PM UTC 24 |
3191317179 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_ram_cfg.1441248901 |
|
|
Aug 28 11:32:07 PM UTC 24 |
Aug 28 11:32:09 PM UTC 24 |
48747494 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_mem_walk.1153611148 |
|
|
Aug 28 11:32:09 PM UTC 24 |
Aug 28 11:32:16 PM UTC 24 |
143518162 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_mem_partial_access.1401462804 |
|
|
Aug 28 11:32:11 PM UTC 24 |
Aug 28 11:32:18 PM UTC 24 |
187980849 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_access_during_key_req.267384309 |
|
|
Aug 28 11:24:12 PM UTC 24 |
Aug 28 11:32:21 PM UTC 24 |
5818653104 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_throughput_w_partial_write.2090327583 |
|
|
Aug 28 11:31:08 PM UTC 24 |
Aug 28 11:32:23 PM UTC 24 |
277113595 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_alert_test.3987731048 |
|
|
Aug 28 11:32:22 PM UTC 24 |
Aug 28 11:32:24 PM UTC 24 |
21438895 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_access_during_key_req.2821007806 |
|
|
Aug 28 11:27:48 PM UTC 24 |
Aug 28 11:32:28 PM UTC 24 |
1189157272 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_partial_access_b2b.208583990 |
|
|
Aug 28 11:26:46 PM UTC 24 |
Aug 28 11:32:30 PM UTC 24 |
14332532209 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_pipeline.4109536766 |
|
|
Aug 28 11:28:18 PM UTC 24 |
Aug 28 11:32:32 PM UTC 24 |
2598063068 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_smoke.3688422466 |
|
|
Aug 28 11:32:24 PM UTC 24 |
Aug 28 11:32:44 PM UTC 24 |
458619557 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_bijection.1037638277 |
|
|
Aug 28 11:32:28 PM UTC 24 |
Aug 28 11:33:04 PM UTC 24 |
899189165 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_max_throughput.1538953067 |
|
|
Aug 28 11:33:05 PM UTC 24 |
Aug 28 11:33:21 PM UTC 24 |
189603390 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.368823035 |
|
|
Aug 28 11:32:17 PM UTC 24 |
Aug 28 11:33:27 PM UTC 24 |
1147353097 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_lc_escalation.1753570118 |
|
|
Aug 28 11:33:28 PM UTC 24 |
Aug 28 11:33:36 PM UTC 24 |
905009502 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_executable.4001021842 |
|
|
Aug 28 11:20:15 PM UTC 24 |
Aug 28 11:33:43 PM UTC 24 |
38539442769 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_executable.2952426539 |
|
|
Aug 28 11:21:26 PM UTC 24 |
Aug 28 11:33:49 PM UTC 24 |
117221462293 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_throughput_w_partial_write.960494254 |
|
|
Aug 28 11:33:22 PM UTC 24 |
Aug 28 11:33:51 PM UTC 24 |
103303063 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_executable.2402439965 |
|
|
Aug 28 11:33:44 PM UTC 24 |
Aug 28 11:33:52 PM UTC 24 |
312637836 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_ram_cfg.2156394329 |
|
|
Aug 28 11:33:52 PM UTC 24 |
Aug 28 11:33:55 PM UTC 24 |
29872956 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_mem_walk.1981607735 |
|
|
Aug 28 11:33:53 PM UTC 24 |
Aug 28 11:33:59 PM UTC 24 |
278618926 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_mem_partial_access.2836557933 |
|
|
Aug 28 11:33:56 PM UTC 24 |
Aug 28 11:34:00 PM UTC 24 |
350743649 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.2420892845 |
|
|
Aug 28 11:29:00 PM UTC 24 |
Aug 28 11:34:07 PM UTC 24 |
14775865325 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_alert_test.3270422126 |
|
|
Aug 28 11:34:08 PM UTC 24 |
Aug 28 11:34:10 PM UTC 24 |
18713765 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_partial_access.2950715031 |
|
|
Aug 28 11:32:33 PM UTC 24 |
Aug 28 11:34:11 PM UTC 24 |
274684631 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_smoke.2213164811 |
|
|
Aug 28 11:34:11 PM UTC 24 |
Aug 28 11:34:22 PM UTC 24 |
2440336075 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_regwen.1781174657 |
|
|
Aug 28 11:28:55 PM UTC 24 |
Aug 28 11:34:51 PM UTC 24 |
20430245439 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_multiple_keys.3420969222 |
|
|
Aug 28 11:23:38 PM UTC 24 |
Aug 28 11:35:01 PM UTC 24 |
11247460879 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_partial_access.1319353452 |
|
|
Aug 28 11:35:02 PM UTC 24 |
Aug 28 11:35:05 PM UTC 24 |
90560153 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_bijection.1419916321 |
|
|
Aug 28 11:34:23 PM UTC 24 |
Aug 28 11:35:09 PM UTC 24 |
1991527129 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_regwen.2369119409 |
|
|
Aug 28 11:11:36 PM UTC 24 |
Aug 28 11:35:29 PM UTC 24 |
11327614800 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_all.2692663889 |
|
|
Aug 28 11:23:32 PM UTC 24 |
Aug 28 11:35:41 PM UTC 24 |
90270382410 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_partial_access_b2b.2240054036 |
|
|
Aug 28 11:28:37 PM UTC 24 |
Aug 28 11:35:30 PM UTC 24 |
30902376519 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_lc_escalation.1880776407 |
|
|
Aug 28 11:35:31 PM UTC 24 |
Aug 28 11:35:35 PM UTC 24 |
324753262 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_throughput_w_partial_write.1305264192 |
|
|
Aug 28 11:35:30 PM UTC 24 |
Aug 28 11:35:43 PM UTC 24 |
248247845 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_max_throughput.3376627079 |
|
|
Aug 28 11:35:10 PM UTC 24 |
Aug 28 11:35:44 PM UTC 24 |
322932002 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_ram_cfg.3026638532 |
|
|
Aug 28 11:35:45 PM UTC 24 |
Aug 28 11:35:47 PM UTC 24 |
30243527 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_multiple_keys.2803377513 |
|
|
Aug 28 11:24:55 PM UTC 24 |
Aug 28 11:35:53 PM UTC 24 |
44198785834 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_regwen.890065128 |
|
|
Aug 28 11:27:56 PM UTC 24 |
Aug 28 11:35:57 PM UTC 24 |
8113116641 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_pipeline.936495274 |
|
|
Aug 28 11:29:13 PM UTC 24 |
Aug 28 11:36:00 PM UTC 24 |
12480420602 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_mem_partial_access.1440931393 |
|
|
Aug 28 11:35:54 PM UTC 24 |
Aug 28 11:36:02 PM UTC 24 |
180876945 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_alert_test.3631056146 |
|
|
Aug 28 11:36:02 PM UTC 24 |
Aug 28 11:36:04 PM UTC 24 |
41104710 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_mem_walk.4095334277 |
|
|
Aug 28 11:35:48 PM UTC 24 |
Aug 28 11:36:05 PM UTC 24 |
2634055549 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_smoke.2069576901 |
|
|
Aug 28 11:36:05 PM UTC 24 |
Aug 28 11:36:16 PM UTC 24 |
156897668 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_multiple_keys.1451445917 |
|
|
Aug 28 11:17:13 PM UTC 24 |
Aug 28 11:36:35 PM UTC 24 |
40662304412 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_multiple_keys.567169333 |
|
|
Aug 28 11:29:09 PM UTC 24 |
Aug 28 11:36:38 PM UTC 24 |
2241544361 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_pipeline.568580052 |
|
|
Aug 28 11:30:36 PM UTC 24 |
Aug 28 11:36:39 PM UTC 24 |
5923759230 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_regwen.1124773956 |
|
|
Aug 28 11:24:20 PM UTC 24 |
Aug 28 11:36:45 PM UTC 24 |
71710195827 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_bijection.1380297104 |
|
|
Aug 28 11:36:17 PM UTC 24 |
Aug 28 11:36:46 PM UTC 24 |
2188046366 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_throughput_w_partial_write.3895132101 |
|
|
Aug 28 11:36:46 PM UTC 24 |
Aug 28 11:37:00 PM UTC 24 |
1384370947 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_executable.2695951444 |
|
|
Aug 28 11:06:38 PM UTC 24 |
Aug 28 11:37:01 PM UTC 24 |
57882931907 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_partial_access_b2b.4142599972 |
|
|
Aug 28 11:23:56 PM UTC 24 |
Aug 28 11:37:04 PM UTC 24 |
47490785431 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_max_throughput.1631534780 |
|
|
Aug 28 11:36:46 PM UTC 24 |
Aug 28 11:37:05 PM UTC 24 |
466882541 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_lc_escalation.4109454859 |
|
|
Aug 28 11:37:00 PM UTC 24 |
Aug 28 11:37:10 PM UTC 24 |
1016118053 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_executable.1450842910 |
|
|
Aug 28 11:25:34 PM UTC 24 |
Aug 28 11:37:13 PM UTC 24 |
56975449982 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_ram_cfg.32717865 |
|
|
Aug 28 11:37:11 PM UTC 24 |
Aug 28 11:37:13 PM UTC 24 |
27025831 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_mem_partial_access.2767217229 |
|
|
Aug 28 11:37:14 PM UTC 24 |
Aug 28 11:37:23 PM UTC 24 |
696043392 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_multiple_keys.1305700011 |
|
|
Aug 28 11:21:37 PM UTC 24 |
Aug 28 11:37:24 PM UTC 24 |
42749143058 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_partial_access.1014065572 |
|
|
Aug 28 11:36:39 PM UTC 24 |
Aug 28 11:37:28 PM UTC 24 |
503195913 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_mem_walk.3278838884 |
|
|
Aug 28 11:37:14 PM UTC 24 |
Aug 28 11:37:28 PM UTC 24 |
455077634 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_alert_test.3436399232 |
|
|
Aug 28 11:37:29 PM UTC 24 |
Aug 28 11:37:31 PM UTC 24 |
32346469 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_smoke.1598295958 |
|
|
Aug 28 11:37:29 PM UTC 24 |
Aug 28 11:37:46 PM UTC 24 |
2536863646 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_pipeline.795062858 |
|
|
Aug 28 11:32:31 PM UTC 24 |
Aug 28 11:38:03 PM UTC 24 |
10205823332 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_access_during_key_req.2969588396 |
|
|
Aug 28 11:23:13 PM UTC 24 |
Aug 28 11:38:10 PM UTC 24 |
26640024414 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_all.1090943573 |
|
|
Aug 28 11:11:55 PM UTC 24 |
Aug 28 11:38:14 PM UTC 24 |
19067580868 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_partial_access.3378684006 |
|
|
Aug 28 11:38:11 PM UTC 24 |
Aug 28 11:38:18 PM UTC 24 |
391509825 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_max_throughput.3155813940 |
|
|
Aug 28 11:38:19 PM UTC 24 |
Aug 28 11:38:22 PM UTC 24 |
129578686 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_partial_access_b2b.1518956108 |
|
|
Aug 28 11:30:58 PM UTC 24 |
Aug 28 11:38:23 PM UTC 24 |
18233912053 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_partial_access_b2b.3840815721 |
|
|
Aug 28 11:29:14 PM UTC 24 |
Aug 28 11:38:27 PM UTC 24 |
15236371515 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_lc_escalation.2172363848 |
|
|
Aug 28 11:38:24 PM UTC 24 |
Aug 28 11:38:31 PM UTC 24 |
1083208057 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_regwen.1380395046 |
|
|
Aug 28 11:15:16 PM UTC 24 |
Aug 28 11:38:44 PM UTC 24 |
18062719327 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_bijection.1024626286 |
|
|
Aug 28 11:37:46 PM UTC 24 |
Aug 28 11:39:01 PM UTC 24 |
6725737999 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_regwen.2871573989 |
|
|
Aug 28 11:30:03 PM UTC 24 |
Aug 28 11:39:02 PM UTC 24 |
19478519952 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_ram_cfg.1352111027 |
|
|
Aug 28 11:39:02 PM UTC 24 |
Aug 28 11:39:04 PM UTC 24 |
85900150 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_mem_partial_access.284670960 |
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Aug 28 11:39:05 PM UTC 24 |
Aug 28 11:39:10 PM UTC 24 |
142147220 ps |