| T558 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.1168647394 |
|
|
Aug 28 11:30:14 PM UTC 24 |
Aug 28 11:39:12 PM UTC 24 |
7027808915 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_mem_walk.971698534 |
|
|
Aug 28 11:39:03 PM UTC 24 |
Aug 28 11:39:14 PM UTC 24 |
511779090 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_alert_test.2180770913 |
|
|
Aug 28 11:39:13 PM UTC 24 |
Aug 28 11:39:15 PM UTC 24 |
42075776 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_throughput_w_partial_write.3014605102 |
|
|
Aug 28 11:38:23 PM UTC 24 |
Aug 28 11:39:19 PM UTC 24 |
448043716 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_partial_access_b2b.2494761612 |
|
|
Aug 28 11:32:46 PM UTC 24 |
Aug 28 11:39:20 PM UTC 24 |
32381313363 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_pipeline.3501993120 |
|
|
Aug 28 11:36:36 PM UTC 24 |
Aug 28 11:39:29 PM UTC 24 |
1430747488 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.3370798577 |
|
|
Aug 28 11:39:11 PM UTC 24 |
Aug 28 11:39:40 PM UTC 24 |
719499034 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_partial_access.2486774019 |
|
|
Aug 28 11:39:30 PM UTC 24 |
Aug 28 11:39:50 PM UTC 24 |
996695858 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_smoke.3682156130 |
|
|
Aug 28 11:39:14 PM UTC 24 |
Aug 28 11:39:51 PM UTC 24 |
747186195 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_partial_access_b2b.3866115766 |
|
|
Aug 28 11:35:06 PM UTC 24 |
Aug 28 11:40:00 PM UTC 24 |
9322900044 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_lc_escalation.4176604419 |
|
|
Aug 28 11:40:01 PM UTC 24 |
Aug 28 11:40:10 PM UTC 24 |
419412062 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_bijection.4145742688 |
|
|
Aug 28 11:39:20 PM UTC 24 |
Aug 28 11:40:14 PM UTC 24 |
6062758335 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_regwen.2803078050 |
|
|
Aug 28 11:21:26 PM UTC 24 |
Aug 28 11:40:26 PM UTC 24 |
177672110029 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_max_throughput.562609206 |
|
|
Aug 28 11:39:51 PM UTC 24 |
Aug 28 11:40:38 PM UTC 24 |
117631267 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_ram_cfg.3193363752 |
|
|
Aug 28 11:40:39 PM UTC 24 |
Aug 28 11:40:41 PM UTC 24 |
78621579 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_mem_partial_access.4210693611 |
|
|
Aug 28 11:40:42 PM UTC 24 |
Aug 28 11:40:47 PM UTC 24 |
140576867 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_access_during_key_req.3169683916 |
|
|
Aug 28 11:38:28 PM UTC 24 |
Aug 28 11:40:48 PM UTC 24 |
4646982359 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_mem_walk.3364004148 |
|
|
Aug 28 11:40:42 PM UTC 24 |
Aug 28 11:40:56 PM UTC 24 |
181728472 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_alert_test.3744580348 |
|
|
Aug 28 11:40:57 PM UTC 24 |
Aug 28 11:40:59 PM UTC 24 |
13547044 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_pipeline.526339122 |
|
|
Aug 28 11:34:52 PM UTC 24 |
Aug 28 11:41:07 PM UTC 24 |
3006896595 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_smoke.481495557 |
|
|
Aug 28 11:41:00 PM UTC 24 |
Aug 28 11:41:08 PM UTC 24 |
769761885 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_all.150139844 |
|
|
Aug 28 11:10:01 PM UTC 24 |
Aug 28 11:41:22 PM UTC 24 |
20287495371 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_access_during_key_req.278917971 |
|
|
Aug 28 11:25:33 PM UTC 24 |
Aug 28 11:41:22 PM UTC 24 |
3737160601 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_partial_access.1356024483 |
|
|
Aug 28 11:41:23 PM UTC 24 |
Aug 28 11:41:28 PM UTC 24 |
309607487 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_multiple_keys.3536370765 |
|
|
Aug 28 11:30:24 PM UTC 24 |
Aug 28 11:41:31 PM UTC 24 |
11500629238 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_throughput_w_partial_write.36724411 |
|
|
Aug 28 11:39:52 PM UTC 24 |
Aug 28 11:41:35 PM UTC 24 |
305973334 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_executable.1786736170 |
|
|
Aug 28 11:18:35 PM UTC 24 |
Aug 28 11:41:36 PM UTC 24 |
120090892992 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_pipeline.1583043903 |
|
|
Aug 28 11:38:04 PM UTC 24 |
Aug 28 11:41:37 PM UTC 24 |
34026329988 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_partial_access_b2b.3366442178 |
|
|
Aug 28 11:36:40 PM UTC 24 |
Aug 28 11:41:42 PM UTC 24 |
17973076348 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_lc_escalation.110505128 |
|
|
Aug 28 11:41:37 PM UTC 24 |
Aug 28 11:41:47 PM UTC 24 |
902030462 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_regwen.1153446733 |
|
|
Aug 28 11:20:20 PM UTC 24 |
Aug 28 11:41:55 PM UTC 24 |
68320889727 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_ram_cfg.2288682260 |
|
|
Aug 28 11:41:56 PM UTC 24 |
Aug 28 11:41:58 PM UTC 24 |
28338734 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_multiple_keys.1052459213 |
|
|
Aug 28 11:37:32 PM UTC 24 |
Aug 28 11:42:00 PM UTC 24 |
3904860340 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_bijection.2226166707 |
|
|
Aug 28 11:41:10 PM UTC 24 |
Aug 28 11:42:01 PM UTC 24 |
1235850022 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_mem_partial_access.589454484 |
|
|
Aug 28 11:42:01 PM UTC 24 |
Aug 28 11:42:07 PM UTC 24 |
60928865 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_throughput_w_partial_write.1470842534 |
|
|
Aug 28 11:41:35 PM UTC 24 |
Aug 28 11:42:08 PM UTC 24 |
99154525 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_alert_test.3962804105 |
|
|
Aug 28 11:42:09 PM UTC 24 |
Aug 28 11:42:11 PM UTC 24 |
14222055 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_mem_walk.1290915587 |
|
|
Aug 28 11:41:59 PM UTC 24 |
Aug 28 11:42:12 PM UTC 24 |
187112910 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.4146675937 |
|
|
Aug 28 11:34:00 PM UTC 24 |
Aug 28 11:42:29 PM UTC 24 |
2374660487 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_executable.2932475566 |
|
|
Aug 28 11:41:43 PM UTC 24 |
Aug 28 11:42:29 PM UTC 24 |
344718126 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_executable.2588833551 |
|
|
Aug 28 11:27:54 PM UTC 24 |
Aug 28 11:42:31 PM UTC 24 |
23576401362 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_all.3456010365 |
|
|
Aug 28 11:20:34 PM UTC 24 |
Aug 28 11:42:31 PM UTC 24 |
19784335935 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_executable.660734918 |
|
|
Aug 28 11:30:02 PM UTC 24 |
Aug 28 11:42:34 PM UTC 24 |
5188479745 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_executable.706937789 |
|
|
Aug 28 11:28:52 PM UTC 24 |
Aug 28 11:42:41 PM UTC 24 |
10304096225 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.1160902336 |
|
|
Aug 28 11:40:48 PM UTC 24 |
Aug 28 11:42:45 PM UTC 24 |
1544823075 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_access_during_key_req.3384625609 |
|
|
Aug 28 11:31:38 PM UTC 24 |
Aug 28 11:42:50 PM UTC 24 |
3015077458 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_lc_escalation.1013072801 |
|
|
Aug 28 11:42:46 PM UTC 24 |
Aug 28 11:42:50 PM UTC 24 |
431897720 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_max_throughput.3023425795 |
|
|
Aug 28 11:41:32 PM UTC 24 |
Aug 28 11:43:03 PM UTC 24 |
150830429 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_partial_access.3481826660 |
|
|
Aug 28 11:42:32 PM UTC 24 |
Aug 28 11:43:28 PM UTC 24 |
609764302 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_access_during_key_req.1997196487 |
|
|
Aug 28 11:28:51 PM UTC 24 |
Aug 28 11:43:29 PM UTC 24 |
4425548283 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_max_throughput.4212341288 |
|
|
Aug 28 11:42:35 PM UTC 24 |
Aug 28 11:43:29 PM UTC 24 |
102951592 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_ram_cfg.2323023626 |
|
|
Aug 28 11:43:29 PM UTC 24 |
Aug 28 11:43:31 PM UTC 24 |
96955533 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_pipeline.4279169346 |
|
|
Aug 28 11:39:21 PM UTC 24 |
Aug 28 11:43:32 PM UTC 24 |
2576270856 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_smoke.1291775323 |
|
|
Aug 28 11:42:12 PM UTC 24 |
Aug 28 11:43:33 PM UTC 24 |
1178252725 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_alert_test.4213152662 |
|
|
Aug 28 11:43:34 PM UTC 24 |
Aug 28 11:43:36 PM UTC 24 |
12871542 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_executable.1139878978 |
|
|
Aug 28 11:24:12 PM UTC 24 |
Aug 28 11:43:36 PM UTC 24 |
26606928685 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_mem_partial_access.1599783510 |
|
|
Aug 28 11:43:31 PM UTC 24 |
Aug 28 11:43:37 PM UTC 24 |
336851043 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_mem_walk.2162596486 |
|
|
Aug 28 11:43:30 PM UTC 24 |
Aug 28 11:43:38 PM UTC 24 |
187951507 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_multiple_keys.3689031828 |
|
|
Aug 28 11:26:28 PM UTC 24 |
Aug 28 11:43:39 PM UTC 24 |
4776560223 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_smoke.1414035385 |
|
|
Aug 28 11:43:37 PM UTC 24 |
Aug 28 11:43:41 PM UTC 24 |
40502213 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_bijection.1950771837 |
|
|
Aug 28 11:42:29 PM UTC 24 |
Aug 28 11:43:49 PM UTC 24 |
14427019863 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_partial_access.4000162585 |
|
|
Aug 28 11:43:40 PM UTC 24 |
Aug 28 11:44:05 PM UTC 24 |
127588984 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_regwen.150902407 |
|
|
Aug 28 11:35:43 PM UTC 24 |
Aug 28 11:44:09 PM UTC 24 |
12644145952 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_bijection.421356533 |
|
|
Aug 28 11:43:37 PM UTC 24 |
Aug 28 11:44:13 PM UTC 24 |
1626936385 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_lc_escalation.2980316439 |
|
|
Aug 28 11:44:10 PM UTC 24 |
Aug 28 11:44:14 PM UTC 24 |
421332071 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_throughput_w_partial_write.2746255042 |
|
|
Aug 28 11:42:42 PM UTC 24 |
Aug 28 11:44:17 PM UTC 24 |
546657669 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_throughput_w_partial_write.1841936641 |
|
|
Aug 28 11:44:06 PM UTC 24 |
Aug 28 11:44:17 PM UTC 24 |
122363183 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_ram_cfg.1864925238 |
|
|
Aug 28 11:44:18 PM UTC 24 |
Aug 28 11:44:20 PM UTC 24 |
40779671 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_mem_walk.2792468555 |
|
|
Aug 28 11:44:21 PM UTC 24 |
Aug 28 11:44:31 PM UTC 24 |
1155765830 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_mem_partial_access.3503509914 |
|
|
Aug 28 11:44:32 PM UTC 24 |
Aug 28 11:44:37 PM UTC 24 |
89216319 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_access_during_key_req.2950400497 |
|
|
Aug 28 11:20:09 PM UTC 24 |
Aug 28 11:44:58 PM UTC 24 |
5579106836 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.3250897167 |
|
|
Aug 28 11:42:02 PM UTC 24 |
Aug 28 11:45:11 PM UTC 24 |
15362367097 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_alert_test.314728166 |
|
|
Aug 28 11:45:12 PM UTC 24 |
Aug 28 11:45:14 PM UTC 24 |
157396816 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_max_throughput.2272642447 |
|
|
Aug 28 11:43:50 PM UTC 24 |
Aug 28 11:45:42 PM UTC 24 |
140320330 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_smoke.3950231763 |
|
|
Aug 28 11:45:15 PM UTC 24 |
Aug 28 11:45:42 PM UTC 24 |
778833122 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_partial_access_b2b.1857375527 |
|
|
Aug 28 11:41:29 PM UTC 24 |
Aug 28 11:45:57 PM UTC 24 |
2861822239 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_regwen.2918913241 |
|
|
Aug 28 11:25:39 PM UTC 24 |
Aug 28 11:46:13 PM UTC 24 |
66164076584 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_multiple_keys.3727600349 |
|
|
Aug 28 11:20:50 PM UTC 24 |
Aug 28 11:46:15 PM UTC 24 |
58445515342 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_executable.897059818 |
|
|
Aug 28 11:31:48 PM UTC 24 |
Aug 28 11:46:28 PM UTC 24 |
7458755772 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_throughput_w_partial_write.1432574174 |
|
|
Aug 28 11:46:29 PM UTC 24 |
Aug 28 11:46:32 PM UTC 24 |
134490968 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_all.3788176156 |
|
|
Aug 28 11:26:13 PM UTC 24 |
Aug 28 11:46:42 PM UTC 24 |
28392865732 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_access_during_key_req.2942591304 |
|
|
Aug 28 11:33:37 PM UTC 24 |
Aug 28 11:46:45 PM UTC 24 |
3638998441 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_lc_escalation.3286796692 |
|
|
Aug 28 11:46:32 PM UTC 24 |
Aug 28 11:46:45 PM UTC 24 |
3311464169 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_multiple_keys.489542345 |
|
|
Aug 28 11:28:14 PM UTC 24 |
Aug 28 11:46:53 PM UTC 24 |
12846991455 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_ram_cfg.2210370095 |
|
|
Aug 28 11:46:54 PM UTC 24 |
Aug 28 11:46:56 PM UTC 24 |
29394684 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_bijection.3739476003 |
|
|
Aug 28 11:45:43 PM UTC 24 |
Aug 28 11:47:13 PM UTC 24 |
7087564785 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_mem_walk.1969223411 |
|
|
Aug 28 11:46:57 PM UTC 24 |
Aug 28 11:47:15 PM UTC 24 |
1425212953 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_executable.2637728806 |
|
|
Aug 28 11:23:15 PM UTC 24 |
Aug 28 11:47:16 PM UTC 24 |
56744874735 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_mem_partial_access.2456288734 |
|
|
Aug 28 11:47:14 PM UTC 24 |
Aug 28 11:47:21 PM UTC 24 |
67607116 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_max_throughput.3995229825 |
|
|
Aug 28 11:46:20 PM UTC 24 |
Aug 28 11:47:24 PM UTC 24 |
137437027 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_alert_test.4071730045 |
|
|
Aug 28 11:47:22 PM UTC 24 |
Aug 28 11:47:24 PM UTC 24 |
14756338 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_multiple_keys.1892746522 |
|
|
Aug 28 11:32:25 PM UTC 24 |
Aug 28 11:47:32 PM UTC 24 |
58285879368 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_multiple_keys.3393491797 |
|
|
Aug 28 11:41:08 PM UTC 24 |
Aug 28 11:47:33 PM UTC 24 |
8977551374 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_regwen.2868905399 |
|
|
Aug 28 11:38:46 PM UTC 24 |
Aug 28 11:47:40 PM UTC 24 |
11666764396 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_executable.3057998245 |
|
|
Aug 28 11:22:29 PM UTC 24 |
Aug 28 11:47:44 PM UTC 24 |
16619496433 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_pipeline.4063537096 |
|
|
Aug 28 11:43:39 PM UTC 24 |
Aug 28 11:47:46 PM UTC 24 |
2264554868 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_max_throughput.2603854849 |
|
|
Aug 28 11:47:47 PM UTC 24 |
Aug 28 11:47:50 PM UTC 24 |
157866983 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_pipeline.3327590876 |
|
|
Aug 28 11:41:23 PM UTC 24 |
Aug 28 11:47:53 PM UTC 24 |
4973066284 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_partial_access.2885069071 |
|
|
Aug 28 11:46:15 PM UTC 24 |
Aug 28 11:47:53 PM UTC 24 |
2924608063 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_throughput_w_partial_write.1153380137 |
|
|
Aug 28 11:47:51 PM UTC 24 |
Aug 28 11:47:56 PM UTC 24 |
86870623 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_partial_access_b2b.1957406724 |
|
|
Aug 28 11:39:41 PM UTC 24 |
Aug 28 11:48:01 PM UTC 24 |
30137744717 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_lc_escalation.3301122235 |
|
|
Aug 28 11:47:53 PM UTC 24 |
Aug 28 11:48:02 PM UTC 24 |
514417279 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_ram_cfg.3070170275 |
|
|
Aug 28 11:48:03 PM UTC 24 |
Aug 28 11:48:05 PM UTC 24 |
87681005 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_mem_walk.745981708 |
|
|
Aug 28 11:48:06 PM UTC 24 |
Aug 28 11:48:21 PM UTC 24 |
2116945299 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_regwen.3843637875 |
|
|
Aug 28 11:37:07 PM UTC 24 |
Aug 28 11:48:26 PM UTC 24 |
1767044615 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_mem_partial_access.2438232804 |
|
|
Aug 28 11:48:22 PM UTC 24 |
Aug 28 11:48:27 PM UTC 24 |
112417350 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_regwen.4223404439 |
|
|
Aug 28 11:41:48 PM UTC 24 |
Aug 28 11:48:31 PM UTC 24 |
6564830972 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_partial_access.2508818063 |
|
|
Aug 28 11:47:41 PM UTC 24 |
Aug 28 11:48:31 PM UTC 24 |
1800923077 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_alert_test.451267462 |
|
|
Aug 28 11:48:32 PM UTC 24 |
Aug 28 11:48:34 PM UTC 24 |
13890904 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.4271132972 |
|
|
Aug 28 11:47:16 PM UTC 24 |
Aug 28 11:48:36 PM UTC 24 |
11603048692 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_pipeline.1319634584 |
|
|
Aug 28 11:42:30 PM UTC 24 |
Aug 28 11:48:40 PM UTC 24 |
13183428542 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_smoke.3455678478 |
|
|
Aug 28 11:47:25 PM UTC 24 |
Aug 28 11:48:43 PM UTC 24 |
4683272272 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_smoke.2736725298 |
|
|
Aug 28 11:48:32 PM UTC 24 |
Aug 28 11:48:45 PM UTC 24 |
1065766609 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_partial_access.3147615660 |
|
|
Aug 28 11:48:44 PM UTC 24 |
Aug 28 11:48:55 PM UTC 24 |
633791254 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_bijection.2029552123 |
|
|
Aug 28 11:47:33 PM UTC 24 |
Aug 28 11:48:57 PM UTC 24 |
6442438552 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_max_throughput.1318568372 |
|
|
Aug 28 11:48:56 PM UTC 24 |
Aug 28 11:48:59 PM UTC 24 |
73920715 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_bijection.2086438175 |
|
|
Aug 28 11:48:36 PM UTC 24 |
Aug 28 11:49:02 PM UTC 24 |
1339288002 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_partial_access_b2b.99871014 |
|
|
Aug 28 11:42:33 PM UTC 24 |
Aug 28 11:49:12 PM UTC 24 |
35664545377 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_lc_escalation.980673804 |
|
|
Aug 28 11:49:00 PM UTC 24 |
Aug 28 11:49:12 PM UTC 24 |
2386575761 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_regwen.2665054329 |
|
|
Aug 28 11:33:50 PM UTC 24 |
Aug 28 11:49:51 PM UTC 24 |
13837085972 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_ram_cfg.3356108077 |
|
|
Aug 28 11:49:52 PM UTC 24 |
Aug 28 11:49:54 PM UTC 24 |
89613854 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_mem_walk.3471237017 |
|
|
Aug 28 11:49:55 PM UTC 24 |
Aug 28 11:50:03 PM UTC 24 |
412798186 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_access_during_key_req.313890455 |
|
|
Aug 28 11:29:51 PM UTC 24 |
Aug 28 11:50:04 PM UTC 24 |
5757051765 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_mem_partial_access.1542776748 |
|
|
Aug 28 11:50:04 PM UTC 24 |
Aug 28 11:50:09 PM UTC 24 |
216904052 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_multiple_keys.887820509 |
|
|
Aug 28 11:39:17 PM UTC 24 |
Aug 28 11:50:10 PM UTC 24 |
29100549943 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_regwen.1414763379 |
|
|
Aug 28 11:43:04 PM UTC 24 |
Aug 28 11:50:11 PM UTC 24 |
13168679739 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_alert_test.3845834122 |
|
|
Aug 28 11:50:11 PM UTC 24 |
Aug 28 11:50:13 PM UTC 24 |
14473926 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_smoke.2702033895 |
|
|
Aug 28 11:50:12 PM UTC 24 |
Aug 28 11:50:20 PM UTC 24 |
143363945 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_partial_access_b2b.1373278564 |
|
|
Aug 28 11:38:15 PM UTC 24 |
Aug 28 11:50:40 PM UTC 24 |
53084723429 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_throughput_w_partial_write.1335880201 |
|
|
Aug 28 11:48:58 PM UTC 24 |
Aug 28 11:50:46 PM UTC 24 |
778412583 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_bijection.477712738 |
|
|
Aug 28 11:50:21 PM UTC 24 |
Aug 28 11:50:59 PM UTC 24 |
1199394527 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_partial_access.2531901362 |
|
|
Aug 28 11:50:47 PM UTC 24 |
Aug 28 11:51:03 PM UTC 24 |
1045121517 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_max_throughput.1630678704 |
|
|
Aug 28 11:51:04 PM UTC 24 |
Aug 28 11:51:17 PM UTC 24 |
501714867 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_partial_access_b2b.568050119 |
|
|
Aug 28 11:43:42 PM UTC 24 |
Aug 28 11:51:29 PM UTC 24 |
16251293928 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_pipeline.409489809 |
|
|
Aug 28 11:45:58 PM UTC 24 |
Aug 28 11:51:31 PM UTC 24 |
5389197927 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_lc_escalation.628531033 |
|
|
Aug 28 11:51:29 PM UTC 24 |
Aug 28 11:51:33 PM UTC 24 |
702801851 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_throughput_w_partial_write.2843234045 |
|
|
Aug 28 11:51:18 PM UTC 24 |
Aug 28 11:51:34 PM UTC 24 |
148735347 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_ram_cfg.3734446105 |
|
|
Aug 28 11:51:35 PM UTC 24 |
Aug 28 11:51:37 PM UTC 24 |
78593825 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_mem_walk.3465910369 |
|
|
Aug 28 11:51:38 PM UTC 24 |
Aug 28 11:51:47 PM UTC 24 |
942985644 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_executable.3343873812 |
|
|
Aug 28 11:40:15 PM UTC 24 |
Aug 28 11:51:54 PM UTC 24 |
23959116149 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_mem_partial_access.3428610736 |
|
|
Aug 28 11:51:47 PM UTC 24 |
Aug 28 11:51:55 PM UTC 24 |
191919050 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_partial_access_b2b.3318005566 |
|
|
Aug 28 11:48:46 PM UTC 24 |
Aug 28 11:52:04 PM UTC 24 |
2658742638 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_access_during_key_req.1330192607 |
|
|
Aug 28 11:37:02 PM UTC 24 |
Aug 28 11:52:05 PM UTC 24 |
51861144476 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_all.1454605013 |
|
|
Aug 28 10:56:39 PM UTC 24 |
Aug 28 11:52:06 PM UTC 24 |
156286024124 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_alert_test.1252690281 |
|
|
Aug 28 11:52:05 PM UTC 24 |
Aug 28 11:52:07 PM UTC 24 |
12279840 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_partial_access_b2b.26479456 |
|
|
Aug 28 11:46:16 PM UTC 24 |
Aug 28 11:52:12 PM UTC 24 |
19274720090 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_smoke.66633719 |
|
|
Aug 28 11:52:06 PM UTC 24 |
Aug 28 11:52:23 PM UTC 24 |
264208263 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_multiple_keys.4141698121 |
|
|
Aug 28 11:42:13 PM UTC 24 |
Aug 28 11:52:29 PM UTC 24 |
25861762078 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_partial_access.2539253008 |
|
|
Aug 28 11:52:23 PM UTC 24 |
Aug 28 11:52:34 PM UTC 24 |
1826192264 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.2725135180 |
|
|
Aug 28 11:51:55 PM UTC 24 |
Aug 28 11:52:35 PM UTC 24 |
1807484321 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_access_during_key_req.2404181497 |
|
|
Aug 28 11:35:36 PM UTC 24 |
Aug 28 11:52:36 PM UTC 24 |
3575260464 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_throughput_w_partial_write.1016085847 |
|
|
Aug 28 11:52:36 PM UTC 24 |
Aug 28 11:52:38 PM UTC 24 |
143486206 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_max_throughput.4283007586 |
|
|
Aug 28 11:52:35 PM UTC 24 |
Aug 28 11:52:41 PM UTC 24 |
96146955 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_bijection.2340199715 |
|
|
Aug 28 11:52:08 PM UTC 24 |
Aug 28 11:52:44 PM UTC 24 |
453414553 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_lc_escalation.901898763 |
|
|
Aug 28 11:52:37 PM UTC 24 |
Aug 28 11:52:47 PM UTC 24 |
1432941616 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_ram_cfg.1629944018 |
|
|
Aug 28 11:52:48 PM UTC 24 |
Aug 28 11:52:51 PM UTC 24 |
32904472 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_mem_walk.1625872673 |
|
|
Aug 28 11:52:51 PM UTC 24 |
Aug 28 11:52:59 PM UTC 24 |
288213258 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_mem_partial_access.3716839588 |
|
|
Aug 28 11:53:00 PM UTC 24 |
Aug 28 11:53:09 PM UTC 24 |
197720165 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_multiple_keys.457739538 |
|
|
Aug 28 11:47:25 PM UTC 24 |
Aug 28 11:53:48 PM UTC 24 |
7209288476 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_executable.2682654746 |
|
|
Aug 28 11:38:32 PM UTC 24 |
Aug 28 11:53:48 PM UTC 24 |
3349335501 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_alert_test.3076465970 |
|
|
Aug 28 11:53:49 PM UTC 24 |
Aug 28 11:53:51 PM UTC 24 |
28081572 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.3436691223 |
|
|
Aug 28 11:53:11 PM UTC 24 |
Aug 28 11:54:06 PM UTC 24 |
662826607 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_smoke.2648093937 |
|
|
Aug 28 11:53:52 PM UTC 24 |
Aug 28 11:54:14 PM UTC 24 |
2568653908 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_partial_access_b2b.1159225872 |
|
|
Aug 28 11:51:00 PM UTC 24 |
Aug 28 11:54:54 PM UTC 24 |
5932472580 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_bijection.1181302083 |
|
|
Aug 28 11:54:15 PM UTC 24 |
Aug 28 11:55:10 PM UTC 24 |
7263973176 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_pipeline.4150918060 |
|
|
Aug 28 11:47:33 PM UTC 24 |
Aug 28 11:55:12 PM UTC 24 |
47406156639 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_pipeline.3009349005 |
|
|
Aug 28 11:52:13 PM UTC 24 |
Aug 28 11:55:14 PM UTC 24 |
1673172799 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_multiple_keys.3559902211 |
|
|
Aug 28 11:45:42 PM UTC 24 |
Aug 28 11:55:24 PM UTC 24 |
9479961433 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_throughput_w_partial_write.160363546 |
|
|
Aug 28 11:55:25 PM UTC 24 |
Aug 28 11:55:30 PM UTC 24 |
51616753 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_executable.1192459881 |
|
|
Aug 28 11:44:14 PM UTC 24 |
Aug 28 11:55:35 PM UTC 24 |
96757770207 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_partial_access_b2b.2806961307 |
|
|
Aug 28 11:47:45 PM UTC 24 |
Aug 28 11:55:40 PM UTC 24 |
5711633040 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_lc_escalation.1524268630 |
|
|
Aug 28 11:55:31 PM UTC 24 |
Aug 28 11:55:45 PM UTC 24 |
1588111878 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_pipeline.3625116056 |
|
|
Aug 28 11:48:42 PM UTC 24 |
Aug 28 11:55:47 PM UTC 24 |
3726279056 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_ram_cfg.2992642044 |
|
|
Aug 28 11:55:48 PM UTC 24 |
Aug 28 11:55:50 PM UTC 24 |
32590780 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_partial_access.817748474 |
|
|
Aug 28 11:55:11 PM UTC 24 |
Aug 28 11:55:54 PM UTC 24 |
1476075239 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_access_during_key_req.3358446438 |
|
|
Aug 28 11:49:03 PM UTC 24 |
Aug 28 11:55:55 PM UTC 24 |
1802698961 ps |
| T90 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_mem_partial_access.3262109795 |
|
|
Aug 28 11:55:54 PM UTC 24 |
Aug 28 11:56:01 PM UTC 24 |
557296709 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_pipeline.1855467399 |
|
|
Aug 28 11:50:41 PM UTC 24 |
Aug 28 11:56:01 PM UTC 24 |
11979642866 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_all.3802631126 |
|
|
Aug 28 11:53:49 PM UTC 24 |
Aug 28 11:56:02 PM UTC 24 |
7005149917 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_mem_walk.1650044996 |
|
|
Aug 28 11:55:51 PM UTC 24 |
Aug 28 11:56:02 PM UTC 24 |
346848794 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.3822233631 |
|
|
Aug 28 11:50:05 PM UTC 24 |
Aug 28 11:56:03 PM UTC 24 |
5149986489 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_alert_test.4005059845 |
|
|
Aug 28 11:56:02 PM UTC 24 |
Aug 28 11:56:04 PM UTC 24 |
23200577 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all.2137933077 |
|
|
Aug 28 10:56:28 PM UTC 24 |
Aug 28 11:56:10 PM UTC 24 |
218242295339 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_smoke.3847208250 |
|
|
Aug 28 11:56:03 PM UTC 24 |
Aug 28 11:56:16 PM UTC 24 |
612508587 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all.1982176914 |
|
|
Aug 28 10:59:39 PM UTC 24 |
Aug 28 11:56:18 PM UTC 24 |
41421325296 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.3334971750 |
|
|
Aug 28 11:43:32 PM UTC 24 |
Aug 28 11:56:20 PM UTC 24 |
2290991392 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_max_throughput.1617743311 |
|
|
Aug 28 11:56:19 PM UTC 24 |
Aug 28 11:56:27 PM UTC 24 |
61512282 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_lc_escalation.643695025 |
|
|
Aug 28 11:56:28 PM UTC 24 |
Aug 28 11:56:43 PM UTC 24 |
990346365 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_bijection.2121395292 |
|
|
Aug 28 11:56:04 PM UTC 24 |
Aug 28 11:56:44 PM UTC 24 |
926713945 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_all.2147359760 |
|
|
Aug 28 11:07:28 PM UTC 24 |
Aug 28 11:56:44 PM UTC 24 |
42406846708 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_all.2705542795 |
|
|
Aug 28 11:48:28 PM UTC 24 |
Aug 28 11:56:47 PM UTC 24 |
6953910729 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_max_throughput.2425308360 |
|
|
Aug 28 11:55:15 PM UTC 24 |
Aug 28 11:56:47 PM UTC 24 |
590141362 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_ram_cfg.444344117 |
|
|
Aug 28 11:56:48 PM UTC 24 |
Aug 28 11:56:50 PM UTC 24 |
144660919 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_access_during_key_req.3745719854 |
|
|
Aug 28 11:42:50 PM UTC 24 |
Aug 28 11:56:51 PM UTC 24 |
13890290358 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_mem_partial_access.882059048 |
|
|
Aug 28 11:56:51 PM UTC 24 |
Aug 28 11:56:56 PM UTC 24 |
110420892 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_mem_walk.3800384771 |
|
|
Aug 28 11:56:48 PM UTC 24 |
Aug 28 11:56:57 PM UTC 24 |
462071915 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_alert_test.1331552091 |
|
|
Aug 28 11:56:57 PM UTC 24 |
Aug 28 11:56:59 PM UTC 24 |
22604106 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_smoke.2215802109 |
|
|
Aug 28 11:57:00 PM UTC 24 |
Aug 28 11:57:20 PM UTC 24 |
835930053 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_partial_access.2624232705 |
|
|
Aug 28 11:56:10 PM UTC 24 |
Aug 28 11:57:31 PM UTC 24 |
579053612 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_regwen.2336992118 |
|
|
Aug 28 11:32:02 PM UTC 24 |
Aug 28 11:57:37 PM UTC 24 |
76351534757 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_executable.1918048111 |
|
|
Aug 28 11:35:42 PM UTC 24 |
Aug 28 11:57:50 PM UTC 24 |
19616866392 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_bijection.3886604673 |
|
|
Aug 28 11:57:32 PM UTC 24 |
Aug 28 11:57:57 PM UTC 24 |
789785103 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_throughput_w_partial_write.3715895786 |
|
|
Aug 28 11:56:21 PM UTC 24 |
Aug 28 11:58:10 PM UTC 24 |
155964285 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_max_throughput.1437544124 |
|
|
Aug 28 11:58:10 PM UTC 24 |
Aug 28 11:58:13 PM UTC 24 |
122282669 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.3832730286 |
|
|
Aug 28 11:56:52 PM UTC 24 |
Aug 28 11:58:13 PM UTC 24 |
2338156572 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_lc_escalation.181518097 |
|
|
Aug 28 11:58:14 PM UTC 24 |
Aug 28 11:58:22 PM UTC 24 |
1797851035 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_multiple_keys.2128532918 |
|
|
Aug 28 11:34:12 PM UTC 24 |
Aug 28 11:58:28 PM UTC 24 |
4393178763 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_all.335484683 |
|
|
Aug 28 11:51:56 PM UTC 24 |
Aug 28 11:58:32 PM UTC 24 |
25178228309 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_multiple_keys.866690777 |
|
|
Aug 28 11:43:37 PM UTC 24 |
Aug 28 11:58:45 PM UTC 24 |
23059357457 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_ram_cfg.3791482833 |
|
|
Aug 28 11:58:46 PM UTC 24 |
Aug 28 11:58:48 PM UTC 24 |
83674644 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_partial_access.3706563104 |
|
|
Aug 28 11:57:50 PM UTC 24 |
Aug 28 11:58:50 PM UTC 24 |
6815392453 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_pipeline.979431833 |
|
|
Aug 28 11:54:55 PM UTC 24 |
Aug 28 11:58:52 PM UTC 24 |
12010618383 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_partial_access_b2b.3600739396 |
|
|
Aug 28 11:52:29 PM UTC 24 |
Aug 28 11:58:54 PM UTC 24 |
18897558956 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_mem_walk.115461037 |
|
|
Aug 28 11:58:49 PM UTC 24 |
Aug 28 11:58:56 PM UTC 24 |
288915439 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_access_during_key_req.1615430138 |
|
|
Aug 28 11:40:11 PM UTC 24 |
Aug 28 11:58:57 PM UTC 24 |
15975537212 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_mem_partial_access.1618398381 |
|
|
Aug 28 11:58:51 PM UTC 24 |
Aug 28 11:58:57 PM UTC 24 |
93322851 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_alert_test.1934680766 |
|
|
Aug 28 11:58:57 PM UTC 24 |
Aug 28 11:58:59 PM UTC 24 |
20193713 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_throughput_w_partial_write.4088197153 |
|
|
Aug 28 11:58:14 PM UTC 24 |
Aug 28 11:59:01 PM UTC 24 |
117469004 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_multiple_keys.1075037730 |
|
|
Aug 28 11:50:15 PM UTC 24 |
Aug 28 11:59:03 PM UTC 24 |
9562857683 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_executable.4065723807 |
|
|
Aug 28 11:47:56 PM UTC 24 |
Aug 28 11:59:06 PM UTC 24 |
11695881687 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_smoke.1857924117 |
|
|
Aug 28 11:58:58 PM UTC 24 |
Aug 28 11:59:09 PM UTC 24 |
210457550 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.477611348 |
|
|
Aug 28 11:55:55 PM UTC 24 |
Aug 28 11:59:10 PM UTC 24 |
3189751797 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_multiple_keys.2937707711 |
|
|
Aug 28 11:48:35 PM UTC 24 |
Aug 28 11:59:15 PM UTC 24 |
42773030449 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_bijection.215046533 |
|
|
Aug 28 11:58:59 PM UTC 24 |
Aug 28 11:59:26 PM UTC 24 |
491594794 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_lc_escalation.3456162392 |
|
|
Aug 28 11:59:16 PM UTC 24 |
Aug 28 11:59:29 PM UTC 24 |
4459751060 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_access_during_key_req.2155996591 |
|
|
Aug 28 11:46:42 PM UTC 24 |
Aug 28 11:59:30 PM UTC 24 |
15954993098 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_all.3267856297 |
|
|
Aug 28 11:56:57 PM UTC 24 |
Aug 28 11:59:42 PM UTC 24 |
4651373375 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_all.2085995490 |
|
|
Aug 28 11:28:06 PM UTC 24 |
Aug 28 11:59:43 PM UTC 24 |
65065826702 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_ram_cfg.130279050 |
|
|
Aug 28 11:59:43 PM UTC 24 |
Aug 28 11:59:45 PM UTC 24 |
34394938 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_regwen.1628591112 |
|
|
Aug 28 11:49:13 PM UTC 24 |
Aug 28 11:59:50 PM UTC 24 |
76590355473 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_partial_access.948795468 |
|
|
Aug 28 11:59:03 PM UTC 24 |
Aug 28 11:59:53 PM UTC 24 |
1658898531 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_mem_walk.2164149572 |
|
|
Aug 28 11:59:44 PM UTC 24 |
Aug 28 11:59:54 PM UTC 24 |
550344871 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_mem_partial_access.2089552226 |
|
|
Aug 28 11:59:46 PM UTC 24 |
Aug 28 11:59:54 PM UTC 24 |
500182985 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_alert_test.1771086056 |
|
|
Aug 28 11:59:55 PM UTC 24 |
Aug 28 11:59:57 PM UTC 24 |
33225237 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.1801458083 |
|
|
Aug 28 11:58:53 PM UTC 24 |
Aug 29 12:00:03 AM UTC 24 |
7525594443 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_throughput_w_partial_write.4077981858 |
|
|
Aug 28 11:59:11 PM UTC 24 |
Aug 29 12:00:10 AM UTC 24 |
236547914 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_smoke.93988624 |
|
|
Aug 28 11:59:55 PM UTC 24 |
Aug 29 12:00:11 AM UTC 24 |
5213892084 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_all.748238441 |
|
|
Aug 28 11:08:42 PM UTC 24 |
Aug 29 12:00:24 AM UTC 24 |
37228408959 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_regwen.1603885425 |
|
|
Aug 28 11:48:03 PM UTC 24 |
Aug 29 12:00:29 AM UTC 24 |
26887497500 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.605852243 |
|
|
Aug 28 11:59:50 PM UTC 24 |
Aug 29 12:00:33 AM UTC 24 |
1444045477 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_max_throughput.2722990964 |
|
|
Aug 29 12:00:29 AM UTC 24 |
Aug 29 12:00:34 AM UTC 24 |
164137149 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_bijection.3712724413 |
|
|
Aug 29 12:00:06 AM UTC 24 |
Aug 29 12:00:40 AM UTC 24 |
1781340381 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_lc_escalation.2981245966 |
|
|
Aug 29 12:00:34 AM UTC 24 |
Aug 29 12:00:41 AM UTC 24 |
661417874 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_throughput_w_partial_write.1163226086 |
|
|
Aug 29 12:00:33 AM UTC 24 |
Aug 29 12:00:45 AM UTC 24 |
146795910 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_max_throughput.2723848887 |
|
|
Aug 28 11:59:10 PM UTC 24 |
Aug 29 12:00:49 AM UTC 24 |
156769303 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_ram_cfg.3594340976 |
|
|
Aug 29 12:00:50 AM UTC 24 |
Aug 29 12:00:52 AM UTC 24 |
135822667 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_regwen.2654944521 |
|
|
Aug 28 11:44:17 PM UTC 24 |
Aug 29 12:00:53 AM UTC 24 |
11344287316 ps |
| T91 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_mem_partial_access.1500017224 |
|
|
Aug 29 12:00:53 AM UTC 24 |
Aug 29 12:00:58 AM UTC 24 |
240253027 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_regwen.1348961901 |
|
|
Aug 28 11:56:45 PM UTC 24 |
Aug 29 12:01:05 AM UTC 24 |
1600759356 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_partial_access_b2b.4281713653 |
|
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Aug 28 11:55:13 PM UTC 24 |
Aug 29 12:01:08 AM UTC 24 |
22917079351 ps |