| T803 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_mem_walk.3285659921 |
|
|
Aug 29 12:00:53 AM UTC 24 |
Aug 29 12:01:10 AM UTC 24 |
916325561 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_alert_test.1291511239 |
|
|
Aug 29 12:01:09 AM UTC 24 |
Aug 29 12:01:11 AM UTC 24 |
12418967 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_all.1458114538 |
|
|
Aug 28 11:40:48 PM UTC 24 |
Aug 29 12:01:26 AM UTC 24 |
10417167878 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_smoke.593035738 |
|
|
Aug 29 12:01:11 AM UTC 24 |
Aug 29 12:01:31 AM UTC 24 |
5369828763 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_partial_access.345154988 |
|
|
Aug 29 12:00:12 AM UTC 24 |
Aug 29 12:01:43 AM UTC 24 |
466767545 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_pipeline.1059305176 |
|
|
Aug 28 11:59:02 PM UTC 24 |
Aug 29 12:01:56 AM UTC 24 |
2714479004 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_multiple_keys.927622820 |
|
|
Aug 28 11:59:58 PM UTC 24 |
Aug 29 12:02:03 AM UTC 24 |
2132880333 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_pipeline.117833947 |
|
|
Aug 28 11:56:05 PM UTC 24 |
Aug 29 12:02:06 AM UTC 24 |
44483456427 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_partial_access.1295524337 |
|
|
Aug 29 12:01:44 AM UTC 24 |
Aug 29 12:02:10 AM UTC 24 |
1826189341 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_throughput_w_partial_write.85628850 |
|
|
Aug 29 12:02:06 AM UTC 24 |
Aug 29 12:02:11 AM UTC 24 |
356898711 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_max_throughput.2976305363 |
|
|
Aug 29 12:02:03 AM UTC 24 |
Aug 29 12:02:13 AM UTC 24 |
59954299 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_lc_escalation.3647249628 |
|
|
Aug 29 12:02:11 AM UTC 24 |
Aug 29 12:02:16 AM UTC 24 |
558486793 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_bijection.32583618 |
|
|
Aug 29 12:01:27 AM UTC 24 |
Aug 29 12:02:26 AM UTC 24 |
2507653204 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_ram_cfg.2750337684 |
|
|
Aug 29 12:02:27 AM UTC 24 |
Aug 29 12:02:29 AM UTC 24 |
30639475 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_mem_walk.3268513870 |
|
|
Aug 29 12:02:30 AM UTC 24 |
Aug 29 12:02:39 AM UTC 24 |
237524894 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_mem_partial_access.3151587908 |
|
|
Aug 29 12:02:40 AM UTC 24 |
Aug 29 12:02:46 AM UTC 24 |
110934786 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_multiple_keys.1548866762 |
|
|
Aug 29 12:01:13 AM UTC 24 |
Aug 29 12:02:55 AM UTC 24 |
5256400462 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3691638471 |
|
|
Aug 29 12:02:47 AM UTC 24 |
Aug 29 12:02:56 AM UTC 24 |
623501237 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_alert_test.1302137780 |
|
|
Aug 29 12:02:58 AM UTC 24 |
Aug 29 12:03:00 AM UTC 24 |
17049254 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_pipeline.1703361354 |
|
|
Aug 29 12:00:11 AM UTC 24 |
Aug 29 12:03:03 AM UTC 24 |
3111140198 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_pipeline.2663350321 |
|
|
Aug 28 11:57:38 PM UTC 24 |
Aug 29 12:03:05 AM UTC 24 |
3039840482 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_smoke.2906708277 |
|
|
Aug 29 12:03:01 AM UTC 24 |
Aug 29 12:03:06 AM UTC 24 |
152456932 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_access_during_key_req.3450279746 |
|
|
Aug 28 11:41:38 PM UTC 24 |
Aug 29 12:03:17 AM UTC 24 |
2658021167 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_access_during_key_req.3318544651 |
|
|
Aug 28 11:44:13 PM UTC 24 |
Aug 29 12:03:22 AM UTC 24 |
4030662331 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_regwen.236301607 |
|
|
Aug 28 11:40:27 PM UTC 24 |
Aug 29 12:03:23 AM UTC 24 |
50559434922 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_bijection.2172967267 |
|
|
Aug 29 12:03:06 AM UTC 24 |
Aug 29 12:03:44 AM UTC 24 |
2017361893 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_executable.924363528 |
|
|
Aug 28 11:59:30 PM UTC 24 |
Aug 29 12:03:50 AM UTC 24 |
2963816196 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_max_throughput.2204746394 |
|
|
Aug 29 12:03:23 AM UTC 24 |
Aug 29 12:03:50 AM UTC 24 |
405315886 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_lc_escalation.3081771254 |
|
|
Aug 29 12:03:51 AM UTC 24 |
Aug 29 12:03:57 AM UTC 24 |
1367542844 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_regwen.1957350701 |
|
|
Aug 28 11:51:34 PM UTC 24 |
Aug 29 12:04:20 AM UTC 24 |
9367013962 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_executable.4135418482 |
|
|
Aug 28 11:42:51 PM UTC 24 |
Aug 29 12:04:21 AM UTC 24 |
15838852833 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_ram_cfg.2257724472 |
|
|
Aug 29 12:04:22 AM UTC 24 |
Aug 29 12:04:25 AM UTC 24 |
119947605 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_partial_access.2940705706 |
|
|
Aug 29 12:03:18 AM UTC 24 |
Aug 29 12:04:27 AM UTC 24 |
1286298669 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_mem_partial_access.2431531097 |
|
|
Aug 29 12:04:28 AM UTC 24 |
Aug 29 12:04:38 AM UTC 24 |
648699002 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_throughput_w_partial_write.968731507 |
|
|
Aug 29 12:03:46 AM UTC 24 |
Aug 29 12:04:38 AM UTC 24 |
115395389 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_mem_walk.4254324214 |
|
|
Aug 29 12:04:25 AM UTC 24 |
Aug 29 12:04:38 AM UTC 24 |
590102439 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_partial_access_b2b.3919956068 |
|
|
Aug 28 11:56:16 PM UTC 24 |
Aug 29 12:04:42 AM UTC 24 |
15461043789 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_alert_test.236551380 |
|
|
Aug 29 12:04:40 AM UTC 24 |
Aug 29 12:04:42 AM UTC 24 |
75104644 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_smoke.3908169154 |
|
|
Aug 29 12:04:41 AM UTC 24 |
Aug 29 12:04:48 AM UTC 24 |
276124491 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_multiple_keys.2040144764 |
|
|
Aug 28 11:58:58 PM UTC 24 |
Aug 29 12:04:48 AM UTC 24 |
8028763395 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_executable.3654411616 |
|
|
Aug 28 11:55:41 PM UTC 24 |
Aug 29 12:04:57 AM UTC 24 |
15619563159 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_access_during_key_req.191441934 |
|
|
Aug 28 11:51:30 PM UTC 24 |
Aug 29 12:05:05 AM UTC 24 |
11571649519 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_partial_access.2878159533 |
|
|
Aug 29 12:04:49 AM UTC 24 |
Aug 29 12:05:09 AM UTC 24 |
651161769 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_all.3792937050 |
|
|
Aug 28 11:30:21 PM UTC 24 |
Aug 29 12:05:13 AM UTC 24 |
28714257508 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_bijection.4106571273 |
|
|
Aug 29 12:04:43 AM UTC 24 |
Aug 29 12:05:22 AM UTC 24 |
3674513497 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_lc_escalation.746022008 |
|
|
Aug 29 12:05:14 AM UTC 24 |
Aug 29 12:05:28 AM UTC 24 |
956431798 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_multiple_keys.3445995290 |
|
|
Aug 28 11:36:06 PM UTC 24 |
Aug 29 12:05:34 AM UTC 24 |
24845332800 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_throughput_w_partial_write.1790584921 |
|
|
Aug 29 12:05:11 AM UTC 24 |
Aug 29 12:05:51 AM UTC 24 |
456563113 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_ram_cfg.274112266 |
|
|
Aug 29 12:05:52 AM UTC 24 |
Aug 29 12:05:54 AM UTC 24 |
30320544 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_mem_walk.3677600349 |
|
|
Aug 29 12:05:55 AM UTC 24 |
Aug 29 12:06:02 AM UTC 24 |
138076635 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_mem_partial_access.4186338956 |
|
|
Aug 29 12:06:03 AM UTC 24 |
Aug 29 12:06:09 AM UTC 24 |
416832491 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_max_throughput.2103983756 |
|
|
Aug 29 12:05:05 AM UTC 24 |
Aug 29 12:06:10 AM UTC 24 |
443585801 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_partial_access_b2b.2689029782 |
|
|
Aug 28 11:57:57 PM UTC 24 |
Aug 29 12:06:11 AM UTC 24 |
10878905784 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_alert_test.663578478 |
|
|
Aug 29 12:06:12 AM UTC 24 |
Aug 29 12:06:14 AM UTC 24 |
21958174 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_pipeline.2355959637 |
|
|
Aug 29 12:03:07 AM UTC 24 |
Aug 29 12:06:14 AM UTC 24 |
19659075896 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_partial_access_b2b.412036590 |
|
|
Aug 29 12:00:24 AM UTC 24 |
Aug 29 12:06:16 AM UTC 24 |
20532165690 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_access_during_key_req.1459782233 |
|
|
Aug 28 11:55:36 PM UTC 24 |
Aug 29 12:06:17 AM UTC 24 |
9075326327 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_partial_access_b2b.1495862860 |
|
|
Aug 29 12:03:22 AM UTC 24 |
Aug 29 12:06:24 AM UTC 24 |
2027624941 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_multiple_keys.3465682313 |
|
|
Aug 29 12:06:15 AM UTC 24 |
Aug 29 12:06:32 AM UTC 24 |
747154232 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_executable.3435071518 |
|
|
Aug 28 11:49:12 PM UTC 24 |
Aug 29 12:06:33 AM UTC 24 |
40799010370 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_smoke.34801506 |
|
|
Aug 29 12:06:15 AM UTC 24 |
Aug 29 12:07:01 AM UTC 24 |
535668702 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_regwen.2135688249 |
|
|
Aug 28 11:52:44 PM UTC 24 |
Aug 29 12:07:03 AM UTC 24 |
36923696230 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_bijection.3731228152 |
|
|
Aug 29 12:06:16 AM UTC 24 |
Aug 29 12:07:11 AM UTC 24 |
3190565526 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_lc_escalation.1953944290 |
|
|
Aug 29 12:07:04 AM UTC 24 |
Aug 29 12:07:13 AM UTC 24 |
1920917949 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_executable.114594691 |
|
|
Aug 28 11:46:46 PM UTC 24 |
Aug 29 12:07:15 AM UTC 24 |
13311254200 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_multiple_keys.1652748831 |
|
|
Aug 28 11:52:07 PM UTC 24 |
Aug 29 12:07:29 AM UTC 24 |
108139197155 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_ram_cfg.2923260643 |
|
|
Aug 29 12:07:30 AM UTC 24 |
Aug 29 12:07:32 AM UTC 24 |
164272413 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_mem_walk.510197943 |
|
|
Aug 29 12:07:33 AM UTC 24 |
Aug 29 12:07:40 AM UTC 24 |
468456912 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.2582209493 |
|
|
Aug 29 12:04:38 AM UTC 24 |
Aug 29 12:07:42 AM UTC 24 |
453171277 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_partial_access_b2b.340410148 |
|
|
Aug 28 11:59:07 PM UTC 24 |
Aug 29 12:07:45 AM UTC 24 |
139625662961 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_mem_partial_access.1019621875 |
|
|
Aug 29 12:07:42 AM UTC 24 |
Aug 29 12:07:47 AM UTC 24 |
392605638 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_alert_test.3966849680 |
|
|
Aug 29 12:07:48 AM UTC 24 |
Aug 29 12:07:50 AM UTC 24 |
34451180 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_partial_access.248876200 |
|
|
Aug 29 12:06:24 AM UTC 24 |
Aug 29 12:07:57 AM UTC 24 |
2444807327 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_max_throughput.1091827550 |
|
|
Aug 29 12:06:34 AM UTC 24 |
Aug 29 12:07:59 AM UTC 24 |
250199476 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_executable.2315340879 |
|
|
Aug 28 11:52:41 PM UTC 24 |
Aug 29 12:08:03 AM UTC 24 |
9750374421 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_throughput_w_partial_write.3060776212 |
|
|
Aug 29 12:07:02 AM UTC 24 |
Aug 29 12:08:21 AM UTC 24 |
146656182 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_all.1362515161 |
|
|
Aug 28 11:44:59 PM UTC 24 |
Aug 29 12:08:57 AM UTC 24 |
155829688897 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_pipeline.2803446991 |
|
|
Aug 29 12:01:32 AM UTC 24 |
Aug 29 12:09:20 AM UTC 24 |
21524355811 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_pipeline.931648281 |
|
|
Aug 29 12:06:17 AM UTC 24 |
Aug 29 12:09:22 AM UTC 24 |
7132893720 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_all.3094144426 |
|
|
Aug 28 11:43:33 PM UTC 24 |
Aug 29 12:09:23 AM UTC 24 |
164536865435 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_pipeline.2327221696 |
|
|
Aug 29 12:04:48 AM UTC 24 |
Aug 29 12:09:30 AM UTC 24 |
4763262832 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_executable.2646382112 |
|
|
Aug 28 11:37:04 PM UTC 24 |
Aug 29 12:09:46 AM UTC 24 |
23358495891 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_partial_access_b2b.2860301340 |
|
|
Aug 29 12:04:57 AM UTC 24 |
Aug 29 12:09:52 AM UTC 24 |
49344360323 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.3158583364 |
|
|
Aug 29 12:07:43 AM UTC 24 |
Aug 29 12:10:07 AM UTC 24 |
11293309997 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_executable.3042807563 |
|
|
Aug 28 11:58:29 PM UTC 24 |
Aug 29 12:10:23 AM UTC 24 |
45365048828 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_access_during_key_req.1760003789 |
|
|
Aug 28 11:47:54 PM UTC 24 |
Aug 29 12:10:36 AM UTC 24 |
22710938279 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_executable.3874898673 |
|
|
Aug 29 12:02:14 AM UTC 24 |
Aug 29 12:10:43 AM UTC 24 |
3865054952 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_access_during_key_req.709611611 |
|
|
Aug 28 11:52:39 PM UTC 24 |
Aug 29 12:10:51 AM UTC 24 |
3217606783 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_access_during_key_req.4214681420 |
|
|
Aug 28 11:56:44 PM UTC 24 |
Aug 29 12:10:52 AM UTC 24 |
3331603376 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_access_during_key_req.2202312204 |
|
|
Aug 28 11:59:27 PM UTC 24 |
Aug 29 12:11:13 AM UTC 24 |
4590635592 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all.3982682648 |
|
|
Aug 28 11:01:18 PM UTC 24 |
Aug 29 12:11:36 AM UTC 24 |
86809017489 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_partial_access_b2b.1257058119 |
|
|
Aug 29 12:06:33 AM UTC 24 |
Aug 29 12:11:45 AM UTC 24 |
3808052929 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_all.1560132965 |
|
|
Aug 28 11:22:40 PM UTC 24 |
Aug 29 12:11:53 AM UTC 24 |
40918158221 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_access_during_key_req.2145515721 |
|
|
Aug 29 12:02:12 AM UTC 24 |
Aug 29 12:12:18 AM UTC 24 |
2535782401 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_executable.3994923012 |
|
|
Aug 28 11:51:32 PM UTC 24 |
Aug 29 12:12:19 AM UTC 24 |
11511790899 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_executable.3374713027 |
|
|
Aug 29 12:00:42 AM UTC 24 |
Aug 29 12:12:26 AM UTC 24 |
44043814288 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_partial_access_b2b.2086064225 |
|
|
Aug 29 12:01:56 AM UTC 24 |
Aug 29 12:12:30 AM UTC 24 |
81224924679 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_executable.1223791067 |
|
|
Aug 29 12:03:58 AM UTC 24 |
Aug 29 12:13:08 AM UTC 24 |
41694211053 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_multiple_keys.1792831577 |
|
|
Aug 28 11:54:07 PM UTC 24 |
Aug 29 12:13:21 AM UTC 24 |
83888335305 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_executable.3598718835 |
|
|
Aug 29 12:05:29 AM UTC 24 |
Aug 29 12:13:24 AM UTC 24 |
1179386454 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_regwen.4116308804 |
|
|
Aug 28 11:59:31 PM UTC 24 |
Aug 29 12:13:41 AM UTC 24 |
19901394437 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_regwen.1278820204 |
|
|
Aug 29 12:04:21 AM UTC 24 |
Aug 29 12:13:56 AM UTC 24 |
20743235584 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_multiple_keys.253453853 |
|
|
Aug 28 11:57:21 PM UTC 24 |
Aug 29 12:14:23 AM UTC 24 |
3453556519 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_regwen.2551043984 |
|
|
Aug 29 12:00:46 AM UTC 24 |
Aug 29 12:14:36 AM UTC 24 |
29834822720 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_regwen.901301795 |
|
|
Aug 28 11:46:46 PM UTC 24 |
Aug 29 12:15:04 AM UTC 24 |
99403427493 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_regwen.2586471485 |
|
|
Aug 29 12:02:17 AM UTC 24 |
Aug 29 12:15:26 AM UTC 24 |
4798186736 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_access_during_key_req.294547394 |
|
|
Aug 29 12:07:12 AM UTC 24 |
Aug 29 12:15:27 AM UTC 24 |
2379971511 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_regwen.662874388 |
|
|
Aug 28 11:55:46 PM UTC 24 |
Aug 29 12:16:03 AM UTC 24 |
97883200119 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_all.2517009641 |
|
|
Aug 28 11:36:01 PM UTC 24 |
Aug 29 12:16:32 AM UTC 24 |
51176459434 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_all.1122402771 |
|
|
Aug 28 11:47:17 PM UTC 24 |
Aug 29 12:16:41 AM UTC 24 |
106725199631 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_access_during_key_req.3706348505 |
|
|
Aug 28 11:58:24 PM UTC 24 |
Aug 29 12:16:45 AM UTC 24 |
5904650094 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_executable.1305173768 |
|
|
Aug 28 11:56:45 PM UTC 24 |
Aug 29 12:17:07 AM UTC 24 |
3427804481 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_multiple_keys.4249318533 |
|
|
Aug 28 11:56:04 PM UTC 24 |
Aug 29 12:17:41 AM UTC 24 |
207521082679 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_all.1408621361 |
|
|
Aug 28 11:59:54 PM UTC 24 |
Aug 29 12:17:47 AM UTC 24 |
19579128524 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.786389339 |
|
|
Aug 29 12:06:10 AM UTC 24 |
Aug 29 12:18:03 AM UTC 24 |
3718730725 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_access_during_key_req.2523610199 |
|
|
Aug 29 12:03:52 AM UTC 24 |
Aug 29 12:18:05 AM UTC 24 |
3671861791 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_access_during_key_req.3524251344 |
|
|
Aug 29 12:05:23 AM UTC 24 |
Aug 29 12:18:24 AM UTC 24 |
7212378064 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_all.2989551716 |
|
|
Aug 28 11:42:07 PM UTC 24 |
Aug 29 12:19:47 AM UTC 24 |
57346792355 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_executable.1926866782 |
|
|
Aug 29 12:07:14 AM UTC 24 |
Aug 29 12:19:50 AM UTC 24 |
4803897129 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_all.2305900888 |
|
|
Aug 28 11:21:32 PM UTC 24 |
Aug 29 12:20:03 AM UTC 24 |
39590399880 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_multiple_keys.3316340805 |
|
|
Aug 29 12:04:43 AM UTC 24 |
Aug 29 12:21:46 AM UTC 24 |
11550987506 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_multiple_keys.910343833 |
|
|
Aug 29 12:03:04 AM UTC 24 |
Aug 29 12:21:58 AM UTC 24 |
32887518977 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_all.2277436922 |
|
|
Aug 28 11:24:46 PM UTC 24 |
Aug 29 12:22:20 AM UTC 24 |
9700024112 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_all.1996150131 |
|
|
Aug 29 12:04:39 AM UTC 24 |
Aug 29 12:22:24 AM UTC 24 |
86690131480 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_regwen.1586334117 |
|
|
Aug 29 12:05:35 AM UTC 24 |
Aug 29 12:22:27 AM UTC 24 |
3565338217 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_regwen.299231994 |
|
|
Aug 29 12:07:16 AM UTC 24 |
Aug 29 12:22:45 AM UTC 24 |
32890977441 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_all.2889676950 |
|
|
Aug 28 11:56:02 PM UTC 24 |
Aug 29 12:22:57 AM UTC 24 |
95628116925 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_access_during_key_req.3821112629 |
|
|
Aug 29 12:00:41 AM UTC 24 |
Aug 29 12:24:19 AM UTC 24 |
10237929918 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_all.1493693661 |
|
|
Aug 28 11:29:00 PM UTC 24 |
Aug 29 12:24:19 AM UTC 24 |
180625105773 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_all.3895252327 |
|
|
Aug 29 12:01:05 AM UTC 24 |
Aug 29 12:25:08 AM UTC 24 |
18040673432 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_regwen.2452785670 |
|
|
Aug 28 11:58:33 PM UTC 24 |
Aug 29 12:26:34 AM UTC 24 |
4723281961 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_all.1924570300 |
|
|
Aug 28 11:37:25 PM UTC 24 |
Aug 29 12:30:30 AM UTC 24 |
9853295910 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_all.1445318543 |
|
|
Aug 28 11:17:02 PM UTC 24 |
Aug 29 12:30:44 AM UTC 24 |
55602733895 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_all.843823092 |
|
|
Aug 28 11:39:13 PM UTC 24 |
Aug 29 12:31:01 AM UTC 24 |
37001987318 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_all.1166517833 |
|
|
Aug 29 12:02:55 AM UTC 24 |
Aug 29 12:31:12 AM UTC 24 |
96693237181 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_all.1157546266 |
|
|
Aug 28 11:58:54 PM UTC 24 |
Aug 29 12:36:53 AM UTC 24 |
152687996178 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_all.455712547 |
|
|
Aug 29 12:07:46 AM UTC 24 |
Aug 29 12:39:38 AM UTC 24 |
14071003974 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_all.3832899238 |
|
|
Aug 28 11:34:01 PM UTC 24 |
Aug 29 12:39:46 AM UTC 24 |
53029843345 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_all.656491837 |
|
|
Aug 29 12:06:11 AM UTC 24 |
Aug 29 12:45:30 AM UTC 24 |
88426353050 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_all.2827020183 |
|
|
Aug 28 11:32:19 PM UTC 24 |
Aug 29 12:45:37 AM UTC 24 |
173288032697 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_all.1270287273 |
|
|
Aug 28 11:50:10 PM UTC 24 |
Aug 29 12:50:41 AM UTC 24 |
44250660463 ps |
| T57 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.981137547 |
|
|
Aug 29 12:07:51 AM UTC 24 |
Aug 29 12:07:55 AM UTC 24 |
777316384 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2135394234 |
|
|
Aug 29 12:07:56 AM UTC 24 |
Aug 29 12:08:01 AM UTC 24 |
71898063 ps |
| T58 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3636886505 |
|
|
Aug 29 12:08:00 AM UTC 24 |
Aug 29 12:08:01 AM UTC 24 |
54717588 ps |
| T50 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1904578842 |
|
|
Aug 29 12:07:58 AM UTC 24 |
Aug 29 12:08:03 AM UTC 24 |
239078595 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1278893628 |
|
|
Aug 29 12:08:02 AM UTC 24 |
Aug 29 12:08:04 AM UTC 24 |
44078185 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3490695011 |
|
|
Aug 29 12:08:04 AM UTC 24 |
Aug 29 12:08:06 AM UTC 24 |
51232052 ps |
| T101 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3444901988 |
|
|
Aug 29 12:08:04 AM UTC 24 |
Aug 29 12:08:06 AM UTC 24 |
32924148 ps |
| T144 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.456277889 |
|
|
Aug 29 12:08:03 AM UTC 24 |
Aug 29 12:08:07 AM UTC 24 |
1269007299 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.600808978 |
|
|
Aug 29 12:08:05 AM UTC 24 |
Aug 29 12:08:08 AM UTC 24 |
45834751 ps |
| T73 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.664307258 |
|
|
Aug 29 12:08:06 AM UTC 24 |
Aug 29 12:08:10 AM UTC 24 |
763777454 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2000397622 |
|
|
Aug 29 12:08:09 AM UTC 24 |
Aug 29 12:08:11 AM UTC 24 |
122790248 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.291470876 |
|
|
Aug 29 12:08:07 AM UTC 24 |
Aug 29 12:08:12 AM UTC 24 |
68928265 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.758271419 |
|
|
Aug 29 12:08:10 AM UTC 24 |
Aug 29 12:08:12 AM UTC 24 |
40332906 ps |
| T51 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1551200646 |
|
|
Aug 29 12:08:08 AM UTC 24 |
Aug 29 12:08:13 AM UTC 24 |
153937877 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1121950217 |
|
|
Aug 29 12:08:13 AM UTC 24 |
Aug 29 12:08:15 AM UTC 24 |
40484535 ps |
| T102 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1503161254 |
|
|
Aug 29 12:08:14 AM UTC 24 |
Aug 29 12:08:16 AM UTC 24 |
37379536 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2263606705 |
|
|
Aug 29 12:08:13 AM UTC 24 |
Aug 29 12:08:16 AM UTC 24 |
163992848 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.9484846 |
|
|
Aug 29 12:08:14 AM UTC 24 |
Aug 29 12:08:18 AM UTC 24 |
40365025 ps |
| T78 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1534382647 |
|
|
Aug 29 12:08:15 AM UTC 24 |
Aug 29 12:08:19 AM UTC 24 |
1514394283 ps |
| T52 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.4213638216 |
|
|
Aug 29 12:08:17 AM UTC 24 |
Aug 29 12:08:21 AM UTC 24 |
276677536 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2602716189 |
|
|
Aug 29 12:08:19 AM UTC 24 |
Aug 29 12:08:21 AM UTC 24 |
19005984 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3221715669 |
|
|
Aug 29 12:08:20 AM UTC 24 |
Aug 29 12:08:22 AM UTC 24 |
30460676 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3910922513 |
|
|
Aug 29 12:08:22 AM UTC 24 |
Aug 29 12:08:24 AM UTC 24 |
21912338 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.894113114 |
|
|
Aug 29 12:08:17 AM UTC 24 |
Aug 29 12:08:24 AM UTC 24 |
199084742 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.222377779 |
|
|
Aug 29 12:08:22 AM UTC 24 |
Aug 29 12:08:24 AM UTC 24 |
25725622 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2009481291 |
|
|
Aug 29 12:08:22 AM UTC 24 |
Aug 29 12:08:25 AM UTC 24 |
177809476 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1385812590 |
|
|
Aug 29 12:08:23 AM UTC 24 |
Aug 29 12:08:25 AM UTC 24 |
116250839 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1081828921 |
|
|
Aug 29 12:08:26 AM UTC 24 |
Aug 29 12:08:28 AM UTC 24 |
47835606 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.852789177 |
|
|
Aug 29 12:08:24 AM UTC 24 |
Aug 29 12:08:28 AM UTC 24 |
131896667 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3781247882 |
|
|
Aug 29 12:08:24 AM UTC 24 |
Aug 29 12:08:28 AM UTC 24 |
22005407 ps |
| T103 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.867182059 |
|
|
Aug 29 12:08:27 AM UTC 24 |
Aug 29 12:08:29 AM UTC 24 |
13885479 ps |
| T82 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.40771336 |
|
|
Aug 29 12:08:24 AM UTC 24 |
Aug 29 12:08:30 AM UTC 24 |
768706887 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2944300043 |
|
|
Aug 29 12:08:29 AM UTC 24 |
Aug 29 12:08:31 AM UTC 24 |
66835079 ps |
| T104 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1764064199 |
|
|
Aug 29 12:08:30 AM UTC 24 |
Aug 29 12:08:32 AM UTC 24 |
17802673 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2412143173 |
|
|
Aug 29 12:08:30 AM UTC 24 |
Aug 29 12:08:32 AM UTC 24 |
98528064 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2781747119 |
|
|
Aug 29 12:08:28 AM UTC 24 |
Aug 29 12:08:32 AM UTC 24 |
155264227 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1816735227 |
|
|
Aug 29 12:08:32 AM UTC 24 |
Aug 29 12:08:35 AM UTC 24 |
116242763 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_rw.913090798 |
|
|
Aug 29 12:08:33 AM UTC 24 |
Aug 29 12:08:35 AM UTC 24 |
53043800 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1935707022 |
|
|
Aug 29 12:08:33 AM UTC 24 |
Aug 29 12:08:35 AM UTC 24 |
18357832 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1645570285 |
|
|
Aug 29 12:08:31 AM UTC 24 |
Aug 29 12:08:35 AM UTC 24 |
963901989 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_errors.848728013 |
|
|
Aug 29 12:08:32 AM UTC 24 |
Aug 29 12:08:35 AM UTC 24 |
209648515 ps |
| T85 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1378249204 |
|
|
Aug 29 12:08:37 AM UTC 24 |
Aug 29 12:08:39 AM UTC 24 |
43528288 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3319576008 |
|
|
Aug 29 12:08:37 AM UTC 24 |
Aug 29 12:08:39 AM UTC 24 |
108482455 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.617768184 |
|
|
Aug 29 12:08:37 AM UTC 24 |
Aug 29 12:08:40 AM UTC 24 |
1899948462 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2560778688 |
|
|
Aug 29 12:08:37 AM UTC 24 |
Aug 29 12:08:42 AM UTC 24 |
292708115 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2788842714 |
|
|
Aug 29 12:08:40 AM UTC 24 |
Aug 29 12:08:42 AM UTC 24 |
45278455 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2636564733 |
|
|
Aug 29 12:08:39 AM UTC 24 |
Aug 29 12:08:43 AM UTC 24 |
186080624 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2433139755 |
|
|
Aug 29 12:08:42 AM UTC 24 |
Aug 29 12:08:43 AM UTC 24 |
30339865 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2817930595 |
|
|
Aug 29 12:08:39 AM UTC 24 |
Aug 29 12:08:44 AM UTC 24 |
34790796 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1614765509 |
|
|
Aug 29 12:08:43 AM UTC 24 |
Aug 29 12:08:45 AM UTC 24 |
41350151 ps |
| T98 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.419732394 |
|
|
Aug 29 12:08:43 AM UTC 24 |
Aug 29 12:08:47 AM UTC 24 |
847568078 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_rw.33261188 |
|
|
Aug 29 12:08:45 AM UTC 24 |
Aug 29 12:08:47 AM UTC 24 |
28061811 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.917570124 |
|
|
Aug 29 12:08:44 AM UTC 24 |
Aug 29 12:08:48 AM UTC 24 |
1472885856 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3497727269 |
|
|
Aug 29 12:08:44 AM UTC 24 |
Aug 29 12:08:48 AM UTC 24 |
74065817 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3299568458 |
|
|
Aug 29 12:08:46 AM UTC 24 |
Aug 29 12:08:49 AM UTC 24 |
19316079 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_rw.113081623 |
|
|
Aug 29 12:08:50 AM UTC 24 |
Aug 29 12:08:52 AM UTC 24 |
17673517 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2645772880 |
|
|
Aug 29 12:08:48 AM UTC 24 |
Aug 29 12:08:53 AM UTC 24 |
92073742 ps |
| T141 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2905374931 |
|
|
Aug 29 12:08:50 AM UTC 24 |
Aug 29 12:08:54 AM UTC 24 |
410727091 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1196946635 |
|
|
Aug 29 12:08:53 AM UTC 24 |
Aug 29 12:08:55 AM UTC 24 |
25241986 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3843373423 |
|
|
Aug 29 12:08:50 AM UTC 24 |
Aug 29 12:08:55 AM UTC 24 |
894624888 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3994656957 |
|
|
Aug 29 12:08:48 AM UTC 24 |
Aug 29 12:08:57 AM UTC 24 |
6645298219 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2012964444 |
|
|
Aug 29 12:08:54 AM UTC 24 |
Aug 29 12:08:57 AM UTC 24 |
97872373 ps |
| T99 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3036691132 |
|
|
Aug 29 12:08:58 AM UTC 24 |
Aug 29 12:09:00 AM UTC 24 |
14239002 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3208925826 |
|
|
Aug 29 12:08:58 AM UTC 24 |
Aug 29 12:09:00 AM UTC 24 |
12419387 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.4151183908 |
|
|
Aug 29 12:08:58 AM UTC 24 |
Aug 29 12:09:01 AM UTC 24 |
29198364 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3712921941 |
|
|
Aug 29 12:08:55 AM UTC 24 |
Aug 29 12:09:01 AM UTC 24 |
253942065 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3435967402 |
|
|
Aug 29 12:08:57 AM UTC 24 |
Aug 29 12:09:01 AM UTC 24 |
831969494 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3148071921 |
|
|
Aug 29 12:08:55 AM UTC 24 |
Aug 29 12:09:02 AM UTC 24 |
1570622964 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.149435843 |
|
|
Aug 29 12:09:02 AM UTC 24 |
Aug 29 12:09:04 AM UTC 24 |
32515791 ps |
| T93 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_rw.4294410570 |
|
|
Aug 29 12:09:02 AM UTC 24 |
Aug 29 12:09:04 AM UTC 24 |
35778215 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2471641640 |
|
|
Aug 29 12:09:02 AM UTC 24 |
Aug 29 12:09:06 AM UTC 24 |
21675377 ps |
| T136 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1552166112 |
|
|
Aug 29 12:09:02 AM UTC 24 |
Aug 29 12:09:07 AM UTC 24 |
621841447 ps |
| T94 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2605932013 |
|
|
Aug 29 12:09:02 AM UTC 24 |
Aug 29 12:09:08 AM UTC 24 |
396290698 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1979906951 |
|
|
Aug 29 12:09:03 AM UTC 24 |
Aug 29 12:09:08 AM UTC 24 |
42865891 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3585411588 |
|
|
Aug 29 12:09:08 AM UTC 24 |
Aug 29 12:09:10 AM UTC 24 |
14682959 ps |
| T139 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1001086500 |
|
|
Aug 29 12:09:07 AM UTC 24 |
Aug 29 12:09:12 AM UTC 24 |
395350348 ps |
| T100 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1350604458 |
|
|
Aug 29 12:09:05 AM UTC 24 |
Aug 29 12:09:11 AM UTC 24 |
1677806043 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3519907080 |
|
|
Aug 29 12:09:06 AM UTC 24 |
Aug 29 12:09:12 AM UTC 24 |
39511046 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1235671975 |
|
|
Aug 29 12:09:10 AM UTC 24 |
Aug 29 12:09:12 AM UTC 24 |
14220208 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.199332844 |
|
|
Aug 29 12:09:10 AM UTC 24 |
Aug 29 12:09:13 AM UTC 24 |
146088007 ps |
| T95 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1234701893 |
|
|
Aug 29 12:09:13 AM UTC 24 |
Aug 29 12:09:15 AM UTC 24 |
47468161 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3498523961 |
|
|
Aug 29 12:09:13 AM UTC 24 |
Aug 29 12:09:15 AM UTC 24 |
39853427 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.4275938962 |
|
|
Aug 29 12:09:14 AM UTC 24 |
Aug 29 12:09:17 AM UTC 24 |
34725813 ps |
| T96 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.815641564 |
|
|
Aug 29 12:09:11 AM UTC 24 |
Aug 29 12:09:17 AM UTC 24 |
446551680 ps |
| T128 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1824589841 |
|
|
Aug 29 12:09:13 AM UTC 24 |
Aug 29 12:09:17 AM UTC 24 |
71957053 ps |
| T137 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2809003545 |
|
|
Aug 29 12:09:13 AM UTC 24 |
Aug 29 12:09:18 AM UTC 24 |
376238290 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.768410384 |
|
|
Aug 29 12:09:18 AM UTC 24 |
Aug 29 12:09:20 AM UTC 24 |
15467601 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.786511059 |
|
|
Aug 29 12:09:18 AM UTC 24 |
Aug 29 12:09:20 AM UTC 24 |
37599994 ps |
| T97 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.468362478 |
|
|
Aug 29 12:09:15 AM UTC 24 |
Aug 29 12:09:21 AM UTC 24 |
385861534 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3416339880 |
|
|
Aug 29 12:09:17 AM UTC 24 |
Aug 29 12:09:22 AM UTC 24 |
484142211 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1082778493 |
|
|
Aug 29 12:09:19 AM UTC 24 |
Aug 29 12:09:23 AM UTC 24 |
157440390 ps |
| T140 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1087068602 |
|
|
Aug 29 12:09:18 AM UTC 24 |
Aug 29 12:09:23 AM UTC 24 |
1163054468 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.373974195 |
|
|
Aug 29 12:09:23 AM UTC 24 |
Aug 29 12:09:25 AM UTC 24 |
24458416 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1805665163 |
|
|
Aug 29 12:09:23 AM UTC 24 |
Aug 29 12:09:25 AM UTC 24 |
46475062 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3189261245 |
|
|
Aug 29 12:09:22 AM UTC 24 |
Aug 29 12:09:27 AM UTC 24 |
778792953 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.109332642 |
|
|
Aug 29 12:09:24 AM UTC 24 |
Aug 29 12:09:27 AM UTC 24 |
254832025 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1266788426 |
|
|
Aug 29 12:09:22 AM UTC 24 |
Aug 29 12:09:28 AM UTC 24 |
37463203 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1351913801 |
|
|
Aug 29 12:09:25 AM UTC 24 |
Aug 29 12:09:28 AM UTC 24 |
1230099584 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2098575504 |
|
|
Aug 29 12:09:26 AM UTC 24 |
Aug 29 12:09:28 AM UTC 24 |
21209508 ps |
| T138 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3949188396 |
|
|
Aug 29 12:09:22 AM UTC 24 |
Aug 29 12:09:28 AM UTC 24 |
2540209801 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.622238926 |
|
|
Aug 29 12:09:26 AM UTC 24 |
Aug 29 12:09:28 AM UTC 24 |
12504662 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1483002658 |
|
|
Aug 29 12:09:25 AM UTC 24 |
Aug 29 12:09:29 AM UTC 24 |
386388719 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1337303031 |
|
|
Aug 29 12:09:27 AM UTC 24 |
Aug 29 12:09:30 AM UTC 24 |
52525052 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3690313979 |
|
|
Aug 29 12:09:29 AM UTC 24 |
Aug 29 12:09:31 AM UTC 24 |
92443578 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3457170846 |
|
|
Aug 29 12:09:29 AM UTC 24 |
Aug 29 12:09:31 AM UTC 24 |
126216681 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3204736757 |
|
|
Aug 29 12:09:29 AM UTC 24 |
Aug 29 12:09:31 AM UTC 24 |
31508924 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2693002364 |
|
|
Aug 29 12:09:25 AM UTC 24 |
Aug 29 12:09:32 AM UTC 24 |
264238495 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1799818954 |
|
|
Aug 29 12:09:29 AM UTC 24 |
Aug 29 12:09:33 AM UTC 24 |
800779182 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2868094929 |
|
|
Aug 29 12:09:29 AM UTC 24 |
Aug 29 12:09:33 AM UTC 24 |
168589383 ps |