| T314 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_multiple_keys.3420841493 |
|
|
Sep 24 09:57:16 PM UTC 24 |
Sep 24 09:58:59 PM UTC 24 |
2458230348 ps |
| T315 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_mem_partial_access.1875715320 |
|
|
Sep 24 09:59:00 PM UTC 24 |
Sep 24 09:59:09 PM UTC 24 |
375040572 ps |
| T316 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_mem_walk.3328328240 |
|
|
Sep 24 09:58:56 PM UTC 24 |
Sep 24 09:59:10 PM UTC 24 |
176059759 ps |
| T317 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_max_throughput.2363314646 |
|
|
Sep 24 09:58:07 PM UTC 24 |
Sep 24 09:59:13 PM UTC 24 |
393203208 ps |
| T318 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_alert_test.2973320377 |
|
|
Sep 24 09:59:12 PM UTC 24 |
Sep 24 09:59:13 PM UTC 24 |
28268898 ps |
| T319 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.3265664514 |
|
|
Sep 24 09:46:24 PM UTC 24 |
Sep 24 09:59:40 PM UTC 24 |
7187957473 ps |
| T139 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_regwen.2259446276 |
|
|
Sep 24 09:41:03 PM UTC 24 |
Sep 24 09:59:42 PM UTC 24 |
16408710731 ps |
| T320 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.2697796925 |
|
|
Sep 24 09:43:52 PM UTC 24 |
Sep 24 10:00:12 PM UTC 24 |
4058698358 ps |
| T321 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_partial_access_b2b.4223606166 |
|
|
Sep 24 09:52:07 PM UTC 24 |
Sep 24 10:00:12 PM UTC 24 |
59716710641 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all.383042008 |
|
|
Sep 24 09:43:20 PM UTC 24 |
Sep 24 10:00:19 PM UTC 24 |
274469199812 ps |
| T161 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_regwen.4166371317 |
|
|
Sep 24 09:40:18 PM UTC 24 |
Sep 24 10:00:22 PM UTC 24 |
38715318894 ps |
| T323 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_max_throughput.1642533892 |
|
|
Sep 24 10:00:20 PM UTC 24 |
Sep 24 10:00:22 PM UTC 24 |
116620465 ps |
| T147 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_executable.1972080435 |
|
|
Sep 24 09:56:38 PM UTC 24 |
Sep 24 10:00:26 PM UTC 24 |
2026870714 ps |
| T324 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_partial_access.2406210586 |
|
|
Sep 24 10:00:12 PM UTC 24 |
Sep 24 10:00:30 PM UTC 24 |
958355094 ps |
| T325 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_lc_escalation.2969080631 |
|
|
Sep 24 10:00:23 PM UTC 24 |
Sep 24 10:00:33 PM UTC 24 |
657645976 ps |
| T326 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_smoke.1516319776 |
|
|
Sep 24 09:59:14 PM UTC 24 |
Sep 24 10:00:37 PM UTC 24 |
2698257233 ps |
| T327 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_ram_cfg.3656887451 |
|
|
Sep 24 10:00:38 PM UTC 24 |
Sep 24 10:00:41 PM UTC 24 |
32120324 ps |
| T328 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_mem_walk.2733573663 |
|
|
Sep 24 10:00:41 PM UTC 24 |
Sep 24 10:00:50 PM UTC 24 |
341285033 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_bijection.3732239449 |
|
|
Sep 24 09:59:41 PM UTC 24 |
Sep 24 10:00:54 PM UTC 24 |
17389296205 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_partial_access_b2b.2599591589 |
|
|
Sep 24 09:50:45 PM UTC 24 |
Sep 24 10:00:57 PM UTC 24 |
6112459104 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_mem_partial_access.2966652391 |
|
|
Sep 24 10:00:51 PM UTC 24 |
Sep 24 10:00:59 PM UTC 24 |
180372952 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_regwen.4037508662 |
|
|
Sep 24 09:46:47 PM UTC 24 |
Sep 24 10:01:01 PM UTC 24 |
78867827491 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_alert_test.1639054729 |
|
|
Sep 24 10:01:00 PM UTC 24 |
Sep 24 10:01:02 PM UTC 24 |
16470500 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_throughput_w_partial_write.2846861582 |
|
|
Sep 24 10:00:23 PM UTC 24 |
Sep 24 10:01:05 PM UTC 24 |
211016197 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_smoke.2993235847 |
|
|
Sep 24 10:01:01 PM UTC 24 |
Sep 24 10:01:15 PM UTC 24 |
969993749 ps |
| T149 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_regwen.813565383 |
|
|
Sep 24 09:58:48 PM UTC 24 |
Sep 24 10:01:28 PM UTC 24 |
3518931370 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_max_throughput.971047265 |
|
|
Sep 24 10:01:29 PM UTC 24 |
Sep 24 10:01:36 PM UTC 24 |
181213135 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.1827242378 |
|
|
Sep 24 09:53:29 PM UTC 24 |
Sep 24 10:01:48 PM UTC 24 |
6768436682 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_partial_access.236528552 |
|
|
Sep 24 10:01:19 PM UTC 24 |
Sep 24 10:01:52 PM UTC 24 |
664346447 ps |
| T338 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_lc_escalation.1735970384 |
|
|
Sep 24 10:01:48 PM UTC 24 |
Sep 24 10:01:58 PM UTC 24 |
369836013 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_regwen.830533040 |
|
|
Sep 24 09:51:18 PM UTC 24 |
Sep 24 10:02:11 PM UTC 24 |
33140655510 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_bijection.2184877951 |
|
|
Sep 24 10:01:06 PM UTC 24 |
Sep 24 10:02:16 PM UTC 24 |
36123865780 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_ram_cfg.3858546500 |
|
|
Sep 24 10:02:17 PM UTC 24 |
Sep 24 10:02:19 PM UTC 24 |
123053100 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_pipeline.212974692 |
|
|
Sep 24 09:57:38 PM UTC 24 |
Sep 24 10:02:22 PM UTC 24 |
2322184921 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_mem_walk.2518187222 |
|
|
Sep 24 10:02:20 PM UTC 24 |
Sep 24 10:02:27 PM UTC 24 |
95310920 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.3368428744 |
|
|
Sep 24 10:00:56 PM UTC 24 |
Sep 24 10:02:27 PM UTC 24 |
1206943160 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_mem_partial_access.4215427291 |
|
|
Sep 24 10:02:22 PM UTC 24 |
Sep 24 10:02:29 PM UTC 24 |
313118118 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_throughput_w_partial_write.317251751 |
|
|
Sep 24 10:01:37 PM UTC 24 |
Sep 24 10:02:32 PM UTC 24 |
251664254 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_alert_test.2459756920 |
|
|
Sep 24 10:02:30 PM UTC 24 |
Sep 24 10:02:32 PM UTC 24 |
15035821 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_access_during_key_req.3845664632 |
|
|
Sep 24 09:39:51 PM UTC 24 |
Sep 24 10:02:45 PM UTC 24 |
9712494001 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_executable.2852559775 |
|
|
Sep 24 09:49:47 PM UTC 24 |
Sep 24 10:03:05 PM UTC 24 |
13466415472 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_partial_access_b2b.2549246727 |
|
|
Sep 24 10:01:19 PM UTC 24 |
Sep 24 10:03:09 PM UTC 24 |
4035850110 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_access_during_key_req.3615791539 |
|
|
Sep 24 09:55:00 PM UTC 24 |
Sep 24 10:03:21 PM UTC 24 |
4599396458 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_pipeline.2021948958 |
|
|
Sep 24 09:55:57 PM UTC 24 |
Sep 24 10:03:49 PM UTC 24 |
15772828246 ps |
| T351 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_executable.172556116 |
|
|
Sep 24 09:55:01 PM UTC 24 |
Sep 24 10:04:03 PM UTC 24 |
6674322651 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_smoke.4253404904 |
|
|
Sep 24 10:02:33 PM UTC 24 |
Sep 24 10:04:03 PM UTC 24 |
124642639 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_executable.2050465311 |
|
|
Sep 24 09:46:28 PM UTC 24 |
Sep 24 10:04:03 PM UTC 24 |
14456351939 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_partial_access_b2b.2186962063 |
|
|
Sep 24 09:58:02 PM UTC 24 |
Sep 24 10:04:05 PM UTC 24 |
11533841851 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_regwen.3411306859 |
|
|
Sep 24 09:40:01 PM UTC 24 |
Sep 24 10:04:07 PM UTC 24 |
39153319915 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_bijection.1568040240 |
|
|
Sep 24 10:02:46 PM UTC 24 |
Sep 24 10:04:12 PM UTC 24 |
4972252481 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.720033562 |
|
|
Sep 24 09:59:10 PM UTC 24 |
Sep 24 10:04:13 PM UTC 24 |
4336416841 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_throughput_w_partial_write.1424310119 |
|
|
Sep 24 10:04:04 PM UTC 24 |
Sep 24 10:04:14 PM UTC 24 |
252782878 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_pipeline.2786598359 |
|
|
Sep 24 09:59:43 PM UTC 24 |
Sep 24 10:04:15 PM UTC 24 |
2446943844 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_ram_cfg.1751256084 |
|
|
Sep 24 10:04:13 PM UTC 24 |
Sep 24 10:04:15 PM UTC 24 |
85616437 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_alert_test.390102270 |
|
|
Sep 24 10:04:16 PM UTC 24 |
Sep 24 10:04:18 PM UTC 24 |
15349299 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_smoke.141781269 |
|
|
Sep 24 10:05:35 PM UTC 24 |
Sep 24 10:05:54 PM UTC 24 |
1017829994 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_lc_escalation.991931345 |
|
|
Sep 24 10:04:04 PM UTC 24 |
Sep 24 10:04:18 PM UTC 24 |
1412690777 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_mem_partial_access.1878098608 |
|
|
Sep 24 10:04:14 PM UTC 24 |
Sep 24 10:04:19 PM UTC 24 |
541870173 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_mem_walk.1083713552 |
|
|
Sep 24 10:04:14 PM UTC 24 |
Sep 24 10:04:22 PM UTC 24 |
447302312 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_multiple_keys.846474391 |
|
|
Sep 24 09:55:46 PM UTC 24 |
Sep 24 10:04:31 PM UTC 24 |
22369891160 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_max_throughput.74922258 |
|
|
Sep 24 10:03:50 PM UTC 24 |
Sep 24 10:04:33 PM UTC 24 |
246055167 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_smoke.2424256214 |
|
|
Sep 24 10:04:19 PM UTC 24 |
Sep 24 10:04:40 PM UTC 24 |
1256727840 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_bijection.1161847357 |
|
|
Sep 24 10:04:20 PM UTC 24 |
Sep 24 10:04:43 PM UTC 24 |
773623141 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_partial_access.2811604499 |
|
|
Sep 24 10:03:09 PM UTC 24 |
Sep 24 10:04:50 PM UTC 24 |
410460403 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_max_throughput.1296581060 |
|
|
Sep 24 10:04:40 PM UTC 24 |
Sep 24 10:04:50 PM UTC 24 |
302939524 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_throughput_w_partial_write.4120747436 |
|
|
Sep 24 10:04:44 PM UTC 24 |
Sep 24 10:04:57 PM UTC 24 |
87872393 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_lc_escalation.2635364046 |
|
|
Sep 24 10:04:51 PM UTC 24 |
Sep 24 10:05:05 PM UTC 24 |
1951761556 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_multiple_keys.1385539814 |
|
|
Sep 24 09:47:13 PM UTC 24 |
Sep 24 10:05:17 PM UTC 24 |
15640186029 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_regwen.2814464131 |
|
|
Sep 24 10:00:34 PM UTC 24 |
Sep 24 10:05:18 PM UTC 24 |
4646063577 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_ram_cfg.2971415975 |
|
|
Sep 24 10:05:18 PM UTC 24 |
Sep 24 10:05:20 PM UTC 24 |
32826182 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_regwen.782046946 |
|
|
Sep 24 09:55:10 PM UTC 24 |
Sep 24 10:05:26 PM UTC 24 |
22292764902 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_mem_walk.2600751165 |
|
|
Sep 24 10:05:18 PM UTC 24 |
Sep 24 10:05:26 PM UTC 24 |
1384482559 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_mem_partial_access.2397755639 |
|
|
Sep 24 10:05:21 PM UTC 24 |
Sep 24 10:05:30 PM UTC 24 |
731347268 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_alert_test.1019188589 |
|
|
Sep 24 10:05:32 PM UTC 24 |
Sep 24 10:05:34 PM UTC 24 |
14668824 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_max_throughput.770741468 |
|
|
Sep 24 10:08:49 PM UTC 24 |
Sep 24 10:10:14 PM UTC 24 |
522054954 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all.1346944053 |
|
|
Sep 24 09:44:19 PM UTC 24 |
Sep 24 10:05:37 PM UTC 24 |
4717104081 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_partial_access.3946559665 |
|
|
Sep 24 10:04:32 PM UTC 24 |
Sep 24 10:06:02 PM UTC 24 |
676840178 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_multiple_keys.4260459178 |
|
|
Sep 24 09:53:48 PM UTC 24 |
Sep 24 10:06:03 PM UTC 24 |
25775725903 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.2096515210 |
|
|
Sep 24 10:02:27 PM UTC 24 |
Sep 24 10:06:05 PM UTC 24 |
4474895276 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_max_throughput.2659587652 |
|
|
Sep 24 10:06:04 PM UTC 24 |
Sep 24 10:06:09 PM UTC 24 |
254130753 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_regwen.961027861 |
|
|
Sep 24 09:52:32 PM UTC 24 |
Sep 24 10:06:12 PM UTC 24 |
27560044739 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_executable.2629235839 |
|
|
Sep 24 09:40:53 PM UTC 24 |
Sep 24 10:06:13 PM UTC 24 |
15659480443 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_partial_access.2516173009 |
|
|
Sep 24 10:05:58 PM UTC 24 |
Sep 24 10:06:16 PM UTC 24 |
804973348 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_lc_escalation.114887560 |
|
|
Sep 24 10:06:10 PM UTC 24 |
Sep 24 10:06:18 PM UTC 24 |
1744129457 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_ram_cfg.1256625409 |
|
|
Sep 24 10:06:18 PM UTC 24 |
Sep 24 10:06:20 PM UTC 24 |
26551120 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_partial_access_b2b.48837560 |
|
|
Sep 24 10:03:22 PM UTC 24 |
Sep 24 10:06:29 PM UTC 24 |
8189904708 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_mem_walk.2222440891 |
|
|
Sep 24 10:06:21 PM UTC 24 |
Sep 24 10:06:30 PM UTC 24 |
190046480 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_mem_partial_access.1921705446 |
|
|
Sep 24 10:06:31 PM UTC 24 |
Sep 24 10:06:40 PM UTC 24 |
287628204 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_bijection.3922160375 |
|
|
Sep 24 10:05:38 PM UTC 24 |
Sep 24 10:06:43 PM UTC 24 |
837662435 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_alert_test.3750370617 |
|
|
Sep 24 10:06:44 PM UTC 24 |
Sep 24 10:06:46 PM UTC 24 |
44907902 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_partial_access_b2b.2397215068 |
|
|
Sep 24 09:56:30 PM UTC 24 |
Sep 24 10:06:53 PM UTC 24 |
332623092213 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_regwen.1058300331 |
|
|
Sep 24 10:02:13 PM UTC 24 |
Sep 24 10:06:58 PM UTC 24 |
8746281229 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_pipeline.1354421393 |
|
|
Sep 24 10:01:17 PM UTC 24 |
Sep 24 10:06:58 PM UTC 24 |
6107002136 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_all.311642847 |
|
|
Sep 24 09:39:54 PM UTC 24 |
Sep 24 10:07:05 PM UTC 24 |
20609252422 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.3208227940 |
|
|
Sep 24 10:05:26 PM UTC 24 |
Sep 24 10:07:09 PM UTC 24 |
8216843848 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_all.1807011862 |
|
|
Sep 24 09:41:17 PM UTC 24 |
Sep 24 10:07:14 PM UTC 24 |
214755121092 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_executable.1712728879 |
|
|
Sep 24 10:00:32 PM UTC 24 |
Sep 24 10:07:24 PM UTC 24 |
1618038520 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_throughput_w_partial_write.1811764668 |
|
|
Sep 24 10:07:25 PM UTC 24 |
Sep 24 10:07:32 PM UTC 24 |
63520799 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_bijection.2264390684 |
|
|
Sep 24 10:06:58 PM UTC 24 |
Sep 24 10:07:36 PM UTC 24 |
5717786571 ps |
| T403 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_lc_escalation.715139448 |
|
|
Sep 24 10:07:32 PM UTC 24 |
Sep 24 10:07:42 PM UTC 24 |
2520538444 ps |
| T404 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_pipeline.436590819 |
|
|
Sep 24 10:03:06 PM UTC 24 |
Sep 24 10:07:49 PM UTC 24 |
7608618591 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_smoke.58072712 |
|
|
Sep 24 10:06:47 PM UTC 24 |
Sep 24 10:07:49 PM UTC 24 |
1166517750 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_ram_cfg.1223802612 |
|
|
Sep 24 10:07:50 PM UTC 24 |
Sep 24 10:07:53 PM UTC 24 |
83667675 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.931729771 |
|
|
Sep 24 10:06:31 PM UTC 24 |
Sep 24 10:07:59 PM UTC 24 |
575367426 ps |
| T408 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_throughput_w_partial_write.2029245462 |
|
|
Sep 24 10:06:06 PM UTC 24 |
Sep 24 10:08:04 PM UTC 24 |
305350941 ps |
| T409 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_mem_partial_access.1949835065 |
|
|
Sep 24 10:08:00 PM UTC 24 |
Sep 24 10:08:05 PM UTC 24 |
228100443 ps |
| T410 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_max_throughput.2188948620 |
|
|
Sep 24 10:07:16 PM UTC 24 |
Sep 24 10:08:07 PM UTC 24 |
113081391 ps |
| T411 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_alert_test.4003893368 |
|
|
Sep 24 10:08:08 PM UTC 24 |
Sep 24 10:08:10 PM UTC 24 |
176036552 ps |
| T412 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_partial_access.1577788908 |
|
|
Sep 24 10:07:05 PM UTC 24 |
Sep 24 10:08:11 PM UTC 24 |
194738738 ps |
| T413 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_mem_walk.4095540647 |
|
|
Sep 24 10:07:54 PM UTC 24 |
Sep 24 10:08:11 PM UTC 24 |
1360766924 ps |
| T414 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_executable.298978886 |
|
|
Sep 24 09:40:15 PM UTC 24 |
Sep 24 10:08:27 PM UTC 24 |
27858350172 ps |
| T415 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_access_during_key_req.172035126 |
|
|
Sep 24 09:56:36 PM UTC 24 |
Sep 24 10:08:39 PM UTC 24 |
2013871385 ps |
| T416 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_partial_access_b2b.2680060497 |
|
|
Sep 24 10:00:13 PM UTC 24 |
Sep 24 10:08:39 PM UTC 24 |
64586257734 ps |
| T417 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_partial_access.755438932 |
|
|
Sep 24 10:08:40 PM UTC 24 |
Sep 24 10:09:02 PM UTC 24 |
573152651 ps |
| T418 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.343897960 |
|
|
Sep 24 09:45:19 PM UTC 24 |
Sep 24 10:09:13 PM UTC 24 |
6272331894 ps |
| T419 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_regwen.3150477982 |
|
|
Sep 24 09:56:45 PM UTC 24 |
Sep 24 10:09:13 PM UTC 24 |
66902055351 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_lc_escalation.3968861245 |
|
|
Sep 24 10:09:14 PM UTC 24 |
Sep 24 10:09:25 PM UTC 24 |
11967233904 ps |
| T421 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_partial_access_b2b.3805854876 |
|
|
Sep 24 10:04:34 PM UTC 24 |
Sep 24 10:09:27 PM UTC 24 |
36767668927 ps |
| T422 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_throughput_w_partial_write.1449393622 |
|
|
Sep 24 10:09:03 PM UTC 24 |
Sep 24 10:09:28 PM UTC 24 |
413576708 ps |
| T423 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_access_during_key_req.2321917337 |
|
|
Sep 24 09:49:42 PM UTC 24 |
Sep 24 10:09:32 PM UTC 24 |
4481317416 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_ram_cfg.3778179626 |
|
|
Sep 24 10:09:30 PM UTC 24 |
Sep 24 10:09:33 PM UTC 24 |
86831221 ps |
| T425 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_bijection.2972753487 |
|
|
Sep 24 10:08:12 PM UTC 24 |
Sep 24 10:09:34 PM UTC 24 |
8400334223 ps |
| T426 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_mem_partial_access.3130539165 |
|
|
Sep 24 10:09:34 PM UTC 24 |
Sep 24 10:09:40 PM UTC 24 |
233043631 ps |
| T427 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.1857294018 |
|
|
Sep 24 10:09:35 PM UTC 24 |
Sep 24 10:09:48 PM UTC 24 |
289704142 ps |
| T428 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_mem_walk.513419881 |
|
|
Sep 24 10:09:34 PM UTC 24 |
Sep 24 10:09:51 PM UTC 24 |
469021149 ps |
| T429 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_pipeline.3382079276 |
|
|
Sep 24 10:04:23 PM UTC 24 |
Sep 24 10:09:51 PM UTC 24 |
13029773265 ps |
| T430 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_alert_test.159773393 |
|
|
Sep 24 10:09:49 PM UTC 24 |
Sep 24 10:09:51 PM UTC 24 |
68206167 ps |
| T431 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_pipeline.128280780 |
|
|
Sep 24 10:06:59 PM UTC 24 |
Sep 24 10:09:59 PM UTC 24 |
2561691632 ps |
| T432 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_pipeline.1835473482 |
|
|
Sep 24 10:05:55 PM UTC 24 |
Sep 24 10:10:02 PM UTC 24 |
8232166459 ps |
| T433 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_smoke.1970518966 |
|
|
Sep 24 10:09:53 PM UTC 24 |
Sep 24 10:10:11 PM UTC 24 |
3022556796 ps |
| T434 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_smoke.2005600840 |
|
|
Sep 24 10:08:11 PM UTC 24 |
Sep 24 10:10:12 PM UTC 24 |
1269406534 ps |
| T435 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_lc_escalation.3752627017 |
|
|
Sep 24 10:10:15 PM UTC 24 |
Sep 24 10:10:26 PM UTC 24 |
601860997 ps |
| T436 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_max_throughput.58702775 |
|
|
Sep 24 10:10:12 PM UTC 24 |
Sep 24 10:10:26 PM UTC 24 |
81333032 ps |
| T437 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_throughput_w_partial_write.4074600806 |
|
|
Sep 24 10:10:13 PM UTC 24 |
Sep 24 10:10:50 PM UTC 24 |
436401155 ps |
| T438 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_bijection.3404889227 |
|
|
Sep 24 10:09:53 PM UTC 24 |
Sep 24 10:11:05 PM UTC 24 |
19864351081 ps |
| T439 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_regwen.153596169 |
|
|
Sep 24 10:04:08 PM UTC 24 |
Sep 24 10:11:05 PM UTC 24 |
94551596988 ps |
| T440 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_ram_cfg.1778619105 |
|
|
Sep 24 10:11:06 PM UTC 24 |
Sep 24 10:11:09 PM UTC 24 |
51444328 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_partial_access.3302269917 |
|
|
Sep 24 10:10:01 PM UTC 24 |
Sep 24 10:11:14 PM UTC 24 |
1870445038 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_mem_walk.483034295 |
|
|
Sep 24 10:11:06 PM UTC 24 |
Sep 24 10:11:15 PM UTC 24 |
237308702 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_mem_partial_access.3955045367 |
|
|
Sep 24 10:11:10 PM UTC 24 |
Sep 24 10:11:17 PM UTC 24 |
275245190 ps |
| T444 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_alert_test.511543322 |
|
|
Sep 24 10:11:18 PM UTC 24 |
Sep 24 10:11:20 PM UTC 24 |
47542865 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_smoke.3911406697 |
|
|
Sep 24 10:11:21 PM UTC 24 |
Sep 24 10:11:40 PM UTC 24 |
1497685826 ps |
| T446 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_regwen.819724137 |
|
|
Sep 24 10:06:16 PM UTC 24 |
Sep 24 10:11:44 PM UTC 24 |
6770761493 ps |
| T447 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_executable.1393608888 |
|
|
Sep 24 09:51:14 PM UTC 24 |
Sep 24 10:11:48 PM UTC 24 |
11361121409 ps |
| T448 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_multiple_keys.3358590724 |
|
|
Sep 24 09:51:45 PM UTC 24 |
Sep 24 10:11:53 PM UTC 24 |
8086577405 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_pipeline.844842388 |
|
|
Sep 24 10:08:29 PM UTC 24 |
Sep 24 10:12:00 PM UTC 24 |
8026625879 ps |
| T450 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_partial_access.402181232 |
|
|
Sep 24 10:11:55 PM UTC 24 |
Sep 24 10:12:18 PM UTC 24 |
1263012358 ps |
| T451 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_access_during_key_req.2699014637 |
|
|
Sep 24 09:58:16 PM UTC 24 |
Sep 24 10:12:36 PM UTC 24 |
16098784417 ps |
| T452 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_max_throughput.2030300142 |
|
|
Sep 24 10:12:19 PM UTC 24 |
Sep 24 10:12:38 PM UTC 24 |
71693604 ps |
| T453 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_bijection.2992709573 |
|
|
Sep 24 10:11:45 PM UTC 24 |
Sep 24 10:12:39 PM UTC 24 |
3327599040 ps |
| T454 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_mem_walk.4036051813 |
|
|
Sep 24 10:18:35 PM UTC 24 |
Sep 24 10:18:49 PM UTC 24 |
721109633 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_lc_escalation.2975394017 |
|
|
Sep 24 10:12:39 PM UTC 24 |
Sep 24 10:12:50 PM UTC 24 |
951763710 ps |
| T456 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_executable.4008156413 |
|
|
Sep 24 09:58:21 PM UTC 24 |
Sep 24 10:12:54 PM UTC 24 |
127817189381 ps |
| T457 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_ram_cfg.3986535827 |
|
|
Sep 24 10:12:54 PM UTC 24 |
Sep 24 10:12:57 PM UTC 24 |
44819998 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_throughput_w_partial_write.2659982085 |
|
|
Sep 24 10:12:37 PM UTC 24 |
Sep 24 10:13:00 PM UTC 24 |
1723820858 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_mem_walk.2004696044 |
|
|
Sep 24 10:12:58 PM UTC 24 |
Sep 24 10:13:06 PM UTC 24 |
498454230 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_mem_partial_access.2636208049 |
|
|
Sep 24 10:13:01 PM UTC 24 |
Sep 24 10:13:06 PM UTC 24 |
528989071 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.3390236108 |
|
|
Sep 24 10:13:07 PM UTC 24 |
Sep 24 10:13:23 PM UTC 24 |
530240488 ps |
| T462 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_alert_test.4149363600 |
|
|
Sep 24 10:13:24 PM UTC 24 |
Sep 24 10:13:26 PM UTC 24 |
17811945 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_partial_access_b2b.272170427 |
|
|
Sep 24 10:07:11 PM UTC 24 |
Sep 24 10:13:42 PM UTC 24 |
9516888261 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_smoke.74499167 |
|
|
Sep 24 10:13:27 PM UTC 24 |
Sep 24 10:13:51 PM UTC 24 |
1096514547 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_access_during_key_req.2571009583 |
|
|
Sep 24 10:00:27 PM UTC 24 |
Sep 24 10:14:34 PM UTC 24 |
5015350997 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_multiple_keys.2389124717 |
|
|
Sep 24 10:01:03 PM UTC 24 |
Sep 24 10:14:48 PM UTC 24 |
23667310751 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_access_during_key_req.2384391665 |
|
|
Sep 24 10:12:39 PM UTC 24 |
Sep 24 10:14:51 PM UTC 24 |
1678499788 ps |
| T468 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_bijection.4154235270 |
|
|
Sep 24 10:13:51 PM UTC 24 |
Sep 24 10:14:52 PM UTC 24 |
3663117816 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_partial_access.3857424723 |
|
|
Sep 24 10:14:49 PM UTC 24 |
Sep 24 10:15:13 PM UTC 24 |
160950142 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_partial_access_b2b.3919104009 |
|
|
Sep 24 10:06:04 PM UTC 24 |
Sep 24 10:15:25 PM UTC 24 |
18063517008 ps |
| T471 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_lc_escalation.648938000 |
|
|
Sep 24 10:15:25 PM UTC 24 |
Sep 24 10:15:38 PM UTC 24 |
2978800420 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_partial_access_b2b.3366537521 |
|
|
Sep 24 10:12:01 PM UTC 24 |
Sep 24 10:15:38 PM UTC 24 |
32911723152 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_throughput_w_partial_write.216806325 |
|
|
Sep 24 10:15:14 PM UTC 24 |
Sep 24 10:15:48 PM UTC 24 |
1013754831 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_executable.4024686300 |
|
|
Sep 24 10:06:13 PM UTC 24 |
Sep 24 10:15:53 PM UTC 24 |
12522025514 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_ram_cfg.1137390011 |
|
|
Sep 24 10:15:54 PM UTC 24 |
Sep 24 10:15:56 PM UTC 24 |
59729070 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_executable.1854115250 |
|
|
Sep 24 10:04:58 PM UTC 24 |
Sep 24 10:15:56 PM UTC 24 |
7017530042 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_executable.381563412 |
|
|
Sep 24 10:01:59 PM UTC 24 |
Sep 24 10:16:00 PM UTC 24 |
11638558496 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_mem_walk.3848625786 |
|
|
Sep 24 10:15:57 PM UTC 24 |
Sep 24 10:16:04 PM UTC 24 |
233763695 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_mem_partial_access.998270328 |
|
|
Sep 24 10:15:57 PM UTC 24 |
Sep 24 10:16:04 PM UTC 24 |
234779216 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_access_during_key_req.30696289 |
|
|
Sep 24 10:07:37 PM UTC 24 |
Sep 24 10:16:06 PM UTC 24 |
4444282845 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_alert_test.1709203725 |
|
|
Sep 24 10:16:05 PM UTC 24 |
Sep 24 10:16:07 PM UTC 24 |
39423198 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_max_throughput.1413368071 |
|
|
Sep 24 10:14:52 PM UTC 24 |
Sep 24 10:16:13 PM UTC 24 |
269499365 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_smoke.1049941689 |
|
|
Sep 24 10:16:06 PM UTC 24 |
Sep 24 10:16:25 PM UTC 24 |
2259097293 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_pipeline.4289016938 |
|
|
Sep 24 10:10:00 PM UTC 24 |
Sep 24 10:16:25 PM UTC 24 |
12184755385 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_partial_access_b2b.2702896578 |
|
|
Sep 24 10:08:40 PM UTC 24 |
Sep 24 10:16:28 PM UTC 24 |
14177350434 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_partial_access.835197711 |
|
|
Sep 24 10:16:26 PM UTC 24 |
Sep 24 10:16:45 PM UTC 24 |
997724110 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_access_during_key_req.559087277 |
|
|
Sep 24 10:01:53 PM UTC 24 |
Sep 24 10:16:56 PM UTC 24 |
3189433664 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_multiple_keys.753675112 |
|
|
Sep 24 10:05:37 PM UTC 24 |
Sep 24 10:16:57 PM UTC 24 |
37817754593 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_lc_escalation.2060328809 |
|
|
Sep 24 10:16:57 PM UTC 24 |
Sep 24 10:17:04 PM UTC 24 |
304122005 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_multiple_keys.4161933045 |
|
|
Sep 24 09:48:35 PM UTC 24 |
Sep 24 10:17:07 PM UTC 24 |
20441865787 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_throughput_w_partial_write.9434910 |
|
|
Sep 24 10:16:46 PM UTC 24 |
Sep 24 10:17:15 PM UTC 24 |
371664545 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_ram_cfg.1549580377 |
|
|
Sep 24 10:17:16 PM UTC 24 |
Sep 24 10:17:18 PM UTC 24 |
29678103 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_bijection.2162234763 |
|
|
Sep 24 10:16:14 PM UTC 24 |
Sep 24 10:17:19 PM UTC 24 |
4793397034 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_mem_partial_access.4218085183 |
|
|
Sep 24 10:17:20 PM UTC 24 |
Sep 24 10:17:28 PM UTC 24 |
276744100 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_regwen.1422653623 |
|
|
Sep 24 10:15:50 PM UTC 24 |
Sep 24 10:17:29 PM UTC 24 |
3987315087 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_mem_walk.3432768282 |
|
|
Sep 24 10:17:19 PM UTC 24 |
Sep 24 10:17:33 PM UTC 24 |
2351351011 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_max_throughput.4183159556 |
|
|
Sep 24 10:16:44 PM UTC 24 |
Sep 24 10:17:34 PM UTC 24 |
448064467 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_alert_test.238540714 |
|
|
Sep 24 10:17:33 PM UTC 24 |
Sep 24 10:17:35 PM UTC 24 |
39081138 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.616589080 |
|
|
Sep 24 10:16:01 PM UTC 24 |
Sep 24 10:17:43 PM UTC 24 |
2776177650 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_partial_access_b2b.2919504510 |
|
|
Sep 24 10:10:04 PM UTC 24 |
Sep 24 10:17:44 PM UTC 24 |
16360540729 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_smoke.3648093625 |
|
|
Sep 24 10:17:36 PM UTC 24 |
Sep 24 10:17:45 PM UTC 24 |
1337718364 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_executable.344913452 |
|
|
Sep 24 10:10:27 PM UTC 24 |
Sep 24 10:17:47 PM UTC 24 |
6791089157 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_regwen.1115271679 |
|
|
Sep 24 10:09:28 PM UTC 24 |
Sep 24 10:17:52 PM UTC 24 |
19229533024 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_partial_access.4098026712 |
|
|
Sep 24 10:17:46 PM UTC 24 |
Sep 24 10:17:54 PM UTC 24 |
719303404 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_bijection.1028055960 |
|
|
Sep 24 10:17:44 PM UTC 24 |
Sep 24 10:18:06 PM UTC 24 |
3691729528 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_access_during_key_req.3882239080 |
|
|
Sep 24 10:16:58 PM UTC 24 |
Sep 24 10:18:09 PM UTC 24 |
1298761789 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_lc_escalation.3004561739 |
|
|
Sep 24 10:18:08 PM UTC 24 |
Sep 24 10:18:12 PM UTC 24 |
354644308 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_executable.4158240777 |
|
|
Sep 24 10:09:27 PM UTC 24 |
Sep 24 10:18:23 PM UTC 24 |
1083023940 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all.492009453 |
|
|
Sep 24 09:39:50 PM UTC 24 |
Sep 24 10:18:30 PM UTC 24 |
103174964601 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_ram_cfg.724437327 |
|
|
Sep 24 10:18:32 PM UTC 24 |
Sep 24 10:18:35 PM UTC 24 |
28987936 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_executable.1482008266 |
|
|
Sep 24 10:12:50 PM UTC 24 |
Sep 24 10:18:58 PM UTC 24 |
9472355923 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_pipeline.3838816795 |
|
|
Sep 24 10:14:36 PM UTC 24 |
Sep 24 10:18:51 PM UTC 24 |
4738969034 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_max_throughput.2254547719 |
|
|
Sep 24 10:17:53 PM UTC 24 |
Sep 24 10:18:54 PM UTC 24 |
445922357 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_mem_partial_access.3941875095 |
|
|
Sep 24 10:18:50 PM UTC 24 |
Sep 24 10:18:58 PM UTC 24 |
177507383 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_alert_test.634514370 |
|
|
Sep 24 10:18:59 PM UTC 24 |
Sep 24 10:19:01 PM UTC 24 |
11869872 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_regwen.1029711144 |
|
|
Sep 24 10:07:50 PM UTC 24 |
Sep 24 10:19:04 PM UTC 24 |
8639376610 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_all.1522708428 |
|
|
Sep 24 09:40:03 PM UTC 24 |
Sep 24 10:19:06 PM UTC 24 |
126370817536 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_regwen.959821322 |
|
|
Sep 24 10:10:51 PM UTC 24 |
Sep 24 10:19:15 PM UTC 24 |
5460430304 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_multiple_keys.3995297853 |
|
|
Sep 24 10:16:08 PM UTC 24 |
Sep 24 10:19:19 PM UTC 24 |
3406650109 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_smoke.2624592615 |
|
|
Sep 24 10:18:59 PM UTC 24 |
Sep 24 10:19:19 PM UTC 24 |
311429760 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_partial_access.256452877 |
|
|
Sep 24 10:19:16 PM UTC 24 |
Sep 24 10:19:21 PM UTC 24 |
102162775 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_throughput_w_partial_write.2700547276 |
|
|
Sep 24 10:17:54 PM UTC 24 |
Sep 24 10:19:27 PM UTC 24 |
147219290 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_lc_escalation.2569531421 |
|
|
Sep 24 10:19:28 PM UTC 24 |
Sep 24 10:19:34 PM UTC 24 |
1208630713 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_executable.2651523856 |
|
|
Sep 24 10:18:13 PM UTC 24 |
Sep 24 10:19:34 PM UTC 24 |
3437189765 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_throughput_w_partial_write.25452831 |
|
|
Sep 24 10:19:23 PM UTC 24 |
Sep 24 10:19:35 PM UTC 24 |
68111455 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_executable.2990167271 |
|
|
Sep 24 10:15:39 PM UTC 24 |
Sep 24 10:19:42 PM UTC 24 |
890452503 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_executable.414054334 |
|
|
Sep 24 10:07:42 PM UTC 24 |
Sep 24 10:19:43 PM UTC 24 |
39843599639 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_pipeline.3152316333 |
|
|
Sep 24 10:11:48 PM UTC 24 |
Sep 24 10:19:45 PM UTC 24 |
14521894605 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_ram_cfg.835841187 |
|
|
Sep 24 10:19:43 PM UTC 24 |
Sep 24 10:19:45 PM UTC 24 |
31048991 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_multiple_keys.644080915 |
|
|
Sep 24 09:59:15 PM UTC 24 |
Sep 24 10:19:52 PM UTC 24 |
30413127833 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_mem_partial_access.4161308873 |
|
|
Sep 24 10:19:45 PM UTC 24 |
Sep 24 10:19:54 PM UTC 24 |
189232472 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_mem_walk.1429537956 |
|
|
Sep 24 10:19:43 PM UTC 24 |
Sep 24 10:19:54 PM UTC 24 |
1176850253 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_alert_test.1271279408 |
|
|
Sep 24 10:19:55 PM UTC 24 |
Sep 24 10:19:57 PM UTC 24 |
20432334 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.1515347951 |
|
|
Sep 24 10:17:29 PM UTC 24 |
Sep 24 10:20:04 PM UTC 24 |
5026531561 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_smoke.412488886 |
|
|
Sep 24 10:19:55 PM UTC 24 |
Sep 24 10:20:09 PM UTC 24 |
1958762389 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_bijection.2349899496 |
|
|
Sep 24 10:19:05 PM UTC 24 |
Sep 24 10:20:18 PM UTC 24 |
13540221125 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_pipeline.1583449286 |
|
|
Sep 24 10:16:26 PM UTC 24 |
Sep 24 10:20:30 PM UTC 24 |
8606247012 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_partial_access.4264217884 |
|
|
Sep 24 10:20:18 PM UTC 24 |
Sep 24 10:20:44 PM UTC 24 |
903888186 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_bijection.917343164 |
|
|
Sep 24 10:20:05 PM UTC 24 |
Sep 24 10:20:49 PM UTC 24 |
516085916 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_max_throughput.1074372735 |
|
|
Sep 24 10:20:45 PM UTC 24 |
Sep 24 10:20:57 PM UTC 24 |
232114664 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_regwen.2567386940 |
|
|
Sep 24 10:05:05 PM UTC 24 |
Sep 24 10:20:57 PM UTC 24 |
9638564846 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_lc_escalation.2879664193 |
|
|
Sep 24 10:20:58 PM UTC 24 |
Sep 24 10:21:01 PM UTC 24 |
84280402 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.3034729573 |
|
|
Sep 24 10:18:51 PM UTC 24 |
Sep 24 10:21:01 PM UTC 24 |
3109722149 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_access_during_key_req.1837110275 |
|
|
Sep 24 10:04:51 PM UTC 24 |
Sep 24 10:21:14 PM UTC 24 |
3227417056 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_ram_cfg.2520483399 |
|
|
Sep 24 10:21:15 PM UTC 24 |
Sep 24 10:21:18 PM UTC 24 |
32051124 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.1266955430 |
|
|
Sep 24 10:19:46 PM UTC 24 |
Sep 24 10:21:18 PM UTC 24 |
1682967443 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_max_throughput.701070504 |
|
|
Sep 24 10:19:21 PM UTC 24 |
Sep 24 10:21:22 PM UTC 24 |
264003247 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_mem_partial_access.788542410 |
|
|
Sep 24 10:21:19 PM UTC 24 |
Sep 24 10:21:22 PM UTC 24 |
58108336 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_multiple_keys.1282959902 |
|
|
Sep 24 10:09:53 PM UTC 24 |
Sep 24 10:21:25 PM UTC 24 |
3801760904 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_mem_walk.2285551137 |
|
|
Sep 24 10:21:19 PM UTC 24 |
Sep 24 10:21:26 PM UTC 24 |
889908425 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_alert_test.2159936157 |
|
|
Sep 24 10:21:26 PM UTC 24 |
Sep 24 10:21:28 PM UTC 24 |
14036662 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_smoke.7455194 |
|
|
Sep 24 10:21:27 PM UTC 24 |
Sep 24 10:21:34 PM UTC 24 |
326612745 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_partial_access_b2b.4189829679 |
|
|
Sep 24 10:14:52 PM UTC 24 |
Sep 24 10:21:41 PM UTC 24 |
63637821444 ps |