| T553 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_all.4128990077 |
|
|
Sep 24 10:02:27 PM UTC 24 |
Sep 24 10:21:56 PM UTC 24 |
22432052481 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_bijection.1500806397 |
|
|
Sep 24 10:21:34 PM UTC 24 |
Sep 24 10:22:04 PM UTC 24 |
1771978259 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_executable.2990734775 |
|
|
Sep 24 10:04:06 PM UTC 24 |
Sep 24 10:22:09 PM UTC 24 |
116238510970 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_partial_access.4163934273 |
|
|
Sep 24 10:21:57 PM UTC 24 |
Sep 24 10:22:13 PM UTC 24 |
255167168 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_throughput_w_partial_write.3404393814 |
|
|
Sep 24 10:20:51 PM UTC 24 |
Sep 24 10:22:16 PM UTC 24 |
160376899 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_max_throughput.3452910474 |
|
|
Sep 24 10:22:10 PM UTC 24 |
Sep 24 10:22:27 PM UTC 24 |
79174006 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_all.4092611350 |
|
|
Sep 24 09:57:11 PM UTC 24 |
Sep 24 10:22:30 PM UTC 24 |
4692309638 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_lc_escalation.898591006 |
|
|
Sep 24 10:22:16 PM UTC 24 |
Sep 24 10:22:32 PM UTC 24 |
3724342135 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_throughput_w_partial_write.2944502778 |
|
|
Sep 24 10:22:14 PM UTC 24 |
Sep 24 10:22:52 PM UTC 24 |
227886014 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_ram_cfg.2438536373 |
|
|
Sep 24 10:22:54 PM UTC 24 |
Sep 24 10:22:56 PM UTC 24 |
52492785 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_access_during_key_req.375660933 |
|
|
Sep 24 10:10:27 PM UTC 24 |
Sep 24 10:22:58 PM UTC 24 |
3741929858 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_pipeline.1200877780 |
|
|
Sep 24 10:17:45 PM UTC 24 |
Sep 24 10:23:00 PM UTC 24 |
12379540567 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_mem_partial_access.2169702487 |
|
|
Sep 24 10:22:58 PM UTC 24 |
Sep 24 10:23:03 PM UTC 24 |
189408142 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_mem_walk.994596576 |
|
|
Sep 24 10:22:57 PM UTC 24 |
Sep 24 10:23:06 PM UTC 24 |
308658361 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_alert_test.1807341551 |
|
|
Sep 24 10:23:06 PM UTC 24 |
Sep 24 10:23:08 PM UTC 24 |
14200516 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_multiple_keys.1354543028 |
|
|
Sep 24 10:04:19 PM UTC 24 |
Sep 24 10:23:27 PM UTC 24 |
2772877244 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_pipeline.1275070984 |
|
|
Sep 24 10:19:07 PM UTC 24 |
Sep 24 10:23:42 PM UTC 24 |
25373471944 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.1016787671 |
|
|
Sep 24 10:23:01 PM UTC 24 |
Sep 24 10:23:45 PM UTC 24 |
6270838397 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.2412262374 |
|
|
Sep 24 10:21:23 PM UTC 24 |
Sep 24 10:24:03 PM UTC 24 |
1594923138 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_smoke.815816974 |
|
|
Sep 24 10:23:10 PM UTC 24 |
Sep 24 10:24:15 PM UTC 24 |
496375632 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_access_during_key_req.665970439 |
|
|
Sep 24 10:06:13 PM UTC 24 |
Sep 24 10:24:19 PM UTC 24 |
73456347644 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_bijection.1715053701 |
|
|
Sep 24 10:23:43 PM UTC 24 |
Sep 24 10:24:21 PM UTC 24 |
4032865537 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_partial_access_b2b.3770158829 |
|
|
Sep 24 10:20:30 PM UTC 24 |
Sep 24 10:24:39 PM UTC 24 |
19535747063 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_max_throughput.3080699511 |
|
|
Sep 24 10:24:20 PM UTC 24 |
Sep 24 10:24:40 PM UTC 24 |
299735048 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_multiple_keys.2675016324 |
|
|
Sep 24 10:02:34 PM UTC 24 |
Sep 24 10:24:47 PM UTC 24 |
13391364133 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_lc_escalation.3946097800 |
|
|
Sep 24 10:24:41 PM UTC 24 |
Sep 24 10:24:49 PM UTC 24 |
805929856 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_multiple_keys.3195622100 |
|
|
Sep 24 10:21:29 PM UTC 24 |
Sep 24 10:24:55 PM UTC 24 |
11175819198 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_ram_cfg.3080144706 |
|
|
Sep 24 10:24:56 PM UTC 24 |
Sep 24 10:24:58 PM UTC 24 |
140258791 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_partial_access_b2b.351217616 |
|
|
Sep 24 10:22:05 PM UTC 24 |
Sep 24 10:25:11 PM UTC 24 |
98516115710 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_mem_partial_access.4246339562 |
|
|
Sep 24 10:25:10 PM UTC 24 |
Sep 24 10:25:15 PM UTC 24 |
199526512 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_mem_walk.2341374762 |
|
|
Sep 24 10:25:00 PM UTC 24 |
Sep 24 10:25:16 PM UTC 24 |
906580795 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_alert_test.3410434972 |
|
|
Sep 24 10:25:17 PM UTC 24 |
Sep 24 10:25:19 PM UTC 24 |
17186227 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_access_during_key_req.1837207099 |
|
|
Sep 24 10:04:04 PM UTC 24 |
Sep 24 10:25:26 PM UTC 24 |
3785249299 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_multiple_keys.128175067 |
|
|
Sep 24 10:08:11 PM UTC 24 |
Sep 24 10:25:28 PM UTC 24 |
3055369823 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_multiple_keys.2962897720 |
|
|
Sep 24 10:19:58 PM UTC 24 |
Sep 24 10:25:34 PM UTC 24 |
17913752513 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all.4166957687 |
|
|
Sep 24 09:40:23 PM UTC 24 |
Sep 24 10:25:36 PM UTC 24 |
22169361209 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_partial_access.55733368 |
|
|
Sep 24 10:24:04 PM UTC 24 |
Sep 24 10:25:37 PM UTC 24 |
2838117491 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_pipeline.2783670918 |
|
|
Sep 24 10:20:10 PM UTC 24 |
Sep 24 10:25:39 PM UTC 24 |
64848168285 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_bijection.1606530098 |
|
|
Sep 24 10:25:29 PM UTC 24 |
Sep 24 10:25:58 PM UTC 24 |
1559922476 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_partial_access_b2b.1239932267 |
|
|
Sep 24 10:17:48 PM UTC 24 |
Sep 24 10:26:00 PM UTC 24 |
15222989951 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_multiple_keys.440979122 |
|
|
Sep 24 10:13:43 PM UTC 24 |
Sep 24 10:26:03 PM UTC 24 |
29346914263 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_throughput_w_partial_write.3302492039 |
|
|
Sep 24 10:24:22 PM UTC 24 |
Sep 24 10:26:08 PM UTC 24 |
158393496 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_lc_escalation.340116938 |
|
|
Sep 24 10:26:01 PM UTC 24 |
Sep 24 10:26:11 PM UTC 24 |
567403092 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_throughput_w_partial_write.491518323 |
|
|
Sep 24 10:25:58 PM UTC 24 |
Sep 24 10:26:17 PM UTC 24 |
290718156 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_multiple_keys.2018356847 |
|
|
Sep 24 10:25:27 PM UTC 24 |
Sep 24 10:26:19 PM UTC 24 |
419477567 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_pipeline.533979742 |
|
|
Sep 24 10:21:42 PM UTC 24 |
Sep 24 10:26:19 PM UTC 24 |
4798464465 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_ram_cfg.3934570103 |
|
|
Sep 24 10:26:18 PM UTC 24 |
Sep 24 10:26:20 PM UTC 24 |
51051572 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_mem_partial_access.4202130284 |
|
|
Sep 24 10:26:20 PM UTC 24 |
Sep 24 10:26:26 PM UTC 24 |
100417307 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_mem_walk.2707543082 |
|
|
Sep 24 10:26:19 PM UTC 24 |
Sep 24 10:26:30 PM UTC 24 |
693346707 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_all.2015163734 |
|
|
Sep 24 10:08:07 PM UTC 24 |
Sep 24 10:26:31 PM UTC 24 |
17145187745 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_alert_test.1539634146 |
|
|
Sep 24 10:26:31 PM UTC 24 |
Sep 24 10:26:33 PM UTC 24 |
17515695 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_regwen.3466563032 |
|
|
Sep 24 10:17:08 PM UTC 24 |
Sep 24 10:26:34 PM UTC 24 |
20468287158 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_regwen.446768433 |
|
|
Sep 24 10:18:25 PM UTC 24 |
Sep 24 10:26:40 PM UTC 24 |
22524849705 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_max_throughput.1570924420 |
|
|
Sep 24 10:25:40 PM UTC 24 |
Sep 24 10:26:45 PM UTC 24 |
114914904 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_partial_access.3738701254 |
|
|
Sep 24 10:25:37 PM UTC 24 |
Sep 24 10:26:51 PM UTC 24 |
548754374 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.3540459747 |
|
|
Sep 24 10:25:12 PM UTC 24 |
Sep 24 10:27:16 PM UTC 24 |
452408756 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_smoke.785263550 |
|
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Sep 24 10:25:21 PM UTC 24 |
Sep 24 10:27:16 PM UTC 24 |
7074205007 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_smoke.1278714516 |
|
|
Sep 24 10:26:32 PM UTC 24 |
Sep 24 10:27:17 PM UTC 24 |
425332949 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_bijection.3185292942 |
|
|
Sep 24 10:26:35 PM UTC 24 |
Sep 24 10:27:19 PM UTC 24 |
7817588081 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_access_during_key_req.3075726628 |
|
|
Sep 24 10:18:10 PM UTC 24 |
Sep 24 10:27:29 PM UTC 24 |
1956076078 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_lc_escalation.1654463241 |
|
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Sep 24 10:27:19 PM UTC 24 |
Sep 24 10:27:30 PM UTC 24 |
429630559 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_max_throughput.1670206726 |
|
|
Sep 24 10:27:17 PM UTC 24 |
Sep 24 10:27:39 PM UTC 24 |
92860825 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_ram_cfg.2879774957 |
|
|
Sep 24 10:27:40 PM UTC 24 |
Sep 24 10:27:42 PM UTC 24 |
93485380 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_regwen.3250975690 |
|
|
Sep 24 10:22:34 PM UTC 24 |
Sep 24 10:27:42 PM UTC 24 |
1753179602 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_access_during_key_req.4155216769 |
|
|
Sep 24 10:15:38 PM UTC 24 |
Sep 24 10:27:46 PM UTC 24 |
8755161506 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_mem_partial_access.809808922 |
|
|
Sep 24 10:27:43 PM UTC 24 |
Sep 24 10:27:49 PM UTC 24 |
506971789 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_mem_walk.2572941655 |
|
|
Sep 24 10:27:43 PM UTC 24 |
Sep 24 10:27:51 PM UTC 24 |
400319969 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_alert_test.3944965136 |
|
|
Sep 24 10:27:52 PM UTC 24 |
Sep 24 10:27:54 PM UTC 24 |
45375515 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_partial_access_b2b.1122933539 |
|
|
Sep 24 10:24:16 PM UTC 24 |
Sep 24 10:27:58 PM UTC 24 |
6333633692 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_regwen.2047796108 |
|
|
Sep 24 10:12:50 PM UTC 24 |
Sep 24 10:27:58 PM UTC 24 |
62246478091 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_access_during_key_req.2457937801 |
|
|
Sep 24 10:09:14 PM UTC 24 |
Sep 24 10:28:01 PM UTC 24 |
3146345970 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_smoke.1927673280 |
|
|
Sep 24 10:27:55 PM UTC 24 |
Sep 24 10:28:03 PM UTC 24 |
224028448 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_partial_access.2380733301 |
|
|
Sep 24 10:26:46 PM UTC 24 |
Sep 24 10:28:07 PM UTC 24 |
3452176487 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_partial_access.1189057703 |
|
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Sep 24 10:28:03 PM UTC 24 |
Sep 24 10:28:07 PM UTC 24 |
184928582 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_pipeline.1489700683 |
|
|
Sep 24 10:25:35 PM UTC 24 |
Sep 24 10:28:21 PM UTC 24 |
7020587457 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_all.1219631265 |
|
|
Sep 24 10:00:59 PM UTC 24 |
Sep 24 10:28:23 PM UTC 24 |
8716322172 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_regwen.2162453507 |
|
|
Sep 24 10:19:36 PM UTC 24 |
Sep 24 10:28:28 PM UTC 24 |
2100572726 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_lc_escalation.827447341 |
|
|
Sep 24 10:28:22 PM UTC 24 |
Sep 24 10:28:34 PM UTC 24 |
4560258083 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_partial_access_b2b.2363944705 |
|
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Sep 24 10:19:20 PM UTC 24 |
Sep 24 10:28:49 PM UTC 24 |
56308300598 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_throughput_w_partial_write.372493912 |
|
|
Sep 24 10:27:17 PM UTC 24 |
Sep 24 10:28:50 PM UTC 24 |
167676970 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_bijection.472395166 |
|
|
Sep 24 10:28:00 PM UTC 24 |
Sep 24 10:28:51 PM UTC 24 |
1111201058 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_ram_cfg.4254935182 |
|
|
Sep 24 10:28:50 PM UTC 24 |
Sep 24 10:28:53 PM UTC 24 |
32290624 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_mem_partial_access.1988200205 |
|
|
Sep 24 10:28:52 PM UTC 24 |
Sep 24 10:29:02 PM UTC 24 |
190263096 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_mem_walk.442462592 |
|
|
Sep 24 10:28:50 PM UTC 24 |
Sep 24 10:29:04 PM UTC 24 |
186980183 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_alert_test.2413236576 |
|
|
Sep 24 10:29:05 PM UTC 24 |
Sep 24 10:29:07 PM UTC 24 |
44676589 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_max_throughput.3497711289 |
|
|
Sep 24 10:28:09 PM UTC 24 |
Sep 24 10:29:33 PM UTC 24 |
249932207 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.4246932653 |
|
|
Sep 24 10:27:47 PM UTC 24 |
Sep 24 10:29:41 PM UTC 24 |
1530236062 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.2209208048 |
|
|
Sep 24 10:28:54 PM UTC 24 |
Sep 24 10:29:58 PM UTC 24 |
621771958 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_partial_access_b2b.2637159561 |
|
|
Sep 24 10:16:29 PM UTC 24 |
Sep 24 10:29:58 PM UTC 24 |
151896210263 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_throughput_w_partial_write.2704130724 |
|
|
Sep 24 10:28:09 PM UTC 24 |
Sep 24 10:30:11 PM UTC 24 |
446188479 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_partial_access.473706224 |
|
|
Sep 24 10:29:59 PM UTC 24 |
Sep 24 10:30:21 PM UTC 24 |
890528958 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_bijection.2498733696 |
|
|
Sep 24 10:29:42 PM UTC 24 |
Sep 24 10:30:22 PM UTC 24 |
543702075 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_max_throughput.1056644091 |
|
|
Sep 24 10:30:22 PM UTC 24 |
Sep 24 10:31:00 PM UTC 24 |
129619422 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_partial_access_b2b.2561294986 |
|
|
Sep 24 10:25:38 PM UTC 24 |
Sep 24 10:31:00 PM UTC 24 |
11277167867 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_lc_escalation.3925240744 |
|
|
Sep 24 10:30:51 PM UTC 24 |
Sep 24 10:31:04 PM UTC 24 |
2063764606 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_executable.2617784347 |
|
|
Sep 24 10:19:35 PM UTC 24 |
Sep 24 10:31:07 PM UTC 24 |
3198657671 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_ram_cfg.1105046937 |
|
|
Sep 24 10:31:08 PM UTC 24 |
Sep 24 10:31:11 PM UTC 24 |
59164247 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_executable.318074951 |
|
|
Sep 24 10:21:02 PM UTC 24 |
Sep 24 10:31:12 PM UTC 24 |
10245425297 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_pipeline.944476363 |
|
|
Sep 24 10:23:46 PM UTC 24 |
Sep 24 10:31:13 PM UTC 24 |
14207881006 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_mem_partial_access.490282283 |
|
|
Sep 24 10:31:13 PM UTC 24 |
Sep 24 10:31:17 PM UTC 24 |
163276451 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_pipeline.4061101612 |
|
|
Sep 24 10:26:41 PM UTC 24 |
Sep 24 10:31:19 PM UTC 24 |
4834009398 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_multiple_keys.3323592488 |
|
|
Sep 24 10:06:54 PM UTC 24 |
Sep 24 10:31:20 PM UTC 24 |
299222454734 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_mem_walk.3110410088 |
|
|
Sep 24 10:31:12 PM UTC 24 |
Sep 24 10:31:21 PM UTC 24 |
340762327 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_alert_test.4085311600 |
|
|
Sep 24 10:31:20 PM UTC 24 |
Sep 24 10:31:22 PM UTC 24 |
33354342 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_smoke.769367925 |
|
|
Sep 24 10:31:21 PM UTC 24 |
Sep 24 10:31:31 PM UTC 24 |
841776037 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_multiple_keys.2005139225 |
|
|
Sep 24 10:17:37 PM UTC 24 |
Sep 24 10:31:46 PM UTC 24 |
2734642848 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_throughput_w_partial_write.1611443635 |
|
|
Sep 24 10:30:23 PM UTC 24 |
Sep 24 10:31:57 PM UTC 24 |
905920670 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_executable.3352330675 |
|
|
Sep 24 10:17:05 PM UTC 24 |
Sep 24 10:31:58 PM UTC 24 |
49080956702 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_bijection.2201443452 |
|
|
Sep 24 10:31:23 PM UTC 24 |
Sep 24 10:31:58 PM UTC 24 |
1772136566 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_partial_access.713437414 |
|
|
Sep 24 10:31:46 PM UTC 24 |
Sep 24 10:31:58 PM UTC 24 |
782552042 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_lc_escalation.1452216953 |
|
|
Sep 24 10:32:00 PM UTC 24 |
Sep 24 10:32:06 PM UTC 24 |
1699345695 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_partial_access_b2b.3029760716 |
|
|
Sep 24 10:26:52 PM UTC 24 |
Sep 24 10:32:07 PM UTC 24 |
95643893822 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_throughput_w_partial_write.601183898 |
|
|
Sep 24 10:31:59 PM UTC 24 |
Sep 24 10:32:14 PM UTC 24 |
1302154233 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_pipeline.3961449411 |
|
|
Sep 24 10:28:02 PM UTC 24 |
Sep 24 10:32:16 PM UTC 24 |
5035207389 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_ram_cfg.199376036 |
|
|
Sep 24 10:32:16 PM UTC 24 |
Sep 24 10:32:19 PM UTC 24 |
205805833 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_mem_walk.1405613228 |
|
|
Sep 24 10:32:19 PM UTC 24 |
Sep 24 10:32:30 PM UTC 24 |
520466161 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_mem_partial_access.3212522538 |
|
|
Sep 24 10:32:31 PM UTC 24 |
Sep 24 10:32:37 PM UTC 24 |
223441913 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_max_throughput.263027885 |
|
|
Sep 24 10:31:59 PM UTC 24 |
Sep 24 10:32:49 PM UTC 24 |
388105409 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.492818228 |
|
|
Sep 24 10:32:38 PM UTC 24 |
Sep 24 10:32:50 PM UTC 24 |
1499190880 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_alert_test.2901461909 |
|
|
Sep 24 10:32:51 PM UTC 24 |
Sep 24 10:32:53 PM UTC 24 |
18270772 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_smoke.685359722 |
|
|
Sep 24 10:32:54 PM UTC 24 |
Sep 24 10:33:02 PM UTC 24 |
392544305 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_access_during_key_req.1446343230 |
|
|
Sep 24 10:20:58 PM UTC 24 |
Sep 24 10:33:05 PM UTC 24 |
3669627341 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_access_during_key_req.958361106 |
|
|
Sep 24 10:22:27 PM UTC 24 |
Sep 24 10:33:12 PM UTC 24 |
2763644289 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.3438592477 |
|
|
Sep 24 10:31:14 PM UTC 24 |
Sep 24 10:33:20 PM UTC 24 |
1569873558 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_pipeline.3719693399 |
|
|
Sep 24 10:31:31 PM UTC 24 |
Sep 24 10:34:05 PM UTC 24 |
2727488442 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_multiple_keys.4142309039 |
|
|
Sep 24 10:11:41 PM UTC 24 |
Sep 24 10:34:23 PM UTC 24 |
39909645535 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_partial_access.2586231799 |
|
|
Sep 24 10:33:21 PM UTC 24 |
Sep 24 10:34:28 PM UTC 24 |
2221570986 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_bijection.2971262103 |
|
|
Sep 24 10:33:06 PM UTC 24 |
Sep 24 10:34:36 PM UTC 24 |
1263054315 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_throughput_w_partial_write.994046302 |
|
|
Sep 24 10:34:29 PM UTC 24 |
Sep 24 10:34:38 PM UTC 24 |
111494659 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_pipeline.630399323 |
|
|
Sep 24 10:29:58 PM UTC 24 |
Sep 24 10:34:41 PM UTC 24 |
21553090759 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_all.2187973801 |
|
|
Sep 24 10:25:16 PM UTC 24 |
Sep 24 10:34:42 PM UTC 24 |
11265932442 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_lc_escalation.1939142097 |
|
|
Sep 24 10:34:37 PM UTC 24 |
Sep 24 10:34:47 PM UTC 24 |
559983505 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_ram_cfg.2796108193 |
|
|
Sep 24 10:34:48 PM UTC 24 |
Sep 24 10:34:50 PM UTC 24 |
59819689 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_mem_walk.2026764250 |
|
|
Sep 24 10:34:51 PM UTC 24 |
Sep 24 10:34:57 PM UTC 24 |
73696209 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_mem_partial_access.320409127 |
|
|
Sep 24 10:34:58 PM UTC 24 |
Sep 24 10:35:03 PM UTC 24 |
185768385 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_max_throughput.285631782 |
|
|
Sep 24 10:34:24 PM UTC 24 |
Sep 24 10:35:09 PM UTC 24 |
459879312 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_executable.559204288 |
|
|
Sep 24 10:22:32 PM UTC 24 |
Sep 24 10:35:11 PM UTC 24 |
2527395377 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_alert_test.858455382 |
|
|
Sep 24 10:35:12 PM UTC 24 |
Sep 24 10:35:14 PM UTC 24 |
56414982 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_smoke.1170762254 |
|
|
Sep 24 10:35:15 PM UTC 24 |
Sep 24 10:35:25 PM UTC 24 |
145911893 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_executable.531526948 |
|
|
Sep 24 10:24:48 PM UTC 24 |
Sep 24 10:35:31 PM UTC 24 |
9683727083 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_partial_access_b2b.3310841782 |
|
|
Sep 24 10:28:04 PM UTC 24 |
Sep 24 10:35:31 PM UTC 24 |
18006571548 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_all.787360257 |
|
|
Sep 24 09:42:13 PM UTC 24 |
Sep 24 10:35:50 PM UTC 24 |
84410109783 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_partial_access.2435350284 |
|
|
Sep 24 10:35:51 PM UTC 24 |
Sep 24 10:36:00 PM UTC 24 |
246474046 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_bijection.2326181146 |
|
|
Sep 24 10:35:32 PM UTC 24 |
Sep 24 10:36:07 PM UTC 24 |
1880823915 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_multiple_keys.2264117891 |
|
|
Sep 24 10:31:22 PM UTC 24 |
Sep 24 10:36:28 PM UTC 24 |
6396260605 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_throughput_w_partial_write.225909149 |
|
|
Sep 24 10:36:28 PM UTC 24 |
Sep 24 10:36:38 PM UTC 24 |
63114406 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_lc_escalation.4128020344 |
|
|
Sep 24 10:36:38 PM UTC 24 |
Sep 24 10:36:43 PM UTC 24 |
355149335 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_partial_access_b2b.544743649 |
|
|
Sep 24 10:31:58 PM UTC 24 |
Sep 24 10:36:57 PM UTC 24 |
3945937996 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_max_throughput.3900172036 |
|
|
Sep 24 10:36:07 PM UTC 24 |
Sep 24 10:37:07 PM UTC 24 |
466921856 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_all.3633369977 |
|
|
Sep 24 09:59:12 PM UTC 24 |
Sep 24 10:37:15 PM UTC 24 |
140134835998 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_ram_cfg.1526800522 |
|
|
Sep 24 10:37:16 PM UTC 24 |
Sep 24 10:37:18 PM UTC 24 |
77717246 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_regwen.2747182213 |
|
|
Sep 24 10:26:12 PM UTC 24 |
Sep 24 10:37:26 PM UTC 24 |
25540934355 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_mem_walk.923287900 |
|
|
Sep 24 10:37:19 PM UTC 24 |
Sep 24 10:37:33 PM UTC 24 |
450687220 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_mem_partial_access.4086920165 |
|
|
Sep 24 10:37:26 PM UTC 24 |
Sep 24 10:37:36 PM UTC 24 |
1646688109 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_pipeline.530810366 |
|
|
Sep 24 10:33:12 PM UTC 24 |
Sep 24 10:37:37 PM UTC 24 |
2592635643 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_executable.1238151769 |
|
|
Sep 24 10:31:00 PM UTC 24 |
Sep 24 10:37:38 PM UTC 24 |
1459708466 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_alert_test.2833513072 |
|
|
Sep 24 10:37:38 PM UTC 24 |
Sep 24 10:37:40 PM UTC 24 |
52553736 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_all.123233247 |
|
|
Sep 24 09:55:36 PM UTC 24 |
Sep 24 10:37:41 PM UTC 24 |
10956578267 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_smoke.899918534 |
|
|
Sep 24 10:37:39 PM UTC 24 |
Sep 24 10:37:50 PM UTC 24 |
381954831 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_regwen.3323453584 |
|
|
Sep 24 10:24:50 PM UTC 24 |
Sep 24 10:37:50 PM UTC 24 |
9978205312 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_bijection.3884650276 |
|
|
Sep 24 10:37:42 PM UTC 24 |
Sep 24 10:38:15 PM UTC 24 |
2151829656 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_multiple_keys.2030784576 |
|
|
Sep 24 10:27:59 PM UTC 24 |
Sep 24 10:38:18 PM UTC 24 |
2789255239 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_multiple_keys.729686214 |
|
|
Sep 24 10:19:02 PM UTC 24 |
Sep 24 10:38:20 PM UTC 24 |
15899589166 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_throughput_w_partial_write.1461243386 |
|
|
Sep 24 10:38:21 PM UTC 24 |
Sep 24 10:38:32 PM UTC 24 |
93313701 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_access_during_key_req.2170817240 |
|
|
Sep 24 10:26:04 PM UTC 24 |
Sep 24 10:38:33 PM UTC 24 |
4221392918 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_executable.394104825 |
|
|
Sep 24 10:27:30 PM UTC 24 |
Sep 24 10:38:34 PM UTC 24 |
34936063441 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_regwen.1802709002 |
|
|
Sep 24 10:21:02 PM UTC 24 |
Sep 24 10:38:42 PM UTC 24 |
33422597464 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_partial_access.3027688717 |
|
|
Sep 24 10:37:51 PM UTC 24 |
Sep 24 10:38:45 PM UTC 24 |
941530184 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_lc_escalation.3466680061 |
|
|
Sep 24 10:38:33 PM UTC 24 |
Sep 24 10:38:46 PM UTC 24 |
2216229809 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_ram_cfg.4116380935 |
|
|
Sep 24 10:38:46 PM UTC 24 |
Sep 24 10:38:49 PM UTC 24 |
59261131 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_mem_partial_access.4110873089 |
|
|
Sep 24 10:38:50 PM UTC 24 |
Sep 24 10:38:55 PM UTC 24 |
409348807 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_mem_walk.107898640 |
|
|
Sep 24 10:38:48 PM UTC 24 |
Sep 24 10:38:57 PM UTC 24 |
226449053 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_access_during_key_req.6588002 |
|
|
Sep 24 10:27:20 PM UTC 24 |
Sep 24 10:38:59 PM UTC 24 |
7499453953 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_alert_test.1287832290 |
|
|
Sep 24 10:39:00 PM UTC 24 |
Sep 24 10:39:03 PM UTC 24 |
14345457 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_smoke.1994124033 |
|
|
Sep 24 10:39:04 PM UTC 24 |
Sep 24 10:39:07 PM UTC 24 |
267889672 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_all.1987988038 |
|
|
Sep 24 09:50:03 PM UTC 24 |
Sep 24 10:39:08 PM UTC 24 |
12918822880 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_partial_access_b2b.1078988113 |
|
|
Sep 24 10:34:06 PM UTC 24 |
Sep 24 10:39:14 PM UTC 24 |
3546563303 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_multiple_keys.2589888930 |
|
|
Sep 24 10:26:34 PM UTC 24 |
Sep 24 10:39:15 PM UTC 24 |
5838802012 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.357776191 |
|
|
Sep 24 10:37:34 PM UTC 24 |
Sep 24 10:39:17 PM UTC 24 |
5931213816 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_max_throughput.3700617039 |
|
|
Sep 24 10:38:19 PM UTC 24 |
Sep 24 10:39:19 PM UTC 24 |
432003315 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_max_throughput.4013961486 |
|
|
Sep 24 10:39:20 PM UTC 24 |
Sep 24 10:39:24 PM UTC 24 |
38245090 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_throughput_w_partial_write.3263020723 |
|
|
Sep 24 10:39:25 PM UTC 24 |
Sep 24 10:39:43 PM UTC 24 |
722479701 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_lc_escalation.3640148567 |
|
|
Sep 24 10:39:43 PM UTC 24 |
Sep 24 10:39:55 PM UTC 24 |
1756099740 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_partial_access.652342432 |
|
|
Sep 24 10:39:16 PM UTC 24 |
Sep 24 10:39:58 PM UTC 24 |
894021050 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_access_during_key_req.2120979925 |
|
|
Sep 24 10:19:35 PM UTC 24 |
Sep 24 10:40:38 PM UTC 24 |
3752650230 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_all.1705752820 |
|
|
Sep 24 10:13:07 PM UTC 24 |
Sep 24 10:40:45 PM UTC 24 |
122246995731 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_ram_cfg.3497225500 |
|
|
Sep 24 10:40:46 PM UTC 24 |
Sep 24 10:40:48 PM UTC 24 |
80903425 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_pipeline.3467838485 |
|
|
Sep 24 10:35:32 PM UTC 24 |
Sep 24 10:40:56 PM UTC 24 |
5263878164 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_bijection.1453862118 |
|
|
Sep 24 10:39:09 PM UTC 24 |
Sep 24 10:40:59 PM UTC 24 |
14383750613 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_mem_walk.81698165 |
|
|
Sep 24 10:40:50 PM UTC 24 |
Sep 24 10:41:00 PM UTC 24 |
825308663 ps |
| T70 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_mem_partial_access.3813550160 |
|
|
Sep 24 10:40:57 PM UTC 24 |
Sep 24 10:41:04 PM UTC 24 |
93337155 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_regwen.4168000540 |
|
|
Sep 24 10:38:43 PM UTC 24 |
Sep 24 10:41:04 PM UTC 24 |
1966016079 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_all.3453838665 |
|
|
Sep 24 10:05:28 PM UTC 24 |
Sep 24 10:41:05 PM UTC 24 |
38506159371 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_alert_test.3393993328 |
|
|
Sep 24 10:41:04 PM UTC 24 |
Sep 24 10:41:06 PM UTC 24 |
105204989 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.3706360745 |
|
|
Sep 24 10:35:04 PM UTC 24 |
Sep 24 10:41:08 PM UTC 24 |
830653788 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_regwen.63365274 |
|
|
Sep 24 10:40:39 PM UTC 24 |
Sep 24 10:41:09 PM UTC 24 |
5399081548 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_access_during_key_req.66464768 |
|
|
Sep 24 10:24:41 PM UTC 24 |
Sep 24 10:41:14 PM UTC 24 |
34863166874 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_partial_access.2878341754 |
|
|
Sep 24 10:41:10 PM UTC 24 |
Sep 24 10:41:15 PM UTC 24 |
186213331 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_pipeline.2738609752 |
|
|
Sep 24 10:39:15 PM UTC 24 |
Sep 24 10:41:17 PM UTC 24 |
2426776852 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_smoke.3749427123 |
|
|
Sep 24 10:41:05 PM UTC 24 |
Sep 24 10:41:29 PM UTC 24 |
976196932 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_bijection.3919225541 |
|
|
Sep 24 10:41:08 PM UTC 24 |
Sep 24 10:41:34 PM UTC 24 |
4410642904 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_lc_escalation.1764528655 |
|
|
Sep 24 10:41:29 PM UTC 24 |
Sep 24 10:41:41 PM UTC 24 |
773755442 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_throughput_w_partial_write.3850452553 |
|
|
Sep 24 10:41:18 PM UTC 24 |
Sep 24 10:41:49 PM UTC 24 |
179546627 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_max_throughput.3553516782 |
|
|
Sep 24 10:41:16 PM UTC 24 |
Sep 24 10:41:56 PM UTC 24 |
196327405 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_access_during_key_req.2314921437 |
|
|
Sep 24 10:34:38 PM UTC 24 |
Sep 24 10:41:58 PM UTC 24 |
1276267728 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_ram_cfg.2484866280 |
|
|
Sep 24 10:41:57 PM UTC 24 |
Sep 24 10:41:59 PM UTC 24 |
98661773 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_mem_partial_access.550493317 |
|
|
Sep 24 10:42:00 PM UTC 24 |
Sep 24 10:42:04 PM UTC 24 |
247590796 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_mem_walk.145888311 |
|
|
Sep 24 10:41:59 PM UTC 24 |
Sep 24 10:42:15 PM UTC 24 |
184573864 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_regwen.2216153816 |
|
|
Sep 24 10:28:35 PM UTC 24 |
Sep 24 10:42:19 PM UTC 24 |
41384469410 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_alert_test.4027040261 |
|
|
Sep 24 10:42:19 PM UTC 24 |
Sep 24 10:42:21 PM UTC 24 |
30087809 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_multiple_keys.2880624766 |
|
|
Sep 24 10:33:02 PM UTC 24 |
Sep 24 10:42:58 PM UTC 24 |
7771499096 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_partial_access_b2b.220462491 |
|
|
Sep 24 10:30:12 PM UTC 24 |
Sep 24 10:43:11 PM UTC 24 |
28270975782 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_smoke.4054299868 |
|
|
Sep 24 10:42:23 PM UTC 24 |
Sep 24 10:43:14 PM UTC 24 |
1926050071 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.781436448 |
|
|
Sep 24 10:38:56 PM UTC 24 |
Sep 24 10:43:29 PM UTC 24 |
2055582792 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_bijection.2494025513 |
|
|
Sep 24 10:43:11 PM UTC 24 |
Sep 24 10:43:30 PM UTC 24 |
229055055 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_multiple_keys.1301939691 |
|
|
Sep 24 10:23:28 PM UTC 24 |
Sep 24 10:43:30 PM UTC 24 |
48884522192 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_pipeline.1815066903 |
|
|
Sep 24 10:37:51 PM UTC 24 |
Sep 24 10:43:34 PM UTC 24 |
2975445357 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_executable.3168372037 |
|
|
Sep 24 10:41:43 PM UTC 24 |
Sep 24 10:43:36 PM UTC 24 |
3821942402 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_partial_access.2966746205 |
|
|
Sep 24 10:43:30 PM UTC 24 |
Sep 24 10:43:40 PM UTC 24 |
147058519 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_lc_escalation.3413263981 |
|
|
Sep 24 10:43:37 PM UTC 24 |
Sep 24 10:43:44 PM UTC 24 |
2072644308 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_pipeline.1737999526 |
|
|
Sep 24 10:41:09 PM UTC 24 |
Sep 24 10:43:47 PM UTC 24 |
2853175538 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_max_throughput.1806801400 |
|
|
Sep 24 10:43:32 PM UTC 24 |
Sep 24 10:44:00 PM UTC 24 |
103213504 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_ram_cfg.3982218878 |
|
|
Sep 24 10:44:01 PM UTC 24 |
Sep 24 10:44:04 PM UTC 24 |
39100786 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_executable.2260187234 |
|
|
Sep 24 10:32:07 PM UTC 24 |
Sep 24 10:44:05 PM UTC 24 |
30831917051 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_mem_partial_access.1888380791 |
|
|
Sep 24 10:44:07 PM UTC 24 |
Sep 24 10:44:13 PM UTC 24 |
100489158 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_executable.3454808115 |
|
|
Sep 24 10:28:29 PM UTC 24 |
Sep 24 10:44:13 PM UTC 24 |
7131144636 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_mem_walk.1277663051 |
|
|
Sep 24 10:44:04 PM UTC 24 |
Sep 24 10:44:13 PM UTC 24 |
933213793 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_alert_test.2083983974 |
|
|
Sep 24 10:44:14 PM UTC 24 |
Sep 24 10:44:16 PM UTC 24 |
50981276 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_throughput_w_partial_write.3962501408 |
|
|
Sep 24 10:43:36 PM UTC 24 |
Sep 24 10:44:28 PM UTC 24 |
186278610 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_partial_access_b2b.1597102796 |
|
|
Sep 24 10:36:01 PM UTC 24 |
Sep 24 10:44:35 PM UTC 24 |
60270837162 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_smoke.1464226434 |
|
|
Sep 24 10:44:17 PM UTC 24 |
Sep 24 10:45:09 PM UTC 24 |
8935271092 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_partial_access_b2b.4160388747 |
|
|
Sep 24 10:39:18 PM UTC 24 |
Sep 24 10:45:28 PM UTC 24 |
4616344441 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_bijection.683870710 |
|
|
Sep 24 10:44:35 PM UTC 24 |
Sep 24 10:45:30 PM UTC 24 |
7847392494 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_all.1975938753 |
|
|
Sep 24 10:35:09 PM UTC 24 |
Sep 24 10:45:39 PM UTC 24 |
3670351634 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_partial_access.1798576887 |
|
|
Sep 24 10:45:29 PM UTC 24 |
Sep 24 10:45:45 PM UTC 24 |
1115714743 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_partial_access_b2b.1090752155 |
|
|
Sep 24 10:38:17 PM UTC 24 |
Sep 24 10:45:50 PM UTC 24 |
46675476164 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_lc_escalation.2384257017 |
|
|
Sep 24 10:45:51 PM UTC 24 |
Sep 24 10:46:04 PM UTC 24 |
2721591086 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_throughput_w_partial_write.4197187395 |
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Sep 24 10:45:46 PM UTC 24 |
Sep 24 10:46:07 PM UTC 24 |
476633462 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_multiple_keys.1812354240 |
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Sep 24 10:29:33 PM UTC 24 |
Sep 24 10:46:10 PM UTC 24 |
16292681424 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_max_throughput.3827515854 |
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Sep 24 10:45:40 PM UTC 24 |
Sep 24 10:46:16 PM UTC 24 |
98066581 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_ram_cfg.476381013 |
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Sep 24 10:46:18 PM UTC 24 |
Sep 24 10:46:20 PM UTC 24 |
88633239 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_mem_walk.1268526185 |
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Sep 24 10:46:21 PM UTC 24 |
Sep 24 10:46:33 PM UTC 24 |
268212318 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_multiple_keys.2246162863 |
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Sep 24 10:41:06 PM UTC 24 |
Sep 24 10:46:34 PM UTC 24 |
7138904657 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_pipeline.2181312194 |
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Sep 24 10:43:14 PM UTC 24 |
Sep 24 10:46:34 PM UTC 24 |
8420320064 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_mem_partial_access.843316341 |
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Sep 24 10:46:34 PM UTC 24 |
Sep 24 10:46:39 PM UTC 24 |
440304789 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_all.2671463991 |
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Sep 24 10:26:28 PM UTC 24 |
Sep 24 10:46:40 PM UTC 24 |
6087487636 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_executable.1375674612 |
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Sep 24 10:46:07 PM UTC 24 |
Sep 24 10:46:40 PM UTC 24 |
674917377 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_alert_test.1449990301 |
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Sep 24 10:46:40 PM UTC 24 |
Sep 24 10:46:42 PM UTC 24 |
12737383 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_access_during_key_req.3329995209 |
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Sep 24 10:32:06 PM UTC 24 |
Sep 24 10:46:45 PM UTC 24 |
3139071351 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_executable.907953949 |
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Sep 24 10:26:09 PM UTC 24 |
Sep 24 10:46:47 PM UTC 24 |
17500276497 ps |