| T800 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_partial_access.1314666722 |
|
|
Sep 24 10:46:48 PM UTC 24 |
Sep 24 10:46:52 PM UTC 24 |
103175787 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_smoke.4147414321 |
|
|
Sep 24 10:46:41 PM UTC 24 |
Sep 24 10:46:53 PM UTC 24 |
1064927088 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_access_during_key_req.2071921022 |
|
|
Sep 24 10:28:24 PM UTC 24 |
Sep 24 10:46:54 PM UTC 24 |
4461282988 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_regwen.2432366916 |
|
|
Sep 24 10:31:04 PM UTC 24 |
Sep 24 10:46:56 PM UTC 24 |
15474387892 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_access_during_key_req.990729166 |
|
|
Sep 24 10:39:56 PM UTC 24 |
Sep 24 10:46:57 PM UTC 24 |
3890273688 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_all.1329911339 |
|
|
Sep 24 10:32:50 PM UTC 24 |
Sep 24 10:47:01 PM UTC 24 |
44763006245 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_lc_escalation.1842147126 |
|
|
Sep 24 10:46:57 PM UTC 24 |
Sep 24 10:47:05 PM UTC 24 |
3260910211 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_bijection.2856472809 |
|
|
Sep 24 10:46:42 PM UTC 24 |
Sep 24 10:47:08 PM UTC 24 |
2627705789 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_all.1824102567 |
|
|
Sep 24 10:06:41 PM UTC 24 |
Sep 24 10:47:09 PM UTC 24 |
9097613120 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_ram_cfg.2054582743 |
|
|
Sep 24 10:47:08 PM UTC 24 |
Sep 24 10:47:10 PM UTC 24 |
27839252 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_mem_partial_access.3133488621 |
|
|
Sep 24 10:47:12 PM UTC 24 |
Sep 24 10:47:20 PM UTC 24 |
95027816 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_mem_walk.3272068711 |
|
|
Sep 24 10:47:10 PM UTC 24 |
Sep 24 10:47:27 PM UTC 24 |
2178926299 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_throughput_w_partial_write.2446336659 |
|
|
Sep 24 10:46:55 PM UTC 24 |
Sep 24 10:47:38 PM UTC 24 |
112828962 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_alert_test.4260419864 |
|
|
Sep 24 10:47:39 PM UTC 24 |
Sep 24 10:47:41 PM UTC 24 |
74047414 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_smoke.2040900897 |
|
|
Sep 24 10:47:42 PM UTC 24 |
Sep 24 10:48:02 PM UTC 24 |
845332855 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_all.741092046 |
|
|
Sep 24 09:48:26 PM UTC 24 |
Sep 24 10:48:18 PM UTC 24 |
52024712095 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_executable.3265535296 |
|
|
Sep 24 10:36:59 PM UTC 24 |
Sep 24 10:48:23 PM UTC 24 |
2576036446 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_max_throughput.1827893191 |
|
|
Sep 24 10:46:54 PM UTC 24 |
Sep 24 10:48:27 PM UTC 24 |
136046174 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_partial_access.1341792215 |
|
|
Sep 24 10:48:28 PM UTC 24 |
Sep 24 10:48:40 PM UTC 24 |
173990206 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_bijection.2885446173 |
|
|
Sep 24 10:48:18 PM UTC 24 |
Sep 24 10:48:42 PM UTC 24 |
4251577797 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_executable.3666062692 |
|
|
Sep 24 10:43:45 PM UTC 24 |
Sep 24 10:48:53 PM UTC 24 |
1960322492 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_max_throughput.2326445029 |
|
|
Sep 24 10:48:43 PM UTC 24 |
Sep 24 10:48:54 PM UTC 24 |
198876221 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_lc_escalation.1942970840 |
|
|
Sep 24 10:48:55 PM UTC 24 |
Sep 24 10:49:02 PM UTC 24 |
283166126 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_multiple_keys.1175207170 |
|
|
Sep 24 10:35:26 PM UTC 24 |
Sep 24 10:49:10 PM UTC 24 |
3610211700 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_regwen.398197152 |
|
|
Sep 24 10:32:14 PM UTC 24 |
Sep 24 10:49:14 PM UTC 24 |
9911585009 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.623456497 |
|
|
Sep 24 10:47:21 PM UTC 24 |
Sep 24 10:49:15 PM UTC 24 |
1020279625 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_ram_cfg.4031124900 |
|
|
Sep 24 10:49:15 PM UTC 24 |
Sep 24 10:49:18 PM UTC 24 |
41656044 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_mem_walk.4092856969 |
|
|
Sep 24 10:49:19 PM UTC 24 |
Sep 24 10:49:35 PM UTC 24 |
450857009 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_throughput_w_partial_write.1032006841 |
|
|
Sep 24 10:48:54 PM UTC 24 |
Sep 24 10:49:37 PM UTC 24 |
119109401 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_mem_partial_access.871982897 |
|
|
Sep 24 10:49:36 PM UTC 24 |
Sep 24 10:49:42 PM UTC 24 |
232142641 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.2311034256 |
|
|
Sep 24 10:49:38 PM UTC 24 |
Sep 24 10:49:50 PM UTC 24 |
828063579 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_alert_test.454196346 |
|
|
Sep 24 10:49:51 PM UTC 24 |
Sep 24 10:49:53 PM UTC 24 |
20093641 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_pipeline.2801356778 |
|
|
Sep 24 10:45:10 PM UTC 24 |
Sep 24 10:50:04 PM UTC 24 |
3036351149 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.272794593 |
|
|
Sep 24 10:42:05 PM UTC 24 |
Sep 24 10:50:05 PM UTC 24 |
15231806928 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_partial_access_b2b.3611141162 |
|
|
Sep 24 10:41:15 PM UTC 24 |
Sep 24 10:50:07 PM UTC 24 |
110537052589 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.1599884361 |
|
|
Sep 24 10:44:14 PM UTC 24 |
Sep 24 10:50:15 PM UTC 24 |
7747287616 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_access_during_key_req.55684041 |
|
|
Sep 24 10:43:40 PM UTC 24 |
Sep 24 10:50:25 PM UTC 24 |
1620325216 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_smoke.2483942965 |
|
|
Sep 24 10:49:54 PM UTC 24 |
Sep 24 10:50:30 PM UTC 24 |
375717124 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_all.1642266220 |
|
|
Sep 24 10:11:17 PM UTC 24 |
Sep 24 10:50:32 PM UTC 24 |
93498467965 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_max_throughput.341258955 |
|
|
Sep 24 10:50:26 PM UTC 24 |
Sep 24 10:50:41 PM UTC 24 |
70918414 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_lc_escalation.1739771560 |
|
|
Sep 24 10:50:33 PM UTC 24 |
Sep 24 10:50:42 PM UTC 24 |
729485412 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_pipeline.1411861419 |
|
|
Sep 24 10:46:46 PM UTC 24 |
Sep 24 10:50:42 PM UTC 24 |
13729579060 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.657550176 |
|
|
Sep 24 10:41:00 PM UTC 24 |
Sep 24 10:50:56 PM UTC 24 |
2336546738 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_ram_cfg.1501005624 |
|
|
Sep 24 10:50:56 PM UTC 24 |
Sep 24 10:50:59 PM UTC 24 |
208612723 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_mem_walk.3284635082 |
|
|
Sep 24 10:50:59 PM UTC 24 |
Sep 24 10:51:14 PM UTC 24 |
896392326 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_bijection.3645813900 |
|
|
Sep 24 10:50:06 PM UTC 24 |
Sep 24 10:51:15 PM UTC 24 |
13919181596 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_throughput_w_partial_write.3376422012 |
|
|
Sep 24 10:50:31 PM UTC 24 |
Sep 24 10:51:19 PM UTC 24 |
1434065269 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_mem_partial_access.4036174867 |
|
|
Sep 24 10:51:16 PM UTC 24 |
Sep 24 10:51:22 PM UTC 24 |
1512168850 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_alert_test.749964938 |
|
|
Sep 24 10:51:23 PM UTC 24 |
Sep 24 10:51:25 PM UTC 24 |
14701737 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_regwen.3252288223 |
|
|
Sep 24 10:43:48 PM UTC 24 |
Sep 24 10:51:27 PM UTC 24 |
4451900576 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_partial_access.3337520576 |
|
|
Sep 24 10:50:08 PM UTC 24 |
Sep 24 10:51:38 PM UTC 24 |
3049920066 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_all.220093338 |
|
|
Sep 24 10:21:23 PM UTC 24 |
Sep 24 10:51:50 PM UTC 24 |
19593368154 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_partial_access_b2b.1106878922 |
|
|
Sep 24 10:46:53 PM UTC 24 |
Sep 24 10:52:14 PM UTC 24 |
19034815894 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_partial_access.2472375692 |
|
|
Sep 24 10:52:16 PM UTC 24 |
Sep 24 10:52:18 PM UTC 24 |
89375415 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_smoke.2031895125 |
|
|
Sep 24 10:51:26 PM UTC 24 |
Sep 24 10:52:22 PM UTC 24 |
466321220 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_regwen.3006358633 |
|
|
Sep 24 10:27:31 PM UTC 24 |
Sep 24 10:52:32 PM UTC 24 |
77887695187 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_pipeline.1728210526 |
|
|
Sep 24 10:48:24 PM UTC 24 |
Sep 24 10:52:41 PM UTC 24 |
8948364413 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_bijection.920844770 |
|
|
Sep 24 10:51:39 PM UTC 24 |
Sep 24 10:52:49 PM UTC 24 |
2350505574 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_lc_escalation.2030036427 |
|
|
Sep 24 10:52:41 PM UTC 24 |
Sep 24 10:52:51 PM UTC 24 |
450627548 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_partial_access_b2b.28097049 |
|
|
Sep 24 10:45:32 PM UTC 24 |
Sep 24 10:52:53 PM UTC 24 |
9624604878 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_pipeline.2286532655 |
|
|
Sep 24 10:50:08 PM UTC 24 |
Sep 24 10:52:55 PM UTC 24 |
13426130378 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_ram_cfg.885619201 |
|
|
Sep 24 10:52:55 PM UTC 24 |
Sep 24 10:52:58 PM UTC 24 |
72376551 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_access_during_key_req.1720936612 |
|
|
Sep 24 10:38:34 PM UTC 24 |
Sep 24 10:52:59 PM UTC 24 |
3562581661 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_access_during_key_req.2003843738 |
|
|
Sep 24 10:31:00 PM UTC 24 |
Sep 24 10:53:05 PM UTC 24 |
12290213238 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_mem_partial_access.3616073330 |
|
|
Sep 24 10:53:00 PM UTC 24 |
Sep 24 10:53:08 PM UTC 24 |
126830551 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_mem_walk.578588201 |
|
|
Sep 24 10:52:59 PM UTC 24 |
Sep 24 10:53:08 PM UTC 24 |
1168571194 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_alert_test.2441083879 |
|
|
Sep 24 10:53:09 PM UTC 24 |
Sep 24 10:53:11 PM UTC 24 |
38319111 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_smoke.3421115939 |
|
|
Sep 24 10:53:12 PM UTC 24 |
Sep 24 10:53:27 PM UTC 24 |
277493155 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_executable.1013019468 |
|
|
Sep 24 10:39:58 PM UTC 24 |
Sep 24 10:53:37 PM UTC 24 |
30293894135 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_partial_access_b2b.1678002943 |
|
|
Sep 24 10:43:31 PM UTC 24 |
Sep 24 10:53:46 PM UTC 24 |
25756559441 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.2957960841 |
|
|
Sep 24 10:51:16 PM UTC 24 |
Sep 24 10:53:47 PM UTC 24 |
2263072010 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_max_throughput.1776084973 |
|
|
Sep 24 10:52:23 PM UTC 24 |
Sep 24 10:53:59 PM UTC 24 |
539645104 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_throughput_w_partial_write.1334790848 |
|
|
Sep 24 10:52:33 PM UTC 24 |
Sep 24 10:54:04 PM UTC 24 |
458216702 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_max_throughput.1679390261 |
|
|
Sep 24 10:54:05 PM UTC 24 |
Sep 24 10:54:15 PM UTC 24 |
113584249 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all.2672600787 |
|
|
Sep 24 09:45:45 PM UTC 24 |
Sep 24 10:54:15 PM UTC 24 |
13984455934 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_lc_escalation.412026880 |
|
|
Sep 24 10:54:16 PM UTC 24 |
Sep 24 10:54:25 PM UTC 24 |
901670431 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_throughput_w_partial_write.2281365165 |
|
|
Sep 24 10:54:16 PM UTC 24 |
Sep 24 10:54:29 PM UTC 24 |
139492803 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_executable.721924992 |
|
|
Sep 24 10:52:52 PM UTC 24 |
Sep 24 10:54:47 PM UTC 24 |
740393304 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_partial_access.2128228936 |
|
|
Sep 24 10:53:49 PM UTC 24 |
Sep 24 10:54:51 PM UTC 24 |
2836825337 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_ram_cfg.472187375 |
|
|
Sep 24 10:54:52 PM UTC 24 |
Sep 24 10:54:54 PM UTC 24 |
28097279 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_executable.1158982309 |
|
|
Sep 24 10:34:41 PM UTC 24 |
Sep 24 10:55:00 PM UTC 24 |
3159987742 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_partial_access_b2b.1701121195 |
|
|
Sep 24 10:48:41 PM UTC 24 |
Sep 24 10:55:05 PM UTC 24 |
4354822814 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_mem_partial_access.1364062707 |
|
|
Sep 24 10:55:01 PM UTC 24 |
Sep 24 10:55:08 PM UTC 24 |
66624406 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_mem_walk.980278871 |
|
|
Sep 24 10:54:55 PM UTC 24 |
Sep 24 10:55:09 PM UTC 24 |
438621913 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_bijection.1927481834 |
|
|
Sep 24 10:53:37 PM UTC 24 |
Sep 24 10:55:11 PM UTC 24 |
1041607996 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_alert_test.1479246183 |
|
|
Sep 24 10:55:10 PM UTC 24 |
Sep 24 10:55:12 PM UTC 24 |
19543737 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_access_during_key_req.2655667778 |
|
|
Sep 24 10:36:44 PM UTC 24 |
Sep 24 10:55:35 PM UTC 24 |
7599376758 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.3067388185 |
|
|
Sep 24 10:55:06 PM UTC 24 |
Sep 24 10:55:57 PM UTC 24 |
1547005764 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_multiple_keys.2123685550 |
|
|
Sep 24 10:39:08 PM UTC 24 |
Sep 24 10:56:06 PM UTC 24 |
23946660864 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_partial_access_b2b.2467339731 |
|
|
Sep 24 10:52:19 PM UTC 24 |
Sep 24 10:57:27 PM UTC 24 |
10059999028 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_executable.1020303825 |
|
|
Sep 24 10:49:11 PM UTC 24 |
Sep 24 10:57:31 PM UTC 24 |
45837894049 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_access_during_key_req.3890395036 |
|
|
Sep 24 10:50:41 PM UTC 24 |
Sep 24 10:57:37 PM UTC 24 |
14260802223 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_regwen.3254965256 |
|
|
Sep 24 10:46:10 PM UTC 24 |
Sep 24 10:57:39 PM UTC 24 |
23426109940 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_access_during_key_req.2817922616 |
|
|
Sep 24 10:46:05 PM UTC 24 |
Sep 24 10:58:00 PM UTC 24 |
6578316390 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_multiple_keys.654469220 |
|
|
Sep 24 10:42:59 PM UTC 24 |
Sep 24 10:58:08 PM UTC 24 |
9845511644 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_pipeline.3415774924 |
|
|
Sep 24 10:51:50 PM UTC 24 |
Sep 24 10:58:20 PM UTC 24 |
27004428041 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_partial_access_b2b.1815694510 |
|
|
Sep 24 10:50:16 PM UTC 24 |
Sep 24 10:58:24 PM UTC 24 |
59644356039 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_pipeline.3308251268 |
|
|
Sep 24 10:53:47 PM UTC 24 |
Sep 24 10:58:31 PM UTC 24 |
5372073443 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_regwen.1793903955 |
|
|
Sep 24 10:47:05 PM UTC 24 |
Sep 24 10:58:46 PM UTC 24 |
6946647864 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_all.290388653 |
|
|
Sep 24 10:23:04 PM UTC 24 |
Sep 24 10:58:52 PM UTC 24 |
249367297943 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_regwen.3529651632 |
|
|
Sep 24 10:34:43 PM UTC 24 |
Sep 24 10:59:33 PM UTC 24 |
4518203422 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all.1003870007 |
|
|
Sep 24 09:47:06 PM UTC 24 |
Sep 24 10:59:48 PM UTC 24 |
197011157795 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_all.2187756034 |
|
|
Sep 24 10:09:41 PM UTC 24 |
Sep 24 10:59:49 PM UTC 24 |
10688195923 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_partial_access_b2b.3912859161 |
|
|
Sep 24 10:54:00 PM UTC 24 |
Sep 24 11:00:08 PM UTC 24 |
26761002819 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_executable.3863592471 |
|
|
Sep 24 10:54:29 PM UTC 24 |
Sep 24 11:00:09 PM UTC 24 |
2147235763 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_regwen.3586436823 |
|
|
Sep 24 10:37:08 PM UTC 24 |
Sep 24 11:00:21 PM UTC 24 |
14112229877 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_regwen.2706635877 |
|
|
Sep 24 10:49:15 PM UTC 24 |
Sep 24 11:00:28 PM UTC 24 |
13688225049 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_access_during_key_req.903623991 |
|
|
Sep 24 10:52:50 PM UTC 24 |
Sep 24 11:00:47 PM UTC 24 |
9557726115 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_access_during_key_req.1116403309 |
|
|
Sep 24 10:46:58 PM UTC 24 |
Sep 24 11:01:53 PM UTC 24 |
20654731849 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_access_during_key_req.1466853038 |
|
|
Sep 24 10:41:35 PM UTC 24 |
Sep 24 11:02:10 PM UTC 24 |
15602000383 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_all.1397571573 |
|
|
Sep 24 10:46:35 PM UTC 24 |
Sep 24 11:02:26 PM UTC 24 |
3567771275 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_access_during_key_req.1033589599 |
|
|
Sep 24 10:49:03 PM UTC 24 |
Sep 24 11:02:36 PM UTC 24 |
11116297779 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_regwen.4008456104 |
|
|
Sep 24 10:41:50 PM UTC 24 |
Sep 24 11:03:32 PM UTC 24 |
3363836966 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_regwen.2867787572 |
|
|
Sep 24 10:54:48 PM UTC 24 |
Sep 24 11:03:37 PM UTC 24 |
13553006693 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_all.495474543 |
|
|
Sep 24 09:53:31 PM UTC 24 |
Sep 24 11:04:57 PM UTC 24 |
44298483038 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_multiple_keys.3732966422 |
|
|
Sep 24 10:37:41 PM UTC 24 |
Sep 24 11:05:02 PM UTC 24 |
64941430240 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_access_during_key_req.3819142406 |
|
|
Sep 24 10:54:25 PM UTC 24 |
Sep 24 11:05:03 PM UTC 24 |
11376669607 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_regwen.1267239096 |
|
|
Sep 24 10:50:43 PM UTC 24 |
Sep 24 11:05:25 PM UTC 24 |
54858899396 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_all.1127450908 |
|
|
Sep 24 10:04:16 PM UTC 24 |
Sep 24 11:05:48 PM UTC 24 |
59732299089 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_multiple_keys.721861248 |
|
|
Sep 24 10:46:41 PM UTC 24 |
Sep 24 11:05:50 PM UTC 24 |
7512293322 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_executable.3654372329 |
|
|
Sep 24 10:38:35 PM UTC 24 |
Sep 24 11:06:18 PM UTC 24 |
16449347348 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_multiple_keys.2352445499 |
|
|
Sep 24 10:53:28 PM UTC 24 |
Sep 24 11:08:35 PM UTC 24 |
90725559118 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_multiple_keys.2374825114 |
|
|
Sep 24 10:48:03 PM UTC 24 |
Sep 24 11:09:48 PM UTC 24 |
4029497140 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_regwen.220497823 |
|
|
Sep 24 10:52:53 PM UTC 24 |
Sep 24 11:09:49 PM UTC 24 |
12488464699 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.1700613266 |
|
|
Sep 24 10:53:06 PM UTC 24 |
Sep 24 11:09:50 PM UTC 24 |
3769912404 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_all.98478171 |
|
|
Sep 24 10:18:55 PM UTC 24 |
Sep 24 11:09:50 PM UTC 24 |
214775508084 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_all.1945890146 |
|
|
Sep 24 10:19:53 PM UTC 24 |
Sep 24 11:09:58 PM UTC 24 |
225876317087 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_all.3411630631 |
|
|
Sep 24 10:31:18 PM UTC 24 |
Sep 24 11:10:24 PM UTC 24 |
8499132581 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_executable.2906895331 |
|
|
Sep 24 10:50:42 PM UTC 24 |
Sep 24 11:11:21 PM UTC 24 |
53761017430 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_multiple_keys.3580676240 |
|
|
Sep 24 10:51:28 PM UTC 24 |
Sep 24 11:11:37 PM UTC 24 |
54532604033 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_multiple_keys.1524811806 |
|
|
Sep 24 10:44:28 PM UTC 24 |
Sep 24 11:12:30 PM UTC 24 |
37318011956 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_all.4210157878 |
|
|
Sep 24 10:16:05 PM UTC 24 |
Sep 24 11:14:35 PM UTC 24 |
62308162378 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_executable.1240177304 |
|
|
Sep 24 10:47:01 PM UTC 24 |
Sep 24 11:15:30 PM UTC 24 |
65203161955 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_all.2866570230 |
|
|
Sep 24 10:38:58 PM UTC 24 |
Sep 24 11:15:41 PM UTC 24 |
53631815006 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_multiple_keys.3301152255 |
|
|
Sep 24 10:50:05 PM UTC 24 |
Sep 24 11:16:28 PM UTC 24 |
68578143136 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_all.6462854 |
|
|
Sep 24 10:53:09 PM UTC 24 |
Sep 24 11:17:08 PM UTC 24 |
11811451545 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_all.1374185157 |
|
|
Sep 24 10:55:09 PM UTC 24 |
Sep 24 11:21:30 PM UTC 24 |
136246263128 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_all.2045553872 |
|
|
Sep 24 10:27:50 PM UTC 24 |
Sep 24 11:25:09 PM UTC 24 |
247248122725 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_all.1970955624 |
|
|
Sep 24 10:17:29 PM UTC 24 |
Sep 24 11:30:15 PM UTC 24 |
71601084498 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_all.3374853299 |
|
|
Sep 24 10:49:42 PM UTC 24 |
Sep 24 11:40:04 PM UTC 24 |
332135606124 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_all.2790361142 |
|
|
Sep 24 10:44:14 PM UTC 24 |
Sep 24 11:42:49 PM UTC 24 |
175529328337 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_all.1638444165 |
|
|
Sep 24 10:29:03 PM UTC 24 |
Sep 24 11:43:02 PM UTC 24 |
52056645601 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_all.1769684021 |
|
|
Sep 24 10:51:20 PM UTC 24 |
Sep 24 11:43:43 PM UTC 24 |
36904047557 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_all.2683610219 |
|
|
Sep 24 09:51:32 PM UTC 24 |
Sep 24 11:44:19 PM UTC 24 |
18919993547 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_all.1878220590 |
|
|
Sep 24 10:37:38 PM UTC 24 |
Sep 24 11:46:01 PM UTC 24 |
106501211808 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_all.1846710592 |
|
|
Sep 24 10:47:28 PM UTC 24 |
Sep 24 11:48:06 PM UTC 24 |
299593451413 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_all.3432322211 |
|
|
Sep 24 10:41:01 PM UTC 24 |
Sep 24 11:52:44 PM UTC 24 |
205496323672 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_all.432646072 |
|
|
Sep 24 10:42:15 PM UTC 24 |
Sep 25 12:08:19 AM UTC 24 |
31901373220 ps |
| T86 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1265423314 |
|
|
Sep 24 10:55:11 PM UTC 24 |
Sep 24 10:55:15 PM UTC 24 |
1506050748 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2759839307 |
|
|
Sep 24 10:55:13 PM UTC 24 |
Sep 24 10:55:18 PM UTC 24 |
22928853 ps |
| T103 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1401890809 |
|
|
Sep 24 10:55:16 PM UTC 24 |
Sep 24 10:55:20 PM UTC 24 |
290763206 ps |
| T96 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3969328343 |
|
|
Sep 24 10:55:19 PM UTC 24 |
Sep 24 10:55:21 PM UTC 24 |
27949690 ps |
| T97 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3456022612 |
|
|
Sep 24 10:55:21 PM UTC 24 |
Sep 24 10:55:23 PM UTC 24 |
16547782 ps |
| T98 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3481338895 |
|
|
Sep 24 10:55:22 PM UTC 24 |
Sep 24 10:55:25 PM UTC 24 |
145061028 ps |
| T99 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3059334385 |
|
|
Sep 24 10:55:24 PM UTC 24 |
Sep 24 10:55:26 PM UTC 24 |
58221365 ps |
| T87 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1675578614 |
|
|
Sep 24 10:55:26 PM UTC 24 |
Sep 24 10:55:28 PM UTC 24 |
42569651 ps |
| T88 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.32929644 |
|
|
Sep 24 10:55:29 PM UTC 24 |
Sep 24 10:55:34 PM UTC 24 |
281943741 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3536491799 |
|
|
Sep 24 10:55:30 PM UTC 24 |
Sep 24 10:55:35 PM UTC 24 |
135917646 ps |
| T100 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.191782051 |
|
|
Sep 24 10:55:36 PM UTC 24 |
Sep 24 10:55:38 PM UTC 24 |
81168322 ps |
| T104 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2864052326 |
|
|
Sep 24 10:55:34 PM UTC 24 |
Sep 24 10:55:38 PM UTC 24 |
502979927 ps |
| T101 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3975689791 |
|
|
Sep 24 10:55:37 PM UTC 24 |
Sep 24 10:55:39 PM UTC 24 |
21243517 ps |
| T51 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3997048850 |
|
|
Sep 24 10:55:39 PM UTC 24 |
Sep 24 10:55:41 PM UTC 24 |
12746141 ps |
| T52 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1767453108 |
|
|
Sep 24 10:55:40 PM UTC 24 |
Sep 24 10:55:42 PM UTC 24 |
23810590 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3717868072 |
|
|
Sep 24 10:55:39 PM UTC 24 |
Sep 24 10:55:43 PM UTC 24 |
423418615 ps |
| T53 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.4222016656 |
|
|
Sep 24 10:55:43 PM UTC 24 |
Sep 24 10:55:47 PM UTC 24 |
764166502 ps |
| T105 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.701059684 |
|
|
Sep 24 10:55:47 PM UTC 24 |
Sep 24 10:55:50 PM UTC 24 |
252990450 ps |
| T54 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1281140646 |
|
|
Sep 24 10:55:48 PM UTC 24 |
Sep 24 10:55:50 PM UTC 24 |
30629962 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.164929857 |
|
|
Sep 24 10:55:43 PM UTC 24 |
Sep 24 10:55:50 PM UTC 24 |
78138531 ps |
| T89 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2340959481 |
|
|
Sep 24 10:55:51 PM UTC 24 |
Sep 24 10:55:53 PM UTC 24 |
62387478 ps |
| T55 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.672433323 |
|
|
Sep 24 10:55:51 PM UTC 24 |
Sep 24 10:55:53 PM UTC 24 |
53246071 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3350781437 |
|
|
Sep 24 10:55:51 PM UTC 24 |
Sep 24 10:55:55 PM UTC 24 |
44043310 ps |
| T56 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3599179372 |
|
|
Sep 24 10:55:54 PM UTC 24 |
Sep 24 10:55:56 PM UTC 24 |
37925685 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.967294089 |
|
|
Sep 24 10:55:54 PM UTC 24 |
Sep 24 10:55:58 PM UTC 24 |
169392894 ps |
| T57 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.507247774 |
|
|
Sep 24 10:55:55 PM UTC 24 |
Sep 24 10:56:01 PM UTC 24 |
2540565442 ps |
| T58 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2566472231 |
|
|
Sep 24 10:55:59 PM UTC 24 |
Sep 24 10:56:01 PM UTC 24 |
55558434 ps |
| T128 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.921575996 |
|
|
Sep 24 10:55:58 PM UTC 24 |
Sep 24 10:56:02 PM UTC 24 |
1045645453 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2808736035 |
|
|
Sep 24 10:55:58 PM UTC 24 |
Sep 24 10:56:04 PM UTC 24 |
124169294 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2361321064 |
|
|
Sep 24 10:56:02 PM UTC 24 |
Sep 24 10:56:04 PM UTC 24 |
32410535 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1492168223 |
|
|
Sep 24 10:56:02 PM UTC 24 |
Sep 24 10:56:05 PM UTC 24 |
879715065 ps |
| T59 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.4062447328 |
|
|
Sep 24 10:56:03 PM UTC 24 |
Sep 24 10:56:05 PM UTC 24 |
88284541 ps |
| T60 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.624238356 |
|
|
Sep 24 10:56:04 PM UTC 24 |
Sep 24 10:56:07 PM UTC 24 |
61594378 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.833518936 |
|
|
Sep 24 10:56:06 PM UTC 24 |
Sep 24 10:56:08 PM UTC 24 |
24853357 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3223331890 |
|
|
Sep 24 10:56:07 PM UTC 24 |
Sep 24 10:56:09 PM UTC 24 |
50926116 ps |
| T61 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.304404786 |
|
|
Sep 24 10:56:06 PM UTC 24 |
Sep 24 10:56:10 PM UTC 24 |
909442351 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2572274090 |
|
|
Sep 24 10:56:06 PM UTC 24 |
Sep 24 10:56:10 PM UTC 24 |
211290903 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3095497430 |
|
|
Sep 24 10:56:08 PM UTC 24 |
Sep 24 10:56:10 PM UTC 24 |
43646538 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3357522136 |
|
|
Sep 24 10:56:07 PM UTC 24 |
Sep 24 10:56:11 PM UTC 24 |
161499962 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3098088646 |
|
|
Sep 24 10:56:10 PM UTC 24 |
Sep 24 10:56:12 PM UTC 24 |
28540288 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3050877282 |
|
|
Sep 24 10:56:11 PM UTC 24 |
Sep 24 10:56:13 PM UTC 24 |
49976543 ps |
| T62 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3308404651 |
|
|
Sep 24 10:56:11 PM UTC 24 |
Sep 24 10:56:13 PM UTC 24 |
54955422 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3964819915 |
|
|
Sep 24 10:56:11 PM UTC 24 |
Sep 24 10:56:15 PM UTC 24 |
497322927 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2184331653 |
|
|
Sep 24 10:56:14 PM UTC 24 |
Sep 24 10:56:16 PM UTC 24 |
67112046 ps |
| T63 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.271938097 |
|
|
Sep 24 10:56:13 PM UTC 24 |
Sep 24 10:56:17 PM UTC 24 |
250827897 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3369467446 |
|
|
Sep 24 10:56:15 PM UTC 24 |
Sep 24 10:56:17 PM UTC 24 |
18846255 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.197195609 |
|
|
Sep 24 10:56:14 PM UTC 24 |
Sep 24 10:56:19 PM UTC 24 |
345103163 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2263216277 |
|
|
Sep 24 10:56:16 PM UTC 24 |
Sep 24 10:56:19 PM UTC 24 |
449273592 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3742498286 |
|
|
Sep 24 10:56:14 PM UTC 24 |
Sep 24 10:56:20 PM UTC 24 |
65049903 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1702633386 |
|
|
Sep 24 10:56:18 PM UTC 24 |
Sep 24 10:56:22 PM UTC 24 |
889351385 ps |
| T64 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3651708554 |
|
|
Sep 24 10:56:20 PM UTC 24 |
Sep 24 10:56:22 PM UTC 24 |
40336339 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3581185827 |
|
|
Sep 24 10:56:19 PM UTC 24 |
Sep 24 10:56:23 PM UTC 24 |
62185479 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.698577439 |
|
|
Sep 24 10:56:20 PM UTC 24 |
Sep 24 10:56:23 PM UTC 24 |
137488898 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2822895765 |
|
|
Sep 24 10:56:21 PM UTC 24 |
Sep 24 10:56:23 PM UTC 24 |
12947738 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2936100616 |
|
|
Sep 24 10:56:24 PM UTC 24 |
Sep 24 10:56:26 PM UTC 24 |
42038126 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3663820782 |
|
|
Sep 24 10:56:23 PM UTC 24 |
Sep 24 10:56:26 PM UTC 24 |
123259705 ps |
| T65 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.230899349 |
|
|
Sep 24 10:56:23 PM UTC 24 |
Sep 24 10:56:27 PM UTC 24 |
1165493634 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1466361955 |
|
|
Sep 24 10:56:24 PM UTC 24 |
Sep 24 10:56:27 PM UTC 24 |
2779628374 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3939032767 |
|
|
Sep 24 10:56:24 PM UTC 24 |
Sep 24 10:56:28 PM UTC 24 |
54578991 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2233798677 |
|
|
Sep 24 10:56:28 PM UTC 24 |
Sep 24 10:56:30 PM UTC 24 |
17554699 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3760745441 |
|
|
Sep 24 10:56:28 PM UTC 24 |
Sep 24 10:56:31 PM UTC 24 |
59139758 ps |
| T66 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3190855177 |
|
|
Sep 24 10:56:30 PM UTC 24 |
Sep 24 10:56:32 PM UTC 24 |
38205202 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1818870243 |
|
|
Sep 24 10:56:29 PM UTC 24 |
Sep 24 10:56:33 PM UTC 24 |
363970237 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1504164671 |
|
|
Sep 24 10:56:32 PM UTC 24 |
Sep 24 10:56:34 PM UTC 24 |
12059602 ps |
| T71 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1755424602 |
|
|
Sep 24 10:56:28 PM UTC 24 |
Sep 24 10:56:34 PM UTC 24 |
464098236 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1874958136 |
|
|
Sep 24 10:56:33 PM UTC 24 |
Sep 24 10:56:36 PM UTC 24 |
64231317 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_errors.70188066 |
|
|
Sep 24 10:56:29 PM UTC 24 |
Sep 24 10:56:37 PM UTC 24 |
484176460 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3739855457 |
|
|
Sep 24 10:56:38 PM UTC 24 |
Sep 24 10:56:40 PM UTC 24 |
12975169 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.837527808 |
|
|
Sep 24 10:56:38 PM UTC 24 |
Sep 24 10:56:40 PM UTC 24 |
30758942 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1242154494 |
|
|
Sep 24 10:56:34 PM UTC 24 |
Sep 24 10:56:41 PM UTC 24 |
805166252 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2575039272 |
|
|
Sep 24 10:56:36 PM UTC 24 |
Sep 24 10:56:41 PM UTC 24 |
536855738 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3762448348 |
|
|
Sep 24 10:56:35 PM UTC 24 |
Sep 24 10:56:41 PM UTC 24 |
115783073 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.4276014444 |
|
|
Sep 24 10:56:42 PM UTC 24 |
Sep 24 10:56:44 PM UTC 24 |
47891566 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3309308441 |
|
|
Sep 24 10:56:43 PM UTC 24 |
Sep 24 10:56:45 PM UTC 24 |
49670530 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3964303058 |
|
|
Sep 24 10:56:42 PM UTC 24 |
Sep 24 10:56:46 PM UTC 24 |
414558228 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.42797146 |
|
|
Sep 24 10:56:42 PM UTC 24 |
Sep 24 10:56:46 PM UTC 24 |
83925092 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2285684959 |
|
|
Sep 24 10:56:45 PM UTC 24 |
Sep 24 10:56:47 PM UTC 24 |
58118830 ps |
| T132 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.67764612 |
|
|
Sep 24 10:56:43 PM UTC 24 |
Sep 24 10:56:48 PM UTC 24 |
189489009 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1361867890 |
|
|
Sep 24 10:56:46 PM UTC 24 |
Sep 24 10:56:48 PM UTC 24 |
46698543 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3800313395 |
|
|
Sep 24 10:56:49 PM UTC 24 |
Sep 24 10:56:51 PM UTC 24 |
12757988 ps |
| T72 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2491049706 |
|
|
Sep 24 10:56:47 PM UTC 24 |
Sep 24 10:56:51 PM UTC 24 |
321732913 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1076483679 |
|
|
Sep 24 10:56:47 PM UTC 24 |
Sep 24 10:56:51 PM UTC 24 |
616417542 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3149537946 |
|
|
Sep 24 10:56:50 PM UTC 24 |
Sep 24 10:56:52 PM UTC 24 |
170504170 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1422994081 |
|
|
Sep 24 10:56:51 PM UTC 24 |
Sep 24 10:56:54 PM UTC 24 |
101377193 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.4148270804 |
|
|
Sep 24 10:56:47 PM UTC 24 |
Sep 24 10:56:55 PM UTC 24 |
607595988 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1972530740 |
|
|
Sep 24 10:56:55 PM UTC 24 |
Sep 24 10:56:57 PM UTC 24 |
35435106 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.380264126 |
|
|
Sep 24 10:56:53 PM UTC 24 |
Sep 24 10:56:57 PM UTC 24 |
273258050 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1186297649 |
|
|
Sep 24 10:56:53 PM UTC 24 |
Sep 24 10:56:58 PM UTC 24 |
155024467 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.368833802 |
|
|
Sep 24 10:56:56 PM UTC 24 |
Sep 24 10:56:59 PM UTC 24 |
20016372 ps |
| T73 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2765124241 |
|
|
Sep 24 10:56:53 PM UTC 24 |
Sep 24 10:57:00 PM UTC 24 |
2185519104 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3834914431 |
|
|
Sep 24 10:56:59 PM UTC 24 |
Sep 24 10:57:02 PM UTC 24 |
46613436 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.98135161 |
|
|
Sep 24 10:57:01 PM UTC 24 |
Sep 24 10:57:03 PM UTC 24 |
49451940 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1898314089 |
|
|
Sep 24 10:57:03 PM UTC 24 |
Sep 24 10:57:05 PM UTC 24 |
81937120 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2331616180 |
|
|
Sep 24 10:57:00 PM UTC 24 |
Sep 24 10:57:05 PM UTC 24 |
356141915 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.4254705574 |
|
|
Sep 24 10:56:59 PM UTC 24 |
Sep 24 10:57:06 PM UTC 24 |
3834709743 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3454109891 |
|
|
Sep 24 10:57:04 PM UTC 24 |
Sep 24 10:57:07 PM UTC 24 |
44394142 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.998819507 |
|
|
Sep 24 10:57:00 PM UTC 24 |
Sep 24 10:57:07 PM UTC 24 |
81778505 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1969300043 |
|
|
Sep 24 10:57:08 PM UTC 24 |
Sep 24 10:57:10 PM UTC 24 |
60203153 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3057913225 |
|
|
Sep 24 10:57:08 PM UTC 24 |
Sep 24 10:57:10 PM UTC 24 |
41342408 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1958281412 |
|
|
Sep 24 10:57:08 PM UTC 24 |
Sep 24 10:57:12 PM UTC 24 |
299645009 ps |
| T1006 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3174444778 |
|
|
Sep 24 10:57:07 PM UTC 24 |
Sep 24 10:57:12 PM UTC 24 |
437931103 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.419822596 |
|
|
Sep 24 10:57:06 PM UTC 24 |
Sep 24 10:57:13 PM UTC 24 |
457828982 ps |