Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13619335

1

T1

87

T2

121

T3

2933

full_word

54260288

1

T1

895

T2

584

T3

672

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	67879323	1			T1	982		T2	705		T3	3605
auto[TlIntgErrCmd]	95	1			T102	5		T103	3		T104	2
auto[TlIntgErrData]	108	1			T102	6		T103	5		T104	3
auto[TlIntgErrBoth]	97	1			T102	9		T103	2		T104	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30940477

1

T1

462

T2

355

T3

1857

auto[1]

36939146

1

T1

520

T2

350

T3

1748

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6492028	1			T1	44		T2	62		T3	1526
auto[TlIntgErrNone]	partial	auto[1]	7127029	1			T1	43		T2	59		T3	1407
auto[TlIntgErrNone]	full_word	auto[0]	24448314	1			T1	418		T2	293		T3	331
auto[TlIntgErrNone]	full_word	auto[1]	29811952	1			T1	477		T2	291		T3	341
auto[TlIntgErrCmd]	partial	auto[0]	31	1			T102	1		T103	2		T104	1
auto[TlIntgErrCmd]	partial	auto[1]	55	1			T102	3		T103	1		T104	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T112	1		T117	1		T118	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T102	1		T119	2		T117	1
auto[TlIntgErrData]	partial	auto[0]	51	1			T102	2		T103	3		T104	1
auto[TlIntgErrData]	partial	auto[1]	50	1			T102	4		T103	2		T104	2
auto[TlIntgErrData]	full_word	auto[0]	4	1			T112	1		T117	1		T120	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T113	1		T110	1		T118	1
auto[TlIntgErrBoth]	partial	auto[0]	42	1			T102	4		T103	1		T104	3
auto[TlIntgErrBoth]	partial	auto[1]	49	1			T102	4		T103	1		T104	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T110	1		T117	1		T111	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T102	1		T104	1		T112	1