Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	770732	1			T1	109		T32	372		T8	28
auto[1]	10298284	1			T1	35		T2	353		T3	1667
auto[2]	631816	1			T1	116		T32	351		T8	24
auto[3]	10168330	1			T1	21		T2	349		T3	1566

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14193748	1			T1	216		T2	488		T3	146
auto[1]	2078313	1			T1	32		T2	93		T3	482
auto[2]	2096728	1			T1	29		T2	100		T3	569
auto[3]	3500373	1			T1	4		T2	21		T3	2036

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8107326

1

T1

280

T2

702

T3

3232

auto[1]

13761836

1

T1

1

T3

1

T12

5

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	271414	1			T1	92		T32	316		T8	25
auto[0]	auto[0]	auto[1]	27551	1			T1	9		T32	21		T8	2
auto[0]	auto[0]	auto[2]	27340	1			T1	7		T32	32		T8	1
auto[0]	auto[0]	auto[3]	5978	1			T32	3		T136	8		T79	50
auto[0]	auto[1]	auto[0]	3070712	1			T1	20		T2	244		T3	73
auto[0]	auto[1]	auto[1]	321486	1			T1	9		T2	47		T3	215
auto[0]	auto[1]	auto[2]	310753	1			T1	4		T2	54		T3	339
auto[0]	auto[1]	auto[3]	69026	1			T1	2		T2	8		T3	1040
auto[0]	auto[2]	auto[0]	223038	1			T1	94		T32	313		T8	18
auto[0]	auto[2]	auto[1]	22795	1			T1	12		T32	18		T8	3
auto[0]	auto[2]	auto[2]	26758	1			T1	10		T32	20		T8	3
auto[0]	auto[2]	auto[3]	4970	1			T136	8		T55	1		T42	1
auto[0]	auto[3]	auto[0]	3025140	1			T1	10		T2	244		T3	73
auto[0]	auto[3]	auto[1]	306282	1			T1	1		T2	46		T3	266
auto[0]	auto[3]	auto[2]	323505	1			T1	8		T2	46		T3	230
auto[0]	auto[3]	auto[3]	70578	1			T1	2		T2	13		T3	996
auto[1]	auto[0]	auto[0]	14777	1			T98	183		T137	1		T135	827
auto[1]	auto[0]	auto[1]	65684	1			T1	1		T98	781		T138	1
auto[1]	auto[0]	auto[2]	65112	1			T98	809		T135	3887		T123	1
auto[1]	auto[0]	auto[3]	292876	1			T98	3638		T79	1		T135	17991
auto[1]	auto[1]	auto[0]	3791336	1			T12	2		T31	5		T33	2
auto[1]	auto[1]	auto[1]	667128	1			T88	1		T89	1		T94	2656
auto[1]	auto[1]	auto[2]	634293	1			T31	1		T94	2593		T139	1
auto[1]	auto[1]	auto[3]	1433550	1			T89	3		T94	222		T140	1
auto[1]	auto[2]	auto[0]	11134	1			T137	1		T44	2		T138	3
auto[1]	auto[2]	auto[1]	49142	1			T135	3650		T141	1098		T142	4472
auto[1]	auto[2]	auto[2]	53666	1			T98	686		T135	2680		T141	1673
auto[1]	auto[2]	auto[3]	240313	1			T98	3187		T44	1		T135	12034
auto[1]	auto[3]	auto[0]	3786197	1			T12	3		T31	2		T33	4
auto[1]	auto[3]	auto[1]	618245	1			T3	1		T7	1		T89	1
auto[1]	auto[3]	auto[2]	655301	1			T89	2		T94	2535		T95	5219
auto[1]	auto[3]	auto[3]	1383082	1			T89	6		T94	263		T140	1