Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.50	100.00	91.92	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	329942355	190192	0	0
ctrl_regwen_rd_A	329942355	5415	0	0
exec_rd_A	329942355	5022	0	0
exec_regwen_rd_A	329942355	5169	0	0
readback_rd_A	329942355	5818	0	0
readback_regwen_rd_A	329942355	2810	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329942355	190192	0	0
T7	35534	0	0	0
T16	2851	0	0	0
T20	0	1504	0	0
T21	0	2670	0	0
T24	19955	849	0	0
T25	0	2929	0	0
T26	0	4715	0	0
T27	2216	0	0	0
T31	15999	0	0	0
T32	23837	0	0	0
T33	5706	0	0	0
T34	4064	0	0	0
T35	22172	0	0	0
T43	0	4260	0	0
T55	0	1770	0	0
T56	0	1334	0	0
T57	0	861	0	0
T58	0	3727	0	0
T59	9115	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329942355	5415	0	0
T7	35534	0	0	0
T16	2851	0	0	0
T24	19955	93	0	0
T26	0	313	0	0
T27	2216	0	0	0
T31	15999	0	0	0
T32	23837	0	0	0
T33	5706	0	0	0
T34	4064	0	0	0
T35	22172	0	0	0
T43	0	397	0	0
T48	0	100	0	0
T49	0	166	0	0
T55	0	170	0	0
T57	0	104	0	0
T59	9115	0	0	0
T105	0	290	0	0
T106	0	309	0	0
T107	0	479	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329942355	5022	0	0
T7	35534	0	0	0
T16	2851	0	0	0
T24	19955	82	0	0
T26	0	377	0	0
T27	2216	0	0	0
T31	15999	0	0	0
T32	23837	0	0	0
T33	5706	0	0	0
T34	4064	0	0	0
T35	22172	0	0	0
T43	0	303	0	0
T48	0	107	0	0
T49	0	91	0	0
T55	0	125	0	0
T57	0	94	0	0
T59	9115	0	0	0
T105	0	345	0	0
T106	0	319	0	0
T107	0	450	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329942355	5169	0	0
T7	35534	0	0	0
T16	2851	0	0	0
T24	19955	108	0	0
T26	0	286	0	0
T27	2216	0	0	0
T31	15999	0	0	0
T32	23837	0	0	0
T33	5706	0	0	0
T34	4064	0	0	0
T35	22172	0	0	0
T43	0	345	0	0
T48	0	99	0	0
T49	0	180	0	0
T55	0	143	0	0
T57	0	58	0	0
T59	9115	0	0	0
T105	0	302	0	0
T106	0	280	0	0
T107	0	410	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329942355	5818	0	0
T7	35534	0	0	0
T16	2851	0	0	0
T22	0	40	0	0
T24	19955	66	0	0
T26	0	361	0	0
T27	2216	0	0	0
T31	15999	0	0	0
T32	23837	0	0	0
T33	5706	0	0	0
T34	4064	0	0	0
T35	22172	0	0	0
T43	0	364	0	0
T48	0	71	0	0
T55	0	80	0	0
T57	0	68	0	0
T59	9115	0	0	0
T105	0	398	0	0
T108	0	96	0	0
T109	0	176	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329942355	2810	0	0
T7	35534	0	0	0
T16	2851	0	0	0
T24	19955	36	0	0
T26	0	301	0	0
T27	2216	0	0	0
T31	15999	0	0	0
T32	23837	0	0	0
T33	5706	0	0	0
T34	4064	0	0	0
T35	22172	0	0	0
T43	0	265	0	0
T48	0	68	0	0
T49	0	96	0	0
T55	0	117	0	0
T57	0	81	0	0
T59	9115	0	0	0
T105	0	189	0	0
T106	0	334	0	0
T107	0	371	0	0