Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13709677

1

T5

1865

T6

90

T10

542

full_word

56186875

1

T2

92

T4

3071

T5

133

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	69896262	1			T2	92		T4	3071		T5	1998
auto[TlIntgErrCmd]	100	1			T124	7		T125	2		T126	4
auto[TlIntgErrData]	99	1			T124	10		T125	3		T126	4
auto[TlIntgErrBoth]	91	1			T124	3		T125	5		T126	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31673930

1

T4

1024

T5

855

T6

486

auto[1]

38222622

1

T2

92

T4

2047

T5

1143

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6513226	1			T5	840		T6	39		T10	273
auto[TlIntgErrNone]	partial	auto[1]	7196181	1			T5	1025		T6	51		T10	269
auto[TlIntgErrNone]	full_word	auto[0]	25160567	1			T4	1024		T5	15		T6	447
auto[TlIntgErrNone]	full_word	auto[1]	31026288	1			T2	92		T4	2047		T5	118
auto[TlIntgErrCmd]	partial	auto[0]	46	1			T124	7		T126	3		T162	4
auto[TlIntgErrCmd]	partial	auto[1]	46	1			T125	2		T126	1		T162	5
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T166	1		T168	1		T169	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T163	1		T165	1		-	-
auto[TlIntgErrData]	partial	auto[0]	49	1			T124	6		T125	1		T126	2
auto[TlIntgErrData]	partial	auto[1]	45	1			T124	4		T125	2		T126	2
auto[TlIntgErrData]	full_word	auto[0]	2	1			T167	1		T170	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	3	1			T171	1		T172	1		T173	1
auto[TlIntgErrBoth]	partial	auto[0]	32	1			T124	2		T125	2		T126	1
auto[TlIntgErrBoth]	partial	auto[1]	52	1			T124	1		T125	1		T126	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T125	1		T172	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T125	1		T162	1		T165	1