Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13008329

1

T1

34

T4

10

T5

863

full_word

55598794

1

T1

3

T4

46

T5

72

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	68606833	1			T1	37		T4	56		T5	935
auto[TlIntgErrCmd]	92	1			T60	3		T61	2		T62	2
auto[TlIntgErrData]	107	1			T60	5		T61	6		T62	4
auto[TlIntgErrBoth]	91	1			T60	2		T61	2		T62	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31383850

1

T1

20

T4

31

T5

352

auto[1]

37223273

1

T1

17

T4

25

T5

583

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6198627	1			T1	18		T4	5		T5	349
auto[TlIntgErrNone]	partial	auto[1]	6809434	1			T1	16		T4	5		T5	514
auto[TlIntgErrNone]	full_word	auto[0]	25185088	1			T1	2		T4	26		T5	3
auto[TlIntgErrNone]	full_word	auto[1]	30413684	1			T1	1		T4	20		T5	69
auto[TlIntgErrCmd]	partial	auto[0]	40	1			T61	2		T62	2		T113	2
auto[TlIntgErrCmd]	partial	auto[1]	49	1			T60	3		T113	6		T117	4
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T115	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T119	1		T121	1		-	-
auto[TlIntgErrData]	partial	auto[0]	48	1			T60	3		T62	2		T113	5
auto[TlIntgErrData]	partial	auto[1]	48	1			T60	2		T61	6		T62	2
auto[TlIntgErrData]	full_word	auto[0]	2	1			T119	1		T120	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	9	1			T113	1		T114	2		T119	1
auto[TlIntgErrBoth]	partial	auto[0]	42	1			T61	2		T62	2		T113	2
auto[TlIntgErrBoth]	partial	auto[1]	41	1			T60	2		T62	2		T113	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T122	1		T123	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T114	1		T123	1		T124	1