Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	726353	1			T7	31		T28	26		T9	1
auto[1]	9846869	1			T5	803		T7	5		T11	1553
auto[2]	598792	1			T7	29		T28	19		T9	2
auto[3]	9719962	1			T5	1094		T10	1		T7	5

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13697003	1			T5	9		T7	60		T11	2144
auto[1]	1972104	1			T5	124		T7	5		T11	476
auto[2]	1993974	1			T5	184		T10	1		T7	4
auto[3]	3228895	1			T5	1580		T7	1		T11	127

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8272827

1

T5

1895

T10

1

T7

70

auto[1]

12619149

1

T5

2

T8

1

T36

5

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	265825	1			T7	29		T28	23		T9	1
auto[0]	auto[0]	auto[1]	27234	1			T7	1		T28	2		T51	99
auto[0]	auto[0]	auto[2]	27340	1			T7	1		T28	1		T51	102
auto[0]	auto[0]	auto[3]	6647	1			T51	11		T87	37		T187	1
auto[0]	auto[1]	auto[0]	3155421	1			T7	3		T11	1034		T8	206
auto[0]	auto[1]	auto[1]	328364	1			T5	15		T7	1		T11	238
auto[0]	auto[1]	auto[2]	316528	1			T5	78		T7	1		T11	222
auto[0]	auto[1]	auto[3]	61339	1			T5	709		T11	59		T25	1
auto[0]	auto[2]	auto[0]	219978	1			T7	26		T9	2		T51	913
auto[0]	auto[2]	auto[1]	22358	1			T7	2		T51	81		T188	15
auto[0]	auto[2]	auto[2]	26636	1			T28	19		T51	89		T188	17
auto[0]	auto[2]	auto[3]	5519	1			T7	1		T51	6		T87	37
auto[0]	auto[3]	auto[0]	3107173	1			T5	9		T7	2		T11	1110
auto[0]	auto[3]	auto[1]	311866	1			T5	109		T7	1		T11	238
auto[0]	auto[3]	auto[2]	327256	1			T5	105		T10	1		T7	2
auto[0]	auto[3]	auto[3]	63343	1			T5	870		T11	68		T8	2
auto[1]	auto[0]	auto[0]	13380	1			T51	1		T188	1		T103	88
auto[1]	auto[0]	auto[1]	59488	1			T103	332		T109	2882		T110	953
auto[1]	auto[0]	auto[2]	59465	1			T103	339		T109	2849		T110	944
auto[1]	auto[0]	auto[3]	266974	1			T103	1485		T87	1		T88	1
auto[1]	auto[1]	auto[0]	3465241	1			T36	4		T40	5		T60	5
auto[1]	auto[1]	auto[1]	611305	1			T68	1		T103	922		T104	5378
auto[1]	auto[1]	auto[2]	586388	1			T5	1		T40	2		T68	1
auto[1]	auto[1]	auto[3]	1322283	1			T68	2		T103	4455		T104	546
auto[1]	auto[2]	auto[0]	9652	1			T51	2		T109	568		T189	530
auto[1]	auto[2]	auto[1]	42723	1			T109	2594		T189	2419		T185	1
auto[1]	auto[2]	auto[2]	49160	1			T103	302		T109	2314		T110	823
auto[1]	auto[2]	auto[3]	222766	1			T103	1336		T109	10773		T110	3630
auto[1]	auto[3]	auto[0]	3460333	1			T36	1		T40	2		T60	2
auto[1]	auto[3]	auto[1]	568766	1			T8	1		T103	301		T104	5321
auto[1]	auto[3]	auto[2]	601201	1			T28	1		T69	1		T86	1
auto[1]	auto[3]	auto[3]	1280024	1			T5	1		T103	4293		T104	519