Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	640330	1			T39	3		T46	599		T47	96
auto[1]	10262045	1			T4	3		T10	1602		T13	482
auto[2]	536968	1			T39	1		T46	399		T47	60
auto[3]	10164137	1			T10	1642		T13	475		T7	1

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14103195	1			T4	3		T10	3244		T13	957
auto[1]	2061492	1			T36	309		T37	429		T139	868
auto[2]	2078843	1			T36	263		T37	401		T39	3
auto[3]	3359950	1			T36	1377		T37	98		T39	1

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8245951

1

T4

3

T10

3240

T13

957

auto[1]

13357529

1

T10

4

T36

3

T37

2

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	289737	1			T46	20		T48	1252		T9	12
auto[0]	auto[0]	auto[1]	29695	1			T46	93		T47	2		T48	116
auto[0]	auto[0]	auto[2]	30155	1			T39	3		T46	82		T48	121
auto[0]	auto[0]	auto[3]	9121	1			T46	403		T47	91		T48	9
auto[0]	auto[1]	auto[0]	3106859	1			T4	3		T10	1600		T13	482
auto[0]	auto[1]	auto[1]	328745	1			T36	154		T37	226		T139	434
auto[0]	auto[1]	auto[2]	312213	1			T36	120		T37	198		T139	406
auto[0]	auto[1]	auto[3]	62596	1			T36	706		T37	42		T139	105
auto[0]	auto[2]	auto[0]	249277	1			T46	17		T48	1140		T9	14
auto[0]	auto[2]	auto[1]	25541	1			T46	73		T47	10		T48	106
auto[0]	auto[2]	auto[2]	29078	1			T46	56		T47	2		T48	98
auto[0]	auto[2]	auto[3]	7655	1			T39	1		T46	253		T47	48
auto[0]	auto[3]	auto[0]	3066289	1			T10	1640		T13	475		T7	1
auto[0]	auto[3]	auto[1]	308068	1			T36	155		T37	203		T139	433
auto[0]	auto[3]	auto[2]	328068	1			T36	143		T37	203		T139	434
auto[0]	auto[3]	auto[3]	62854	1			T36	668		T37	56		T139	98
auto[1]	auto[0]	auto[0]	9485	1			T102	188		T63	1		T138	95
auto[1]	auto[0]	auto[1]	41530	1			T140	1		T102	860		T138	441
auto[1]	auto[0]	auto[2]	41931	1			T102	796		T138	451		T141	407
auto[1]	auto[0]	auto[3]	188676	1			T46	1		T47	3		T140	2
auto[1]	auto[1]	auto[0]	3690287	1			T10	2		T37	1		T139	2
auto[1]	auto[1]	auto[1]	660449	1			T48	1		T142	2		T42	1
auto[1]	auto[1]	auto[2]	648715	1			T139	1		T97	6330		T143	2
auto[1]	auto[1]	auto[3]	1452181	1			T144	3		T97	25777		T98	34113
auto[1]	auto[2]	auto[0]	6611	1			T48	2		T102	130		T67	1
auto[1]	auto[2]	auto[1]	28959	1			T140	1		T102	534		T145	4890
auto[1]	auto[2]	auto[2]	34540	1			T102	1011		T138	391		T141	357
auto[1]	auto[2]	auto[3]	155307	1			T140	1		T102	4437		T138	1826
auto[1]	auto[3]	auto[0]	3684650	1			T10	2		T37	1		T139	1
auto[1]	auto[3]	auto[1]	638505	1			T139	1		T8	1		T42	1
auto[1]	auto[3]	auto[2]	654143	1			T142	1		T42	1		T144	2
auto[1]	auto[3]	auto[3]	1421560	1			T36	3		T142	1		T144	2