Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression/sram_ctrl_ret-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	328051196	169816	0	0
ctrl_regwen_rd_A	328051196	4003	0	0
exec_rd_A	328051196	3425	0	0
exec_regwen_rd_A	328051196	3587	0	0
readback_rd_A	328051196	1740	0	0
readback_regwen_rd_A	328051196	1466	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328051196	169816	0	0
T7	9135	0	0	0
T11	22508	1032	0	0
T13	3851	0	0	0
T14	865	0	0	0
T17	8800	0	0	0
T22	0	4197	0	0
T26	0	4747	0	0
T27	0	1303	0	0
T28	0	4527	0	0
T32	2502	0	0	0
T36	11651	0	0	0
T37	6317	0	0	0
T38	10664	0	0	0
T40	9038	0	0	0
T49	0	1146	0	0
T51	0	1155	0	0
T67	0	5372	0	0
T68	0	5474	0	0
T69	0	1333	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328051196	4003	0	0
T7	9135	0	0	0
T11	22508	148	0	0
T13	3851	0	0	0
T14	865	0	0	0
T17	8800	0	0	0
T26	0	245	0	0
T32	2502	0	0	0
T36	11651	0	0	0
T37	6317	0	0	0
T38	10664	0	0	0
T40	9038	0	0	0
T50	0	266	0	0
T106	0	67	0	0
T107	0	241	0	0
T108	0	297	0	0
T109	0	212	0	0
T110	0	151	0	0
T111	0	64	0	0
T112	0	208	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328051196	3425	0	0
T7	9135	0	0	0
T11	22508	112	0	0
T13	3851	0	0	0
T14	865	0	0	0
T17	8800	0	0	0
T26	0	145	0	0
T32	2502	0	0	0
T36	11651	0	0	0
T37	6317	0	0	0
T38	10664	0	0	0
T40	9038	0	0	0
T50	0	170	0	0
T106	0	67	0	0
T107	0	112	0	0
T108	0	307	0	0
T109	0	186	0	0
T110	0	115	0	0
T111	0	42	0	0
T112	0	100	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328051196	3587	0	0
T7	9135	0	0	0
T11	22508	136	0	0
T13	3851	0	0	0
T14	865	0	0	0
T17	8800	0	0	0
T26	0	186	0	0
T32	2502	0	0	0
T36	11651	0	0	0
T37	6317	0	0	0
T38	10664	0	0	0
T40	9038	0	0	0
T50	0	171	0	0
T106	0	78	0	0
T107	0	172	0	0
T108	0	260	0	0
T109	0	207	0	0
T110	0	165	0	0
T111	0	30	0	0
T112	0	78	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328051196	1740	0	0
T7	9135	0	0	0
T11	22508	114	0	0
T13	3851	0	0	0
T14	865	0	0	0
T17	8800	0	0	0
T26	0	156	0	0
T32	2502	0	0	0
T36	11651	0	0	0
T37	6317	0	0	0
T38	10664	0	0	0
T40	9038	0	0	0
T50	0	233	0	0
T106	0	73	0	0
T107	0	145	0	0
T108	0	316	0	0
T109	0	237	0	0
T110	0	177	0	0
T111	0	51	0	0
T112	0	94	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328051196	1466	0	0
T7	9135	0	0	0
T11	22508	88	0	0
T13	3851	0	0	0
T14	865	0	0	0
T17	8800	0	0	0
T26	0	113	0	0
T32	2502	0	0	0
T36	11651	0	0	0
T37	6317	0	0	0
T38	10664	0	0	0
T40	9038	0	0	0
T50	0	197	0	0
T106	0	75	0	0
T107	0	121	0	0
T108	0	248	0	0
T109	0	201	0	0
T110	0	141	0	0
T111	0	44	0	0
T112	0	109	0	0