Line Coverage for Module :
tlul_sram_byte
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 145 | 145 | 100.00 |
| ALWAYS | 105 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 142 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| ALWAYS | 239 | 95 | 95 | 100.00 |
| CONT_ASSIGN | 506 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 517 | 1 | 1 | 100.00 |
| ALWAYS | 542 | 2 | 2 | 100.00 |
| ALWAYS | 553 | 0 | 0 | |
| ALWAYS | 553 | 2 | 2 | 100.00 |
| ALWAYS | 572 | 2 | 2 | 100.00 |
| ALWAYS | 579 | 22 | 22 | 100.00 |
| CONT_ASSIGN | 633 | 1 | 1 | 100.00 |
| ALWAYS | 658 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 676 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 699 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 716 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 717 | 1 | 1 | 100.00 |
104 always_ff @(posedge clk_i or negedge rst_ni) begin
105 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
106 1/1 state_q <= StPassThru;
Tests: T1 T2 T3
107 end else begin
108 1/1 state_q <= state_d;
Tests: T1 T2 T3
109 end
110 end
111
112 // transaction qualifying signals
113 logic a_ack; // upstream a channel acknowledgement
114 logic d_ack; // upstream d channel acknowledgement
115 logic sram_a_ack; // downstream a channel acknowledgement
116 logic sram_d_ack; // downstream d channel acknowledgement
117 logic wr_txn;
118 logic byte_wr_txn;
119 logic byte_req_ack;
120 logic hold_tx_data;
121
122 localparam int unsigned PendingTxnCntW = prim_util_pkg::vbits(Outstanding+1);
123 logic [PendingTxnCntW-1:0] pending_txn_cnt;
124
125 // prim fifo for capturing info
126 typedef struct packed {
127 logic [2:0] a_param;
128 logic [top_pkg::TL_SZW-1:0] a_size;
129 logic [top_pkg::TL_AIW-1:0] a_source;
130 logic [top_pkg::TL_AW-1:0] a_address;
131 logic [top_pkg::TL_DBW-1:0] a_mask;
132 logic [top_pkg::TL_DW-1:0] a_data;
133 tl_a_user_t a_user;
134 } tl_txn_data_t;
135
136 tl_txn_data_t held_data;
137
138 1/1 assign a_ack = tl_i.a_valid & tl_o.a_ready;
Tests: T1 T2 T3
139 1/1 assign d_ack = tl_o.d_valid & tl_i.d_ready;
Tests: T1 T2 T3
140 1/1 assign sram_a_ack = tl_sram_o.a_valid & tl_sram_i.a_ready;
Tests: T1 T2 T3
141 1/1 assign sram_d_ack = tl_sram_i.d_valid & tl_sram_o.d_ready;
Tests: T1 T2 T3
142 1/1 assign wr_txn = (tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData);
Tests: T1 T2 T3
143
144 1/1 assign byte_req_ack = byte_wr_txn & a_ack & ~error_i;
Tests: T1 T2 T3
145 1/1 assign byte_wr_txn = tl_i.a_valid & ~&tl_i.a_mask & wr_txn;
Tests: T1 T2 T3
146
147 logic rdback_chk_ok;
148 mubi4_t rdback_check_q, rdback_check_d;
149 mubi4_t rdback_en_q, rdback_en_d;
150 logic [31:0] rdback_data_exp_q, rdback_data_exp_d;
151 logic [DataIntgWidth-1:0] rdback_data_exp_intg_q, rdback_data_exp_intg_d;
152
153 if (EnableReadback) begin : gen_readback_logic
154 logic rdback_chk_ok_unbuf;
155
156 1/1 assign rdback_chk_ok_unbuf = (rdback_data_exp_q == tl_sram_i.d_data);
Tests: T1 T2 T3
157
158 prim_sec_anchor_buf #(
159 .Width(1)
160 ) u_rdback_chk_ok_buf (
161 .in_i (rdback_chk_ok_unbuf),
162 .out_o(rdback_chk_ok)
163 );
164
165 prim_flop #(
166 .Width(MuBi4Width),
167 .ResetValue(MuBi4Width'(MuBi4False))
168 ) u_rdback_check_flop (
169 .clk_i,
170 .rst_ni,
171
172 .d_i(MuBi4Width'(rdback_check_d)),
173 .q_o({rdback_check_q})
174 );
175
176 prim_flop #(
177 .Width(MuBi4Width),
178 .ResetValue(MuBi4Width'(MuBi4False))
179 ) u_rdback_en_flop (
180 .clk_i,
181 .rst_ni,
182
183 .d_i(MuBi4Width'(rdback_en_d)),
184 .q_o({rdback_en_q})
185 );
186
187 prim_flop #(
188 .Width(32),
189 .ResetValue(0)
190 ) u_rdback_data_exp (
191 .clk_i,
192 .rst_ni,
193
194 .d_i(rdback_data_exp_d),
195 .q_o(rdback_data_exp_q)
196 );
197
198 prim_flop #(
199 .Width(DataIntgWidth),
200 .ResetValue(0)
201 ) u_rdback_data_exp_intg (
202 .clk_i,
203 .rst_ni,
204
205 .d_i(rdback_data_exp_intg_d),
206 .q_o(rdback_data_exp_intg_q)
207 );
208
209 // If the readback feature is enabled and we are currently in the readback phase,
210 // no address collision should happen inside prim_ram_1p_scr. If this would be the
211 // case, we would read from the holding register inside prim_ram_1p_scr instead of
212 // actually performing the readback from the memory.
213 `ASSERT(WRCollisionDuringReadBack_A, (rdback_phase | rdback_phase_wrreadback) &
214 mubi4_test_true_loose(rdback_en_q) |-> !wr_collision_i)
215
216
217 // If the readback feature is enabled, we assume that the write phase takes one extra cycle
218 // due to the underyling scrambling mechanism. If this additional cycle is not needed anymore
219 // in the future (e.g. due to the removale of the scrambling mechanism), the readback does not
220 // need to be delayed by once cylce in the FSM below.
221 `ASSERT(NoPendingWriteAfterWrite_A, wr_phase & mubi4_test_true_loose(rdback_en_q)
222 |=> write_pending_i)
223
224
225 end else begin: gen_no_readback_logic
226 assign rdback_chk_ok = 1'b0;
227 assign rdback_check_q = MuBi4False;
228 assign rdback_en_q = MuBi4False;
229 assign rdback_data_exp_q = 1'b0;
230 assign rdback_data_exp_intg_q = 1'b0;
231
232 logic unused_rdback;
233
234 assign unused_rdback = ^{rdback_check_d, rdback_data_exp_d, rdback_data_exp_intg_d};
235 end
236
237 // state machine handling
238 always_comb begin
239 1/1 rd_wait = 1'b0;
Tests: T1 T2 T3
240 1/1 wait_phase = 1'b0;
Tests: T1 T2 T3
241 1/1 stall_host = 1'b0;
Tests: T1 T2 T3
242 1/1 wr_phase = 1'b0;
Tests: T1 T2 T3
243 1/1 rd_phase = 1'b0;
Tests: T1 T2 T3
244 1/1 rdback_phase = 1'b0;
Tests: T1 T2 T3
245 1/1 rdback_phase_wrreadback = 1'b0;
Tests: T1 T2 T3
246 1/1 rdback_wait = 1'b0;
Tests: T1 T2 T3
247 1/1 state_d = state_q;
Tests: T1 T2 T3
248 1/1 hold_tx_data = 1'b0;
Tests: T1 T2 T3
249 1/1 alert_o = 1'b0;
Tests: T1 T2 T3
250 1/1 rdback_check_d = rdback_check_q;
Tests: T1 T2 T3
251 1/1 rdback_en_d = rdback_en_q;
Tests: T1 T2 T3
252 1/1 rdback_data_exp_d = rdback_data_exp_q;
Tests: T1 T2 T3
253 1/1 rdback_data_exp_intg_d = rdback_data_exp_intg_q;
Tests: T1 T2 T3
254
255 1/1 unique case (state_q)
Tests: T1 T2 T3
256 StPassThru: begin
257 1/1 if (mubi4_test_true_loose(rdback_en_q) && mubi4_test_true_loose(rdback_check_q)) begin
Tests: T1 T2 T3
258 // When we're expecting a readback check that means we'll see a data response from the
259 // SRAM this cycle which we need to check against the readback registers. During this
260 // cycle the data response out (via tl_o) will be squashed to invalid but we can accept
261 // a new transaction (via tl_i).
262 1/1 rdback_wait = 1'b1;
Tests: T2 T14 T26
263 1/1 rdback_check_d = MuBi4False;
Tests: T2 T14 T26
264
265 // Perform the readback check.
266 1/1 if (!rdback_chk_ok) begin
Tests: T2 T14 T26
267 1/1 alert_o = 1'b1;
Tests: T2 T14 T15
268 end
MISSING_ELSE
269 end
MISSING_ELSE
270
271 1/1 if (byte_wr_txn) begin
Tests: T1 T2 T3
272 1/1 rd_phase = 1'b1;
Tests: T5 T10 T7
273 1/1 if (byte_req_ack) begin
Tests: T5 T10 T7
274 1/1 state_d = StWaitRd;
Tests: T5 T10 T7
275 end
MISSING_ELSE
276 1/1 end else if (a_ack && mubi4_test_true_loose(rdback_en_q) && !error_i) begin
Tests: T1 T2 T3
277 // For reads and full word writes we'll first do the transaction and then do a readback
278 // check. Setting `hold_tx_data` here will preserve the transaction information in
279 // u_sync_fifo for doing the readback transaction.
280 1/1 hold_tx_data = 1'b1;
Tests: T2 T14 T26
281 1/1 state_d = wr_txn ? StWrReadBackInit : StRdReadBack;
Tests: T2 T14 T26
282 end
MISSING_ELSE
283
284 1/1 if (!tl_sram_o.a_valid && !tl_o.d_valid &&
Tests: T1 T2 T3
285 mubi4_test_false_strict(rdback_check_q)) begin
286 // Store readback enable into register when bus is idle and no readback is processed.
287 1/1 rdback_en_d = readback_en_i;
Tests: T1 T2 T3
288 end
MISSING_ELSE
289 end
290
291 // Due to the way things are serialized, there is no way for the logic to tell which read
292 // belongs to the partial read unless it flushes all prior transactions. Hence, we wait
293 // here until exactly one outstanding transaction remains (that one is the partial read).
294 StWaitRd: begin
295 1/1 rd_phase = 1'b1;
Tests: T5 T10 T7
296 1/1 stall_host = 1'b1;
Tests: T5 T10 T7
297 1/1 if (pending_txn_cnt == PendingTxnCntW'(1)) begin
Tests: T5 T10 T7
298 1/1 rd_wait = 1'b1;
Tests: T5 T10 T7
299 1/1 if (sram_d_ack) begin
Tests: T5 T10 T7
300 1/1 state_d = StWriteCmd;
Tests: T5 T10 T7
301 end
==> MISSING_ELSE
302 end
MISSING_ELSE
303 end
304
305 StWriteCmd: begin
306 1/1 stall_host = 1'b1;
Tests: T5 T10 T7
307 1/1 wr_phase = 1'b1;
Tests: T5 T10 T7
308
309 1/1 if (sram_a_ack) begin
Tests: T5 T10 T7
310 1/1 state_d = mubi4_test_true_loose(rdback_en_q) ? StByteWrReadBackInit : StPassThru;
Tests: T5 T10 T7
311 1/1 rdback_check_d = mubi4_test_true_loose(rdback_en_q) ? MuBi4True : MuBi4False;
Tests: T5 T10 T7
312 1/1 rdback_data_exp_d = tl_sram_o.a_data;
Tests: T5 T10 T7
313 1/1 rdback_data_exp_intg_d = tl_sram_o.a_user.data_intg;
Tests: T5 T10 T7
314 end
==> MISSING_ELSE
315 end
316
317 StWrReadBackInit: begin
318 // Perform readback after full write. To avoid that we read the holding register
319 // in the readback, wait until the write was processed by the memory module.
320 1/1 if (EnableReadback == 0) begin : gen_inv_state_StWrReadBackInit
Tests: T2 T14 T26
321 // If readback is disabled, we shouldn't be in this state.
322 unreachable alert_o = 1'b1;
323 end
MISSING_ELSE
324
325 // Stall the host to perform the readback in the next cycle.
326 1/1 stall_host = 1'b1;
Tests: T2 T14 T26
327
328 // Need to ensure there's no other transactions in flight before we do the readback (the
329 // initial write we're doing the readback for should be the only one active).
330 1/1 if (pending_txn_cnt == PendingTxnCntW'(1)) begin
Tests: T2 T14 T26
331 1/1 wait_phase = 1'b1;
Tests: T2 T14 T26
332 // Data we're checking against the readback is captured from the write transaction that
333 // was sent.
334 1/1 rdback_check_d = mubi4_test_true_loose(rdback_en_q) ? MuBi4True : MuBi4False;
Tests: T2 T14 T26
335 1/1 rdback_data_exp_d = held_data.a_data;
Tests: T2 T14 T26
336 1/1 rdback_data_exp_intg_d = held_data.a_user.data_intg;
Tests: T2 T14 T26
337 1/1 if (d_ack) begin
Tests: T2 T14 T26
338 // Got an immediate TL-UL write response. Wait for one cycle until the holding
339 // register is flushed and then perform the readback.
340 1/1 state_d = StWrReadBack;
Tests: T2 T14 T26
341 end else begin
342 // No response yet to the initial write.
343 1/1 state_d = StWrReadBackDWait;
Tests: T2 T14 T26
344 end
345 end
MISSING_ELSE
346 end
347
348 StWrReadBack: begin
349 // Perform readback and check response in StPassThru.
350 1/1 if (EnableReadback == 0) begin : gen_inv_state_StWrReadBack
Tests: T2 T14 T26
351 // If readback is disabled, we shouldn't be in this state.
352 unreachable alert_o = 1'b1;
353 end
MISSING_ELSE
354
355 1/1 stall_host = 1'b1;
Tests: T2 T14 T26
356
357 1/1 rdback_phase = 1'b1;
Tests: T2 T14 T26
358
359 1/1 state_d = StPassThru;
Tests: T2 T14 T26
360 end
361
362 StWrReadBackDWait: begin
363 // We have not received the d_valid response of the initial write. Wait
364 // for the valid signal.
365 1/1 if (EnableReadback == 0) begin : gen_inv_state_StWrReadBackDWait
Tests: T47 T48 T46
366 // If readback is disabled, we shouldn't be in this state.
367 unreachable alert_o = 1'b1;
368 end
MISSING_ELSE
369
370 // Wait until we get write response.
371 1/1 wait_phase = 1'b1;
Tests: T47 T48 T46
372
373 1/1 stall_host = 1'b1;
Tests: T47 T48 T46
374
375 1/1 if (d_ack) begin
Tests: T47 T48 T46
376 // Got the TL-UL write response. Wait for one cycle until the holding
377 // register is flushed and then perform the readback.
378 1/1 state_d = StWrReadBack;
Tests: T47 T48 T46
379 end
MISSING_ELSE
380 end
381
382 StByteWrReadBackInit: begin
383 // Perform readback after partial write. To avoid that we read the holding register
384 // in the readback, do the actual readback check in the next FSM state.
385 1/1 if (EnableReadback == 0) begin : gen_inv_state_StByteWrReadBackInit
Tests: T26 T29 T49
386 // If readback is disabled, we shouldn't be in this state.
387 unreachable alert_o = 1'b1;
388 end
MISSING_ELSE
389
390 // Sends out a read to a readback check on a partial write. The host is stalled whilst
391 // this is happening.
392 1/1 stall_host = 1'b1;
Tests: T26 T29 T49
393
394 // Wait until there is a single ongoing transaction.
395 1/1 if (pending_txn_cnt == PendingTxnCntW'(1)) begin
Tests: T26 T29 T49
396 // Wait for one cycle with sending readback request to SRAM to avoid reading from
397 // holding register.
398 1/1 wait_phase = 1'b1;
Tests: T26 T29 T49
399
400 1/1 if (d_ack) begin
Tests: T26 T29 T49
401 // Got an immediate TL-UL write response. Wait for one cycle until the holding
402 // register is flushed and then perform the readback.
403 1/1 state_d = StByteWrReadBack;
Tests: T26 T29 T49
404 end else begin
405 // No response received for initial write. We already can send the
406 // request for the readback in the next cycle but we need to wait
407 // for the response for the initial write before doing the readback
408 // check.
409 1/1 state_d = StByteWrReadBackDWait;
Tests: T26 T49 T50
410 end
411 end
==> MISSING_ELSE
412 end
413
414 StByteWrReadBack: begin
415 // Wait until the memory module has completed the partial write.
416 // Perform readback and check response in StPassThru.
417 1/1 if (EnableReadback == 0) begin : gen_inv_state_StByteWrReadBack
Tests: T26 T29 T49
418 // If readback is disabled, we shouldn't be in this state.
419 unreachable alert_o = 1'b1;
420 end
MISSING_ELSE
421
422 1/1 stall_host = 1'b1;
Tests: T26 T29 T49
423
424 1/1 rdback_phase_wrreadback = 1'b1;
Tests: T26 T29 T49
425
426 1/1 state_d = StPassThru;
Tests: T26 T29 T49
427 end
428
429 StByteWrReadBackDWait: begin
430 1/1 if (EnableReadback == 0) begin : gen_inv_state_StByteWrReadBackDWait
Tests: T26 T50 T46
431 // If readback is disabled, we shouldn't be in this state.
432 unreachable alert_o = 1'b1;
433 end
MISSING_ELSE
434
435 1/1 stall_host = 1'b1;
Tests: T26 T50 T46
436
437 // Wait for one cycle with sending readback request to SRAM.
438 1/1 wait_phase = 1'b1;
Tests: T26 T50 T46
439
440 1/1 if (d_ack) begin
Tests: T26 T50 T46
441 // Got the TL-UL write response. Wait for one cycle until the holding
442 // register is flushed and then perform the readback.
443 1/1 state_d = StByteWrReadBack;
Tests: T26 T50 T46
444 end
MISSING_ELSE
445 end
446
447 StRdReadBack: begin
448 1/1 if (EnableReadback == 0) begin : gen_inv_state_StRdReadBack
Tests: T26 T47 T15
449 // If readback is disabled, we shouldn't be in this state.
450 unreachable alert_o = 1'b1;
451 end
MISSING_ELSE
452
453 // Sends out a read to a readback check on a read. The host is stalled whilst
454 // this is happening.
455 1/1 stall_host = 1'b1;
Tests: T26 T47 T15
456
457 // Need to ensure there's no other transactions in flight before we do the readback (the
458 // read we're doing the readback for should be the only one active).
459 1/1 if (pending_txn_cnt == PendingTxnCntW'(1)) begin
Tests: T26 T47 T15
460 1/1 rdback_phase = 1'b1;
Tests: T26 T47 T15
461
462 1/1 if (d_ack) begin
Tests: T26 T47 T15
463 1/1 state_d = StPassThru;
Tests: T26 T47 T15
464 // Data for the readback check comes from the first read.
465 1/1 rdback_check_d = mubi4_test_true_loose(rdback_en_q) ? MuBi4True : MuBi4False;
Tests: T26 T47 T15
466 1/1 rdback_data_exp_d = tl_o.d_data;
Tests: T26 T47 T15
467 1/1 rdback_data_exp_intg_d = tl_o.d_user.data_intg;
Tests: T26 T47 T15
468 end else begin
469 // No response yet to the initial read, so go wait for it.
470 1/1 state_d = StRdReadBackDWait;
Tests: T26 T47 T15
471 end
472 end
MISSING_ELSE
473 end
474
475 StRdReadBackDWait : begin
476 1/1 if (EnableReadback == 0) begin : gen_inv_state_StRdReadBackDWait
Tests: T47 T15 T48
477 // If readback is disabled, we shouldn't be in this state.
478 unreachable alert_o = 1'b1;
479 end
MISSING_ELSE
480
481 1/1 stall_host = 1'b1;
Tests: T47 T15 T48
482
483 1/1 if (d_ack) begin
Tests: T47 T15 T48
484 // Response received for first read. Now need to await data for the readback check
485 // which is done in the `StPassThru` state.
486 1/1 state_d = StPassThru;
Tests: T47 T15 T48
487 // Data for the readback check comes from the first read.
488 1/1 rdback_check_d = mubi4_test_true_loose(rdback_en_q) ? MuBi4True : MuBi4False;
Tests: T47 T15 T48
489 1/1 rdback_data_exp_d = tl_o.d_data;
Tests: T47 T15 T48
490 1/1 rdback_data_exp_intg_d = tl_o.d_user.data_intg;
Tests: T47 T15 T48
491 end
MISSING_ELSE
492 end
493
494 default: begin
495 alert_o = 1'b1;
496 end
497 endcase // unique case (state_q)
498
499 end
500
501 tl_txn_data_t txn_data;
502 logic fifo_rdy;
503 logic txn_data_wr;
504 localparam int TxnDataWidth = $bits(tl_txn_data_t);
505
506 1/1 assign txn_data = '{
Tests: T1 T2 T3
507 a_param: tl_i.a_param,
508 a_size: tl_i.a_size,
509 a_source: tl_i.a_source,
510 a_address: tl_i.a_address,
511 a_mask: tl_i.a_mask,
512 a_data: tl_i.a_data,
513 a_user: tl_i.a_user
514 };
515
516
517 1/1 assign txn_data_wr = hold_tx_data | byte_req_ack;
Tests: T1 T2 T3
518
519 prim_fifo_sync #(
520 .Width(TxnDataWidth),
521 .Pass(1'b0),
522 .Depth(1),
523 .OutputZeroIfEmpty(1'b0)
524 ) u_sync_fifo (
525 .clk_i,
526 .rst_ni,
527 .clr_i(1'b0),
528 .wvalid_i(txn_data_wr),
529 .wready_o(fifo_rdy),
530 .wdata_i(txn_data),
531 .rvalid_o(),
532 .rready_i(sram_a_ack),
533 .rdata_o(held_data),
534 .full_o(),
535 .depth_o(),
536 .err_o()
537 );
538
539 // captured read data
540 logic [top_pkg::TL_DW-1:0] rsp_data;
541 always_ff @(posedge clk_i) begin
542 1/1 if (sram_d_ack && rd_wait) begin
Tests: T1 T2 T3
543 1/1 rsp_data <= tl_sram_i.d_data;
Tests: T5 T10 T7
544 end
MISSING_ELSE
545 end
546
547 // while we could simply not assert a_ready to ensure the host keeps
548 // the request lines stable, there is no guarantee the hosts (if there are multiple)
549 // do not re-arbitrate on every cycle if its transactions are not accepted.
550 // As a result, it is better to capture the transaction attributes.
551 logic [top_pkg::TL_DW-1:0] combined_data, unused_data;
552 always_comb begin
553 1/1 for (int i = 0; i < top_pkg::TL_DBW; i++) begin
Tests: T2 T5 T10
554 1/1 combined_data[i*8 +: 8] = held_data.a_mask[i] ?
Tests: T2 T5 T10
555 held_data.a_data[i*8 +: 8] :
556 rsp_data[i*8 +: 8];
557 end
558 end
559
560 // Compute updated integrity bits for the data.
561 // Note that the CMD integrity does not have to be correct, since it is not consumed nor
562 // checked further downstream.
563 logic [tlul_pkg::DataIntgWidth-1:0] data_intg;
564
565 tlul_data_integ_enc u_tlul_data_integ_enc (
566 .data_i(combined_data),
567 .data_intg_o({data_intg, unused_data})
568 );
569
570 tl_a_user_t combined_user;
571 always_comb begin
572 1/1 combined_user = held_data.a_user;
Tests: T2 T5 T10
573 1/1 combined_user.data_intg = data_intg;
Tests: T2 T5 T10
574 end
575
576 localparam int unsigned AccessSize = $clog2(top_pkg::TL_DBW);
577 always_comb begin
578 // Pass-through by default
579 1/1 tl_sram_o = tl_i;
Tests: T1 T2 T3
580 // If we're waiting for an internal read for RMW, or a readback read, we force this to 1.
581 1/1 tl_sram_o.d_ready = tl_i.d_ready | rd_wait | rdback_wait;
Tests: T1 T2 T3
582
583 // We take over the TL-UL bus if there is a pending read or write for the RMW transaction.
584 // TL-UL signals are selectively muxed below to reduce complexity and remove long timing
585 // paths through the error_i signal. In particular, we avoid creating paths from error_i
586 // to the address and data output since these may feed into RAM scrambling logic further
587 // downstream.
588
589 // Write transactions for RMW or reads when in readback mode.
590 1/1 if (wr_phase | rdback_phase | rdback_phase_wrreadback) begin
Tests: T1 T2 T3
591 1/1 tl_sram_o.a_valid = 1'b1;
Tests: T2 T5 T10
592 // During a read-modify write, always access the entire word.
593 1/1 tl_sram_o.a_opcode = wr_phase ? PutFullData : Get;
Tests: T2 T5 T10
594 // In either read-modify write or SRAM readback mode, use the mask, size and address
595 // of the original request.
596 1/1 tl_sram_o.a_size =
Tests: T2 T5 T10
597 (wr_phase | rdback_phase_wrreadback) ? top_pkg::TL_SZW'(AccessSize) : held_data.a_size;
598 1/1 tl_sram_o.a_mask =
Tests: T2 T5 T10
599 (wr_phase | rdback_phase_wrreadback) ? '{default: '1} : held_data.a_mask;
600 // override with held / combined data.
601 // need to use word aligned addresses here.
602 1/1 tl_sram_o.a_address = held_data.a_address;
Tests: T2 T5 T10
603 1/1 tl_sram_o.a_address[AccessSize-1:0] =
Tests: T2 T5 T10
604 (wr_phase | rdback_phase_wrreadback) ? '0 : held_data.a_address[AccessSize-1:0];
605 1/1 tl_sram_o.a_source = held_data.a_source;
Tests: T2 T5 T10
606 1/1 tl_sram_o.a_param = held_data.a_param;
Tests: T2 T5 T10
607 1/1 tl_sram_o.a_data = wr_phase ? combined_data : '0;
Tests: T2 T5 T10
608 1/1 tl_sram_o.a_user = wr_phase ? combined_user : '0;
Tests: T2 T5 T10
609 // Read transactions for RMW.
610 1/1 end else if (rd_phase) begin
Tests: T1 T2 T3
611 // need to use word aligned addresses here.
612 1/1 tl_sram_o.a_address[AccessSize-1:0] = '0;
Tests: T5 T10 T7
613 // Only override the control signals if there is no error at the input.
614 1/1 if (!error_i || stall_host) begin
Tests: T5 T10 T7
615 // Since we are performing a read-modify-write operation,
616 // we always access the entire word.
617 1/1 tl_sram_o.a_size = top_pkg::TL_SZW'(AccessSize);
Tests: T5 T10 T7
618 1/1 tl_sram_o.a_mask = '{default: '1};
Tests: T5 T10 T7
619 // use incoming valid as long as we are not stalling the host
620 1/1 tl_sram_o.a_valid = tl_i.a_valid & ~stall_host;
Tests: T5 T10 T7
621 1/1 tl_sram_o.a_opcode = Get;
Tests: T5 T10 T7
622 end
MISSING_ELSE
623 1/1 end else if (wait_phase) begin
Tests: T1 T2 T3
624 // Delay the readback request to avoid that we are reading the holding
625 // register.
626 1/1 tl_sram_o.a_valid = 1'b0;
Tests: T2 T14 T26
627 end
MISSING_ELSE
628 end
629
630 // This assert is necessary for the casting of AccessSize.
631 `ASSERT(TlulSramByteTlSize_A, top_pkg::TL_SZW >= $clog2(AccessSize + 1))
632
633 1/1 assign error_o = error_i & ~stall_host;
Tests: T1 T2 T3
634
635 logic size_fifo_rdy;
636 logic [top_pkg::TL_SZW-1:0] a_size;
637 prim_fifo_sync #(
638 .Width(top_pkg::TL_SZW),
639 .Pass(1'b0),
640 .Depth(Outstanding),
641 .OutputZeroIfEmpty(1'b1)
642 ) u_sync_fifo_a_size (
643 .clk_i,
644 .rst_ni,
645 .clr_i(1'b0),
646 .wvalid_i(a_ack),
647 .wready_o(size_fifo_rdy),
648 .wdata_i(tl_i.a_size),
649 .rvalid_o(),
650 .rready_i(d_ack),
651 .rdata_o(a_size),
652 .full_o(),
653 .depth_o(pending_txn_cnt),
654 .err_o()
655 );
656
657 always_comb begin
658 1/1 tl_o = tl_sram_i;
Tests: T1 T2 T3
659
660 // pass a_ready through directly if we are not stalling
661 1/1 tl_o.a_ready = tl_sram_i.a_ready & ~stall_host & fifo_rdy & size_fifo_rdy;
Tests: T1 T2 T3
662
663 // when internal logic has taken over, do not show response to host during
664 // read phase. During write phase, allow the host to see the completion.
665 1/1 tl_o.d_valid = tl_sram_i.d_valid & ~rd_wait & ~rdback_wait;
Tests: T1 T2 T3
666
667 // the size returned by tl_sram_i does not always correspond to the actual
668 // transaction size in cases where a read modify write operation is
669 // performed. Hence, we always return the registered size here.
670 1/1 tl_o.d_size = a_size;
Tests: T1 T2 T3
671 end // always_comb
672
673 // unused info from tl_sram_i
674 // see explanation in above block
675 logic unused_tl;
676 1/1 assign unused_tl = |tl_sram_i.d_size;
Tests: T1 T2 T3
677
678 // when byte access detected, go to wait read
679 `ASSERT(ByteAccessStateChange_A, a_ack & wr_txn & ~&tl_i.a_mask & ~error_i |=>
680 state_q inside {StWaitRd})
681 // when in wait for read, a successful response should move to write phase
682 `ASSERT(ReadCompleteStateChange_A,
683 (state_q == StWaitRd) && (pending_txn_cnt == 1) && sram_d_ack |=> state_q == StWriteCmd)
684 // The readback logic assumes that any request on the readback channel will be instantly granted
685 // (i.e. after the initial SRAM read or write request from the external requester has been
686 // granted). This helps simplify the logic. It is guaranteed when connected to an SRAM as it
687 // produces no back pressure. When connected to a scrambled SRAM the key going invalid will
688 // cause a_ready to drop. The `compound_txn_in_progress_o` output is provided for this scenario.
689 // When asserted SRAM should not drop `a_ready` even if there is an invalid scrambling key.
690 `ASSERT(ReadbackAccessAlwaysGranted_A, (rdback_phase | rdback_phase_wrreadback) && !error_i
691 |-> tl_sram_i.a_ready)
692
693 // The readback logic assumes the result of a read transaction issues for the readback will get
694 // an immediate response. This can be guaranteed when connected to a SRAM, see above comment.
695 `ASSERT(ReadbackDataImmediatelyAvailable_A, (state_q == StPassThru) &&
696 mubi4_test_true_loose(rdback_en_q) && mubi4_test_true_loose(rdback_check_q) &&
697 !error_i|-> tl_sram_i.d_valid)
698
699 1/1 assign compound_txn_in_progress_o = wr_phase | rdback_phase | rdback_phase_wrreadback;
Tests: T1 T2 T3
700 end else begin : gen_no_integ_handling
701 // In this case we pass everything just through.
702 assign tl_sram_o = tl_i;
703 assign tl_o = tl_sram_i;
704 assign error_o = error_i;
705 assign alert_o = 1'b0;
706 assign compound_txn_in_progress_o = 1'b0;
707
708 // Signal only used in readback mode.
709 mubi4_t unused_readback_en;
710 assign unused_readback_en = readback_en_i;
711
712 end
713
714 // Signals only used for SVA.
715 logic unused_write_pending, unused_wr_collision;
716 1/1 assign unused_write_pending = write_pending_i;
Tests: T1 T2 T3
717 1/1 assign unused_wr_collision = wr_collision_i;
Tests: T1 T2 T3
Cond Coverage for Module :
tlul_sram_byte
| Total | Covered | Percent |
|---|
| Conditions | 98 | 93 | 94.90 |
| Logical | 98 | 93 | 94.90 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 138
EXPRESSION (tl_i.a_valid & tl_o.a_ready)
------1----- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T5,T10 |
| 1 | 1 | Covered | T2,T4,T5 |
LINE 139
EXPRESSION (tl_o.d_valid & tl_i.d_ready)
------1----- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T5,T10 |
| 1 | 1 | Covered | T2,T4,T5 |
LINE 140
EXPRESSION (tl_sram_o.a_valid & tl_sram_i.a_ready)
--------1-------- --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T7,T28,T9 |
| 1 | 1 | Covered | T2,T4,T5 |
LINE 141
EXPRESSION (tl_sram_i.d_valid & tl_sram_o.d_ready)
--------1-------- --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T5,T10 |
| 1 | 1 | Covered | T2,T4,T5 |
LINE 142
EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData))
---------------1-------------- ----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T2,T3,T4 |
| 0 | 1 | Covered | T2,T4,T5 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 142
SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
---------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 142
SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T4,T5 |
LINE 144
EXPRESSION (gen_integ_handling.byte_wr_txn & gen_integ_handling.a_ack & ((~error_i)))
---------------1-------------- ------------2----------- ------3-----
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T2,T4,T5 |
| 1 | 0 | 1 | Covered | T5,T10,T7 |
| 1 | 1 | 0 | Covered | T28,T29,T19 |
| 1 | 1 | 1 | Covered | T5,T10,T7 |
LINE 145
EXPRESSION (tl_i.a_valid & ((~&tl_i.a_mask)) & gen_integ_handling.wr_txn)
------1----- --------2-------- ------------3------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T4,T5 |
| 1 | 1 | 0 | Covered | T5,T10,T7 |
| 1 | 1 | 1 | Covered | T5,T10,T7 |
LINE 156
EXPRESSION (gen_integ_handling.rdback_data_exp_q == tl_sram_i.d_data)
-----------------------------1----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T5,T10 |
LINE 281
EXPRESSION (gen_integ_handling.wr_txn ? StWrReadBackInit : StRdReadBack)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T26,T47,T15 |
| 1 | Covered | T2,T14,T26 |
LINE 297
EXPRESSION (gen_integ_handling.pending_txn_cnt == 2'(1))
----------------------1----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T7,T28,T51 |
| 1 | Covered | T5,T10,T7 |
LINE 330
EXPRESSION (gen_integ_handling.pending_txn_cnt == 2'(1))
----------------------1----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T46,T52,T53 |
| 1 | Covered | T2,T14,T26 |
LINE 395
EXPRESSION (gen_integ_handling.pending_txn_cnt == 2'(1))
----------------------1----------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Covered | T26,T29,T49 |
LINE 459
EXPRESSION (gen_integ_handling.pending_txn_cnt == 2'(1))
----------------------1----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T52,T53 |
| 1 | Covered | T26,T47,T15 |
LINE 517
EXPRESSION (gen_integ_handling.hold_tx_data | gen_integ_handling.byte_req_ack)
---------------1--------------- ---------------2---------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T5,T10,T7 |
| 1 | 0 | Covered | T2,T14,T26 |
LINE 542
EXPRESSION (gen_integ_handling.sram_d_ack && gen_integ_handling.rd_wait)
--------------1-------------- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T2,T4,T5 |
| 1 | 1 | Covered | T5,T10,T7 |
LINE 554
EXPRESSION (gen_integ_handling.held_data.a_mask[i] ? gen_integ_handling.held_data.a_data[(i * 8)+:8] : gen_integ_handling.rsp_data[(i * 8)+:8])
-------------------1------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T5,T10,T7 |
| 1 | Covered | T2,T5,T10 |
LINE 581
EXPRESSION (tl_i.d_ready | gen_integ_handling.rd_wait | gen_integ_handling.rdback_wait)
------1----- -------------2------------ ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T2,T14,T26 |
| 0 | 1 | 0 | Covered | T5,T10,T7 |
| 1 | 0 | 0 | Covered | T1,T2,T3 |
LINE 590
EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase | gen_integ_handling.rdback_phase_wrreadback)
-------------1------------- ---------------2--------------- ---------------------3--------------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T26,T29,T49 |
| 0 | 1 | 0 | Covered | T2,T14,T26 |
| 1 | 0 | 0 | Covered | T5,T10,T7 |
LINE 593
EXPRESSION (gen_integ_handling.wr_phase ? PutFullData : Get)
-------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T14,T26 |
| 1 | Covered | T5,T10,T7 |
LINE 596
EXPRESSION
Number Term
1 (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback) ? (2'(gen_integ_handling.AccessSize)) : gen_integ_handling.held_data.a_size)
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T14,T26 |
| 1 | Covered | T5,T10,T7 |
LINE 596
SUB-EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)
-------------1------------- ---------------------2--------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T2,T14,T26 |
| 0 | 1 | Covered | T26,T29,T49 |
| 1 | 0 | Covered | T5,T10,T7 |
LINE 598
EXPRESSION ((gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback) ? ('{(*adjust*)default:'1}) : gen_integ_handling.held_data.a_mask)
-------------------------------------1------------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T14,T26 |
| 1 | Covered | T5,T10,T7 |
LINE 598
SUB-EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)
-------------1------------- ---------------------2--------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T2,T14,T26 |
| 0 | 1 | Covered | T26,T29,T49 |
| 1 | 0 | Covered | T5,T10,T7 |
LINE 603
EXPRESSION
Number Term
1 (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback) ? '0 : gen_integ_handling.held_data.a_address[(gen_integ_handling.AccessSize - 1):0])
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T14,T26 |
| 1 | Covered | T5,T10,T7 |
LINE 603
SUB-EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)
-------------1------------- ---------------------2--------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T2,T14,T26 |
| 0 | 1 | Covered | T26,T29,T49 |
| 1 | 0 | Covered | T5,T10,T7 |
LINE 607
EXPRESSION (gen_integ_handling.wr_phase ? gen_integ_handling.combined_data : '0)
-------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T14,T26 |
| 1 | Covered | T5,T10,T7 |
LINE 608
EXPRESSION (gen_integ_handling.wr_phase ? gen_integ_handling.combined_user : '0)
-------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T14,T26 |
| 1 | Covered | T5,T10,T7 |
LINE 614
EXPRESSION (((!error_i)) || gen_integ_handling.stall_host)
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T28,T29,T19 |
| 0 | 1 | Covered | T5,T10,T7 |
| 1 | 0 | Covered | T5,T10,T7 |
LINE 620
EXPRESSION (tl_i.a_valid & ((~gen_integ_handling.stall_host)))
------1----- -----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T5,T10,T7 |
| 1 | 1 | Covered | T5,T10,T7 |
LINE 633
EXPRESSION (error_i & ((~gen_integ_handling.stall_host)))
---1--- -----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T4,T5 |
| 1 | 0 | Covered | T2,T5,T10 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 661
EXPRESSION (tl_sram_i.a_ready & ((~gen_integ_handling.stall_host)) & gen_integ_handling.fifo_rdy & gen_integ_handling.size_fifo_rdy)
--------1-------- -----------------2---------------- -------------3------------- ----------------4---------------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T5 |
| 1 | 0 | 1 | 1 | Covered | T26,T29,T49 |
| 1 | 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 665
EXPRESSION (tl_sram_i.d_valid & ((~gen_integ_handling.rd_wait)) & ((~gen_integ_handling.rdback_wait)))
--------1-------- ---------------2--------------- -----------------3-----------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T5,T10,T7 |
| 1 | 1 | 0 | Covered | T2,T14,T26 |
| 1 | 1 | 1 | Covered | T2,T4,T5 |
LINE 699
EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase | gen_integ_handling.rdback_phase_wrreadback)
-------------1------------- ---------------2--------------- ---------------------3--------------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T26,T29,T49 |
| 0 | 1 | 0 | Covered | T2,T14,T26 |
| 1 | 0 | 0 | Covered | T5,T10,T7 |
FSM Coverage for Module :
tlul_sram_byte
Summary for FSM :: gen_integ_handling.state_q
| Total | Covered | Percent | |
| States |
11 |
11 |
100.00 |
(Not included in score) |
| Transitions |
17 |
17 |
100.00 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: gen_integ_handling.state_q
| states | Line No. | Covered | Tests |
| StByteWrReadBack |
403 |
Covered |
T26,T29,T49 |
| StByteWrReadBackDWait |
409 |
Covered |
T26,T50,T46 |
| StByteWrReadBackInit |
310 |
Covered |
T26,T29,T49 |
| StPassThru |
310 |
Covered |
T1,T2,T3 |
| StRdReadBack |
281 |
Covered |
T26,T47,T15 |
| StRdReadBackDWait |
470 |
Covered |
T47,T15,T48 |
| StWaitRd |
274 |
Covered |
T5,T10,T7 |
| StWrReadBack |
340 |
Covered |
T2,T14,T26 |
| StWrReadBackDWait |
343 |
Covered |
T47,T48,T46 |
| StWrReadBackInit |
281 |
Covered |
T2,T14,T26 |
| StWriteCmd |
300 |
Covered |
T5,T10,T7 |
| transitions | Line No. | Covered | Tests |
| StByteWrReadBack->StPassThru |
426 |
Covered |
T26,T29,T49 |
| StByteWrReadBackDWait->StByteWrReadBack |
443 |
Covered |
T26,T50,T46 |
| StByteWrReadBackInit->StByteWrReadBack |
403 |
Covered |
T26,T29,T49 |
| StByteWrReadBackInit->StByteWrReadBackDWait |
409 |
Covered |
T26,T50,T46 |
| StPassThru->StRdReadBack |
281 |
Covered |
T26,T47,T15 |
| StPassThru->StWaitRd |
274 |
Covered |
T5,T10,T7 |
| StPassThru->StWrReadBackInit |
281 |
Covered |
T2,T14,T26 |
| StRdReadBack->StPassThru |
463 |
Covered |
T26,T47,T15 |
| StRdReadBack->StRdReadBackDWait |
470 |
Covered |
T47,T15,T48 |
| StRdReadBackDWait->StPassThru |
486 |
Covered |
T47,T15,T48 |
| StWaitRd->StWriteCmd |
300 |
Covered |
T5,T10,T7 |
| StWrReadBack->StPassThru |
359 |
Covered |
T2,T14,T26 |
| StWrReadBackDWait->StWrReadBack |
378 |
Covered |
T47,T48,T46 |
| StWrReadBackInit->StWrReadBack |
340 |
Covered |
T2,T14,T26 |
| StWrReadBackInit->StWrReadBackDWait |
343 |
Covered |
T47,T48,T46 |
| StWriteCmd->StByteWrReadBackInit |
310 |
Covered |
T26,T29,T49 |
| StWriteCmd->StPassThru |
310 |
Covered |
T5,T10,T7 |
Branch Coverage for Module :
tlul_sram_byte
| Line No. | Total | Covered | Percent |
| Branches |
|
61 |
57 |
93.44 |
| IF |
105 |
2 |
2 |
100.00 |
| CASE |
255 |
39 |
35 |
89.74 |
| IF |
542 |
2 |
2 |
100.00 |
| TERNARY |
554 |
2 |
2 |
100.00 |
| IF |
590 |
16 |
16 |
100.00 |
105 if (!rst_ni) begin
-1-
106 state_q <= StPassThru;
==>
107 end else begin
108 state_q <= state_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
255 unique case (state_q)
-1-
256 StPassThru: begin
257 if (mubi4_test_true_loose(rdback_en_q) && mubi4_test_true_loose(rdback_check_q)) begin
-2-
258 // When we're expecting a readback check that means we'll see a data response from the
259 // SRAM this cycle which we need to check against the readback registers. During this
260 // cycle the data response out (via tl_o) will be squashed to invalid but we can accept
261 // a new transaction (via tl_i).
262 rdback_wait = 1'b1;
263 rdback_check_d = MuBi4False;
264
265 // Perform the readback check.
266 if (!rdback_chk_ok) begin
-3-
267 alert_o = 1'b1;
==>
268 end
MISSING_ELSE
==>
269 end
MISSING_ELSE
==>
270
271 if (byte_wr_txn) begin
-4-
272 rd_phase = 1'b1;
273 if (byte_req_ack) begin
-5-
274 state_d = StWaitRd;
==>
275 end
MISSING_ELSE
==>
276 end else if (a_ack && mubi4_test_true_loose(rdback_en_q) && !error_i) begin
-6-
277 // For reads and full word writes we'll first do the transaction and then do a readback
278 // check. Setting `hold_tx_data` here will preserve the transaction information in
279 // u_sync_fifo for doing the readback transaction.
280 hold_tx_data = 1'b1;
281 state_d = wr_txn ? StWrReadBackInit : StRdReadBack;
-7-
==>
==>
282 end
MISSING_ELSE
==>
283
284 if (!tl_sram_o.a_valid && !tl_o.d_valid &&
-8-
285 mubi4_test_false_strict(rdback_check_q)) begin
286 // Store readback enable into register when bus is idle and no readback is processed.
287 rdback_en_d = readback_en_i;
==>
288 end
MISSING_ELSE
==>
289 end
290
291 // Due to the way things are serialized, there is no way for the logic to tell which read
292 // belongs to the partial read unless it flushes all prior transactions. Hence, we wait
293 // here until exactly one outstanding transaction remains (that one is the partial read).
294 StWaitRd: begin
295 rd_phase = 1'b1;
296 stall_host = 1'b1;
297 if (pending_txn_cnt == PendingTxnCntW'(1)) begin
-9-
298 rd_wait = 1'b1;
299 if (sram_d_ack) begin
-10-
300 state_d = StWriteCmd;
==>
301 end
MISSING_ELSE
==>
302 end
MISSING_ELSE
==>
303 end
304
305 StWriteCmd: begin
306 stall_host = 1'b1;
307 wr_phase = 1'b1;
308
309 if (sram_a_ack) begin
-11-
310 state_d = mubi4_test_true_loose(rdback_en_q) ? StByteWrReadBackInit : StPassThru;
==>
311 rdback_check_d = mubi4_test_true_loose(rdback_en_q) ? MuBi4True : MuBi4False;
312 rdback_data_exp_d = tl_sram_o.a_data;
313 rdback_data_exp_intg_d = tl_sram_o.a_user.data_intg;
314 end
MISSING_ELSE
==>
315 end
316
317 StWrReadBackInit: begin
318 // Perform readback after full write. To avoid that we read the holding register
319 // in the readback, wait until the write was processed by the memory module.
320 if (EnableReadback == 0) begin : gen_inv_state_StWrReadBackInit
-12-
321 // If readback is disabled, we shouldn't be in this state.
322 alert_o = 1'b1;
==> (Unreachable)
323 end
MISSING_ELSE
==>
324
325 // Stall the host to perform the readback in the next cycle.
326 stall_host = 1'b1;
327
328 // Need to ensure there's no other transactions in flight before we do the readback (the
329 // initial write we're doing the readback for should be the only one active).
330 if (pending_txn_cnt == PendingTxnCntW'(1)) begin
-13-
331 wait_phase = 1'b1;
332 // Data we're checking against the readback is captured from the write transaction that
333 // was sent.
334 rdback_check_d = mubi4_test_true_loose(rdback_en_q) ? MuBi4True : MuBi4False;
335 rdback_data_exp_d = held_data.a_data;
336 rdback_data_exp_intg_d = held_data.a_user.data_intg;
337 if (d_ack) begin
-14-
338 // Got an immediate TL-UL write response. Wait for one cycle until the holding
339 // register is flushed and then perform the readback.
340 state_d = StWrReadBack;
==>
341 end else begin
342 // No response yet to the initial write.
343 state_d = StWrReadBackDWait;
==>
344 end
345 end
MISSING_ELSE
==>
346 end
347
348 StWrReadBack: begin
349 // Perform readback and check response in StPassThru.
350 if (EnableReadback == 0) begin : gen_inv_state_StWrReadBack
-15-
351 // If readback is disabled, we shouldn't be in this state.
352 alert_o = 1'b1;
==> (Unreachable)
353 end
MISSING_ELSE
==>
354
355 stall_host = 1'b1;
356
357 rdback_phase = 1'b1;
358
359 state_d = StPassThru;
360 end
361
362 StWrReadBackDWait: begin
363 // We have not received the d_valid response of the initial write. Wait
364 // for the valid signal.
365 if (EnableReadback == 0) begin : gen_inv_state_StWrReadBackDWait
-16-
366 // If readback is disabled, we shouldn't be in this state.
367 alert_o = 1'b1;
==> (Unreachable)
368 end
MISSING_ELSE
==>
369
370 // Wait until we get write response.
371 wait_phase = 1'b1;
372
373 stall_host = 1'b1;
374
375 if (d_ack) begin
-17-
376 // Got the TL-UL write response. Wait for one cycle until the holding
377 // register is flushed and then perform the readback.
378 state_d = StWrReadBack;
==>
379 end
MISSING_ELSE
==>
380 end
381
382 StByteWrReadBackInit: begin
383 // Perform readback after partial write. To avoid that we read the holding register
384 // in the readback, do the actual readback check in the next FSM state.
385 if (EnableReadback == 0) begin : gen_inv_state_StByteWrReadBackInit
-18-
386 // If readback is disabled, we shouldn't be in this state.
387 alert_o = 1'b1;
==> (Unreachable)
388 end
MISSING_ELSE
==>
389
390 // Sends out a read to a readback check on a partial write. The host is stalled whilst
391 // this is happening.
392 stall_host = 1'b1;
393
394 // Wait until there is a single ongoing transaction.
395 if (pending_txn_cnt == PendingTxnCntW'(1)) begin
-19-
396 // Wait for one cycle with sending readback request to SRAM to avoid reading from
397 // holding register.
398 wait_phase = 1'b1;
399
400 if (d_ack) begin
-20-
401 // Got an immediate TL-UL write response. Wait for one cycle until the holding
402 // register is flushed and then perform the readback.
403 state_d = StByteWrReadBack;
==>
404 end else begin
405 // No response received for initial write. We already can send the
406 // request for the readback in the next cycle but we need to wait
407 // for the response for the initial write before doing the readback
408 // check.
409 state_d = StByteWrReadBackDWait;
==>
410 end
411 end
MISSING_ELSE
==>
412 end
413
414 StByteWrReadBack: begin
415 // Wait until the memory module has completed the partial write.
416 // Perform readback and check response in StPassThru.
417 if (EnableReadback == 0) begin : gen_inv_state_StByteWrReadBack
-21-
418 // If readback is disabled, we shouldn't be in this state.
419 alert_o = 1'b1;
==> (Unreachable)
420 end
MISSING_ELSE
==>
421
422 stall_host = 1'b1;
423
424 rdback_phase_wrreadback = 1'b1;
425
426 state_d = StPassThru;
427 end
428
429 StByteWrReadBackDWait: begin
430 if (EnableReadback == 0) begin : gen_inv_state_StByteWrReadBackDWait
-22-
431 // If readback is disabled, we shouldn't be in this state.
432 alert_o = 1'b1;
==> (Unreachable)
433 end
MISSING_ELSE
==>
434
435 stall_host = 1'b1;
436
437 // Wait for one cycle with sending readback request to SRAM.
438 wait_phase = 1'b1;
439
440 if (d_ack) begin
-23-
441 // Got the TL-UL write response. Wait for one cycle until the holding
442 // register is flushed and then perform the readback.
443 state_d = StByteWrReadBack;
==>
444 end
MISSING_ELSE
==>
445 end
446
447 StRdReadBack: begin
448 if (EnableReadback == 0) begin : gen_inv_state_StRdReadBack
-24-
449 // If readback is disabled, we shouldn't be in this state.
450 alert_o = 1'b1;
==> (Unreachable)
451 end
MISSING_ELSE
==>
452
453 // Sends out a read to a readback check on a read. The host is stalled whilst
454 // this is happening.
455 stall_host = 1'b1;
456
457 // Need to ensure there's no other transactions in flight before we do the readback (the
458 // read we're doing the readback for should be the only one active).
459 if (pending_txn_cnt == PendingTxnCntW'(1)) begin
-25-
460 rdback_phase = 1'b1;
461
462 if (d_ack) begin
-26-
463 state_d = StPassThru;
==>
464 // Data for the readback check comes from the first read.
465 rdback_check_d = mubi4_test_true_loose(rdback_en_q) ? MuBi4True : MuBi4False;
466 rdback_data_exp_d = tl_o.d_data;
467 rdback_data_exp_intg_d = tl_o.d_user.data_intg;
468 end else begin
469 // No response yet to the initial read, so go wait for it.
470 state_d = StRdReadBackDWait;
==>
471 end
472 end
MISSING_ELSE
==>
473 end
474
475 StRdReadBackDWait : begin
476 if (EnableReadback == 0) begin : gen_inv_state_StRdReadBackDWait
-27-
477 // If readback is disabled, we shouldn't be in this state.
478 alert_o = 1'b1;
==> (Unreachable)
479 end
MISSING_ELSE
==>
480
481 stall_host = 1'b1;
482
483 if (d_ack) begin
-28-
484 // Response received for first read. Now need to await data for the readback check
485 // which is done in the `StPassThru` state.
486 state_d = StPassThru;
==>
487 // Data for the readback check comes from the first read.
488 rdback_check_d = mubi4_test_true_loose(rdback_en_q) ? MuBi4True : MuBi4False;
489 rdback_data_exp_d = tl_o.d_data;
490 rdback_data_exp_intg_d = tl_o.d_user.data_intg;
491 end
MISSING_ELSE
==>
492 end
493
494 default: begin
495 alert_o = 1'b1;
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | -14- | -15- | -16- | -17- | -18- | -19- | -20- | -21- | -22- | -23- | -24- | -25- | -26- | -27- | -28- | Status | Tests |
| StPassThru |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T14,T15 |
| StPassThru |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T14,T26 |
| StPassThru |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| StPassThru |
- |
- |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T5,T10,T7 |
| StPassThru |
- |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T7,T28,T51 |
| StPassThru |
- |
- |
0 |
- |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T14,T26 |
| StPassThru |
- |
- |
0 |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T26,T47,T15 |
| StPassThru |
- |
- |
0 |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| StPassThru |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| StPassThru |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T4,T5 |
| StWaitRd |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T5,T10,T7 |
| StWaitRd |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
| StWaitRd |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T7,T28,T51 |
| StWriteCmd |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T5,T10,T7 |
| StWriteCmd |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
| StWrReadBackInit |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
|
| StWrReadBackInit |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T14,T26 |
| StWrReadBackInit |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T14,T26 |
| StWrReadBackInit |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T14,T26 |
| StWrReadBackInit |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T46,T52,T53 |
| StWrReadBack |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
|
| StWrReadBack |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T14,T26 |
| StWrReadBackDWait |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
|
| StWrReadBackDWait |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T47,T48,T46 |
| StWrReadBackDWait |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T47,T48,T46 |
| StWrReadBackDWait |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T47,T48,T46 |
| StByteWrReadBackInit |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
|
| StByteWrReadBackInit |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T26,T29,T49 |
| StByteWrReadBackInit |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T26,T29,T49 |
| StByteWrReadBackInit |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T26,T49,T50 |
| StByteWrReadBackInit |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
| StByteWrReadBack |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
|
| StByteWrReadBack |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T26,T29,T49 |
| StByteWrReadBackDWait |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
Unreachable |
|
| StByteWrReadBackDWait |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T26,T50,T46 |
| StByteWrReadBackDWait |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T26,T50,T46 |
| StByteWrReadBackDWait |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
Covered |
T26,T50,T46 |
| StRdReadBack |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
Unreachable |
|
| StRdReadBack |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
Covered |
T26,T47,T15 |
| StRdReadBack |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
- |
- |
Covered |
T26,T47,T15 |
| StRdReadBack |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
Covered |
T26,T47,T15 |
| StRdReadBack |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
Covered |
T52,T53 |
| StRdReadBackDWait |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
Unreachable |
|
| StRdReadBackDWait |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
Covered |
T47,T15,T48 |
| StRdReadBackDWait |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T47,T15,T48 |
| StRdReadBackDWait |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T47,T15,T48 |
| default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
542 if (sram_d_ack && rd_wait) begin
-1-
543 rsp_data <= tl_sram_i.d_data;
==>
544 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T10,T7 |
| 0 |
Covered |
T1,T2,T3 |
554 combined_data[i*8 +: 8] = held_data.a_mask[i] ?
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T5,T10 |
| 0 |
Covered |
T5,T10,T7 |
590 if (wr_phase | rdback_phase | rdback_phase_wrreadback) begin
-1-
591 tl_sram_o.a_valid = 1'b1;
592 // During a read-modify write, always access the entire word.
593 tl_sram_o.a_opcode = wr_phase ? PutFullData : Get;
-2-
==>
==>
594 // In either read-modify write or SRAM readback mode, use the mask, size and address
595 // of the original request.
596 tl_sram_o.a_size =
597 (wr_phase | rdback_phase_wrreadback) ? top_pkg::TL_SZW'(AccessSize) : held_data.a_size;
-3-
==>
==>
598 tl_sram_o.a_mask =
599 (wr_phase | rdback_phase_wrreadback) ? '{default: '1} : held_data.a_mask;
-4-
==>
==>
600 // override with held / combined data.
601 // need to use word aligned addresses here.
602 tl_sram_o.a_address = held_data.a_address;
603 tl_sram_o.a_address[AccessSize-1:0] =
604 (wr_phase | rdback_phase_wrreadback) ? '0 : held_data.a_address[AccessSize-1:0];
-5-
==>
==>
605 tl_sram_o.a_source = held_data.a_source;
606 tl_sram_o.a_param = held_data.a_param;
607 tl_sram_o.a_data = wr_phase ? combined_data : '0;
-6-
==>
==>
608 tl_sram_o.a_user = wr_phase ? combined_user : '0;
-7-
==>
==>
609 // Read transactions for RMW.
610 end else if (rd_phase) begin
-8-
611 // need to use word aligned addresses here.
612 tl_sram_o.a_address[AccessSize-1:0] = '0;
613 // Only override the control signals if there is no error at the input.
614 if (!error_i || stall_host) begin
-9-
615 // Since we are performing a read-modify-write operation,
616 // we always access the entire word.
617 tl_sram_o.a_size = top_pkg::TL_SZW'(AccessSize);
==>
618 tl_sram_o.a_mask = '{default: '1};
619 // use incoming valid as long as we are not stalling the host
620 tl_sram_o.a_valid = tl_i.a_valid & ~stall_host;
621 tl_sram_o.a_opcode = Get;
622 end
MISSING_ELSE
==>
623 end else if (wait_phase) begin
-10-
624 // Delay the readback request to avoid that we are reading the holding
625 // register.
626 tl_sram_o.a_valid = 1'b0;
==>
627 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | Status | Tests |
| 1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T5,T10,T7 |
| 1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T14,T26 |
| 1 |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T5,T10,T7 |
| 1 |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T14,T26 |
| 1 |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T5,T10,T7 |
| 1 |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T2,T14,T26 |
| 1 |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T5,T10,T7 |
| 1 |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
Covered |
T2,T14,T26 |
| 1 |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
Covered |
T5,T10,T7 |
| 1 |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
Covered |
T2,T14,T26 |
| 1 |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
Covered |
T5,T10,T7 |
| 1 |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
Covered |
T2,T14,T26 |
| 0 |
- |
- |
- |
- |
- |
- |
1 |
1 |
- |
Covered |
T5,T10,T7 |
| 0 |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
Covered |
T28,T29,T19 |
| 0 |
- |
- |
- |
- |
- |
- |
0 |
- |
1 |
Covered |
T2,T14,T26 |
| 0 |
- |
- |
- |
- |
- |
- |
0 |
- |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
tlul_sram_byte
Assertion Details
SramReadbackAndIntg
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
944 |
944 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
gen_integ_handling.ByteAccessStateChange_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
339860600 |
6207205 |
0 |
0 |
| T5 |
6298 |
1025 |
0 |
0 |
| T6 |
38390 |
0 |
0 |
0 |
| T7 |
69128 |
5 |
0 |
0 |
| T8 |
17872 |
22 |
0 |
0 |
| T10 |
47016 |
269 |
0 |
0 |
| T11 |
7027 |
306 |
0 |
0 |
| T25 |
23722 |
466 |
0 |
0 |
| T26 |
0 |
1010 |
0 |
0 |
| T27 |
2751 |
0 |
0 |
0 |
| T28 |
0 |
425 |
0 |
0 |
| T32 |
16294 |
1902 |
0 |
0 |
| T36 |
8639 |
0 |
0 |
0 |
| T40 |
0 |
547 |
0 |
0 |
gen_integ_handling.ReadCompleteStateChange_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
339860600 |
6207205 |
0 |
0 |
| T5 |
6298 |
1025 |
0 |
0 |
| T6 |
38390 |
0 |
0 |
0 |
| T7 |
69128 |
5 |
0 |
0 |
| T8 |
17872 |
22 |
0 |
0 |
| T10 |
47016 |
269 |
0 |
0 |
| T11 |
7027 |
306 |
0 |
0 |
| T25 |
23722 |
466 |
0 |
0 |
| T26 |
0 |
1010 |
0 |
0 |
| T27 |
2751 |
0 |
0 |
0 |
| T28 |
0 |
425 |
0 |
0 |
| T32 |
16294 |
1902 |
0 |
0 |
| T36 |
8639 |
0 |
0 |
0 |
| T40 |
0 |
547 |
0 |
0 |
gen_integ_handling.ReadbackAccessAlwaysGranted_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
339860600 |
188964 |
0 |
0 |
| T12 |
859 |
0 |
0 |
0 |
| T16 |
14412 |
0 |
0 |
0 |
| T18 |
219341 |
0 |
0 |
0 |
| T26 |
17939 |
817 |
0 |
0 |
| T28 |
128791 |
0 |
0 |
0 |
| T29 |
0 |
4736 |
0 |
0 |
| T40 |
10524 |
0 |
0 |
0 |
| T47 |
0 |
44 |
0 |
0 |
| T48 |
0 |
197 |
0 |
0 |
| T49 |
0 |
889 |
0 |
0 |
| T54 |
0 |
4094 |
0 |
0 |
| T55 |
0 |
77 |
0 |
0 |
| T56 |
0 |
25088 |
0 |
0 |
| T57 |
0 |
874 |
0 |
0 |
| T58 |
0 |
4094 |
0 |
0 |
| T59 |
170358 |
0 |
0 |
0 |
| T60 |
11556 |
0 |
0 |
0 |
| T61 |
9322 |
0 |
0 |
0 |
| T62 |
4470 |
0 |
0 |
0 |
gen_integ_handling.ReadbackDataImmediatelyAvailable_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
339860600 |
254076 |
0 |
0 |
| T12 |
859 |
0 |
0 |
0 |
| T16 |
14412 |
0 |
0 |
0 |
| T18 |
219341 |
0 |
0 |
0 |
| T26 |
17939 |
933 |
0 |
0 |
| T28 |
128791 |
0 |
0 |
0 |
| T29 |
0 |
4519 |
0 |
0 |
| T40 |
10524 |
0 |
0 |
0 |
| T47 |
0 |
119 |
0 |
0 |
| T48 |
0 |
495 |
0 |
0 |
| T49 |
0 |
869 |
0 |
0 |
| T54 |
0 |
6141 |
0 |
0 |
| T55 |
0 |
225 |
0 |
0 |
| T56 |
0 |
26259 |
0 |
0 |
| T57 |
0 |
871 |
0 |
0 |
| T58 |
0 |
6141 |
0 |
0 |
| T59 |
170358 |
0 |
0 |
0 |
| T60 |
11556 |
0 |
0 |
0 |
| T61 |
9322 |
0 |
0 |
0 |
| T62 |
4470 |
0 |
0 |
0 |
gen_integ_handling.TlulSramByteTlSize_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
339860600 |
339753777 |
0 |
0 |
| T1 |
2648 |
2571 |
0 |
0 |
| T2 |
1170 |
1095 |
0 |
0 |
| T3 |
1447 |
1386 |
0 |
0 |
| T4 |
7305 |
7253 |
0 |
0 |
| T5 |
6298 |
6233 |
0 |
0 |
| T6 |
38390 |
33020 |
0 |
0 |
| T7 |
69128 |
68910 |
0 |
0 |
| T8 |
17872 |
17733 |
0 |
0 |
| T10 |
47016 |
46956 |
0 |
0 |
| T11 |
7027 |
6955 |
0 |
0 |
gen_integ_handling.gen_readback_logic.NoPendingWriteAfterWrite_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
339860600 |
22665 |
0 |
0 |
| T12 |
859 |
0 |
0 |
0 |
| T16 |
14412 |
0 |
0 |
0 |
| T18 |
219341 |
0 |
0 |
0 |
| T26 |
17939 |
1010 |
0 |
0 |
| T28 |
128791 |
0 |
0 |
0 |
| T29 |
0 |
216 |
0 |
0 |
| T40 |
10524 |
0 |
0 |
0 |
| T46 |
0 |
1 |
0 |
0 |
| T49 |
0 |
525 |
0 |
0 |
| T50 |
0 |
222 |
0 |
0 |
| T56 |
0 |
1153 |
0 |
0 |
| T57 |
0 |
518 |
0 |
0 |
| T59 |
170358 |
0 |
0 |
0 |
| T60 |
11556 |
0 |
0 |
0 |
| T61 |
9322 |
0 |
0 |
0 |
| T62 |
4470 |
0 |
0 |
0 |
| T63 |
0 |
544 |
0 |
0 |
| T64 |
0 |
316 |
0 |
0 |
| T65 |
0 |
562 |
0 |
0 |
gen_integ_handling.gen_readback_logic.WRCollisionDuringReadBack_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
339860600 |
363704 |
0 |
0 |
| T12 |
859 |
0 |
0 |
0 |
| T16 |
14412 |
0 |
0 |
0 |
| T18 |
219341 |
0 |
0 |
0 |
| T26 |
17939 |
1968 |
0 |
0 |
| T28 |
128791 |
0 |
0 |
0 |
| T29 |
0 |
4830 |
0 |
0 |
| T40 |
10524 |
0 |
0 |
0 |
| T47 |
0 |
827 |
0 |
0 |
| T48 |
0 |
3253 |
0 |
0 |
| T49 |
0 |
941 |
0 |
0 |
| T54 |
0 |
6142 |
0 |
0 |
| T55 |
0 |
1361 |
0 |
0 |
| T56 |
0 |
26984 |
0 |
0 |
| T57 |
0 |
935 |
0 |
0 |
| T58 |
0 |
6142 |
0 |
0 |
| T59 |
170358 |
0 |
0 |
0 |
| T60 |
11556 |
0 |
0 |
0 |
| T61 |
9322 |
0 |
0 |
0 |
| T62 |
4470 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 145 | 145 | 100.00 |
| ALWAYS | 105 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 142 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| ALWAYS | 239 | 95 | 95 | 100.00 |
| CONT_ASSIGN | 506 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 517 | 1 | 1 | 100.00 |
| ALWAYS | 542 | 2 | 2 | 100.00 |
| ALWAYS | 553 | 0 | 0 | |
| ALWAYS | 553 | 2 | 2 | 100.00 |
| ALWAYS | 572 | 2 | 2 | 100.00 |
| ALWAYS | 579 | 22 | 22 | 100.00 |
| CONT_ASSIGN | 633 | 1 | 1 | 100.00 |
| ALWAYS | 658 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 676 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 699 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 716 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 717 | 1 | 1 | 100.00 |
104 always_ff @(posedge clk_i or negedge rst_ni) begin
105 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
106 1/1 state_q <= StPassThru;
Tests: T1 T2 T3
107 end else begin
108 1/1 state_q <= state_d;
Tests: T1 T2 T3
109 end
110 end
111
112 // transaction qualifying signals
113 logic a_ack; // upstream a channel acknowledgement
114 logic d_ack; // upstream d channel acknowledgement
115 logic sram_a_ack; // downstream a channel acknowledgement
116 logic sram_d_ack; // downstream d channel acknowledgement
117 logic wr_txn;
118 logic byte_wr_txn;
119 logic byte_req_ack;
120 logic hold_tx_data;
121
122 localparam int unsigned PendingTxnCntW = prim_util_pkg::vbits(Outstanding+1);
123 logic [PendingTxnCntW-1:0] pending_txn_cnt;
124
125 // prim fifo for capturing info
126 typedef struct packed {
127 logic [2:0] a_param;
128 logic [top_pkg::TL_SZW-1:0] a_size;
129 logic [top_pkg::TL_AIW-1:0] a_source;
130 logic [top_pkg::TL_AW-1:0] a_address;
131 logic [top_pkg::TL_DBW-1:0] a_mask;
132 logic [top_pkg::TL_DW-1:0] a_data;
133 tl_a_user_t a_user;
134 } tl_txn_data_t;
135
136 tl_txn_data_t held_data;
137
138 1/1 assign a_ack = tl_i.a_valid & tl_o.a_ready;
Tests: T1 T2 T3
139 1/1 assign d_ack = tl_o.d_valid & tl_i.d_ready;
Tests: T1 T2 T3
140 1/1 assign sram_a_ack = tl_sram_o.a_valid & tl_sram_i.a_ready;
Tests: T1 T2 T3
141 1/1 assign sram_d_ack = tl_sram_i.d_valid & tl_sram_o.d_ready;
Tests: T1 T2 T3
142 1/1 assign wr_txn = (tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData);
Tests: T1 T2 T3
143
144 1/1 assign byte_req_ack = byte_wr_txn & a_ack & ~error_i;
Tests: T1 T2 T3
145 1/1 assign byte_wr_txn = tl_i.a_valid & ~&tl_i.a_mask & wr_txn;
Tests: T1 T2 T3
146
147 logic rdback_chk_ok;
148 mubi4_t rdback_check_q, rdback_check_d;
149 mubi4_t rdback_en_q, rdback_en_d;
150 logic [31:0] rdback_data_exp_q, rdback_data_exp_d;
151 logic [DataIntgWidth-1:0] rdback_data_exp_intg_q, rdback_data_exp_intg_d;
152
153 if (EnableReadback) begin : gen_readback_logic
154 logic rdback_chk_ok_unbuf;
155
156 1/1 assign rdback_chk_ok_unbuf = (rdback_data_exp_q == tl_sram_i.d_data);
Tests: T1 T2 T3
157
158 prim_sec_anchor_buf #(
159 .Width(1)
160 ) u_rdback_chk_ok_buf (
161 .in_i (rdback_chk_ok_unbuf),
162 .out_o(rdback_chk_ok)
163 );
164
165 prim_flop #(
166 .Width(MuBi4Width),
167 .ResetValue(MuBi4Width'(MuBi4False))
168 ) u_rdback_check_flop (
169 .clk_i,
170 .rst_ni,
171
172 .d_i(MuBi4Width'(rdback_check_d)),
173 .q_o({rdback_check_q})
174 );
175
176 prim_flop #(
177 .Width(MuBi4Width),
178 .ResetValue(MuBi4Width'(MuBi4False))
179 ) u_rdback_en_flop (
180 .clk_i,
181 .rst_ni,
182
183 .d_i(MuBi4Width'(rdback_en_d)),
184 .q_o({rdback_en_q})
185 );
186
187 prim_flop #(
188 .Width(32),
189 .ResetValue(0)
190 ) u_rdback_data_exp (
191 .clk_i,
192 .rst_ni,
193
194 .d_i(rdback_data_exp_d),
195 .q_o(rdback_data_exp_q)
196 );
197
198 prim_flop #(
199 .Width(DataIntgWidth),
200 .ResetValue(0)
201 ) u_rdback_data_exp_intg (
202 .clk_i,
203 .rst_ni,
204
205 .d_i(rdback_data_exp_intg_d),
206 .q_o(rdback_data_exp_intg_q)
207 );
208
209 // If the readback feature is enabled and we are currently in the readback phase,
210 // no address collision should happen inside prim_ram_1p_scr. If this would be the
211 // case, we would read from the holding register inside prim_ram_1p_scr instead of
212 // actually performing the readback from the memory.
213 `ASSERT(WRCollisionDuringReadBack_A, (rdback_phase | rdback_phase_wrreadback) &
214 mubi4_test_true_loose(rdback_en_q) |-> !wr_collision_i)
215
216
217 // If the readback feature is enabled, we assume that the write phase takes one extra cycle
218 // due to the underyling scrambling mechanism. If this additional cycle is not needed anymore
219 // in the future (e.g. due to the removale of the scrambling mechanism), the readback does not
220 // need to be delayed by once cylce in the FSM below.
221 `ASSERT(NoPendingWriteAfterWrite_A, wr_phase & mubi4_test_true_loose(rdback_en_q)
222 |=> write_pending_i)
223
224
225 end else begin: gen_no_readback_logic
226 assign rdback_chk_ok = 1'b0;
227 assign rdback_check_q = MuBi4False;
228 assign rdback_en_q = MuBi4False;
229 assign rdback_data_exp_q = 1'b0;
230 assign rdback_data_exp_intg_q = 1'b0;
231
232 logic unused_rdback;
233
234 assign unused_rdback = ^{rdback_check_d, rdback_data_exp_d, rdback_data_exp_intg_d};
235 end
236
237 // state machine handling
238 always_comb begin
239 1/1 rd_wait = 1'b0;
Tests: T1 T2 T3
240 1/1 wait_phase = 1'b0;
Tests: T1 T2 T3
241 1/1 stall_host = 1'b0;
Tests: T1 T2 T3
242 1/1 wr_phase = 1'b0;
Tests: T1 T2 T3
243 1/1 rd_phase = 1'b0;
Tests: T1 T2 T3
244 1/1 rdback_phase = 1'b0;
Tests: T1 T2 T3
245 1/1 rdback_phase_wrreadback = 1'b0;
Tests: T1 T2 T3
246 1/1 rdback_wait = 1'b0;
Tests: T1 T2 T3
247 1/1 state_d = state_q;
Tests: T1 T2 T3
248 1/1 hold_tx_data = 1'b0;
Tests: T1 T2 T3
249 1/1 alert_o = 1'b0;
Tests: T1 T2 T3
250 1/1 rdback_check_d = rdback_check_q;
Tests: T1 T2 T3
251 1/1 rdback_en_d = rdback_en_q;
Tests: T1 T2 T3
252 1/1 rdback_data_exp_d = rdback_data_exp_q;
Tests: T1 T2 T3
253 1/1 rdback_data_exp_intg_d = rdback_data_exp_intg_q;
Tests: T1 T2 T3
254
255 1/1 unique case (state_q)
Tests: T1 T2 T3
256 StPassThru: begin
257 1/1 if (mubi4_test_true_loose(rdback_en_q) && mubi4_test_true_loose(rdback_check_q)) begin
Tests: T1 T2 T3
258 // When we're expecting a readback check that means we'll see a data response from the
259 // SRAM this cycle which we need to check against the readback registers. During this
260 // cycle the data response out (via tl_o) will be squashed to invalid but we can accept
261 // a new transaction (via tl_i).
262 1/1 rdback_wait = 1'b1;
Tests: T2 T14 T26
263 1/1 rdback_check_d = MuBi4False;
Tests: T2 T14 T26
264
265 // Perform the readback check.
266 1/1 if (!rdback_chk_ok) begin
Tests: T2 T14 T26
267 1/1 alert_o = 1'b1;
Tests: T2 T14 T15
268 end
MISSING_ELSE
269 end
MISSING_ELSE
270
271 1/1 if (byte_wr_txn) begin
Tests: T1 T2 T3
272 1/1 rd_phase = 1'b1;
Tests: T5 T10 T7
273 1/1 if (byte_req_ack) begin
Tests: T5 T10 T7
274 1/1 state_d = StWaitRd;
Tests: T5 T10 T7
275 end
MISSING_ELSE
276 1/1 end else if (a_ack && mubi4_test_true_loose(rdback_en_q) && !error_i) begin
Tests: T1 T2 T3
277 // For reads and full word writes we'll first do the transaction and then do a readback
278 // check. Setting `hold_tx_data` here will preserve the transaction information in
279 // u_sync_fifo for doing the readback transaction.
280 1/1 hold_tx_data = 1'b1;
Tests: T2 T14 T26
281 1/1 state_d = wr_txn ? StWrReadBackInit : StRdReadBack;
Tests: T2 T14 T26
282 end
MISSING_ELSE
283
284 1/1 if (!tl_sram_o.a_valid && !tl_o.d_valid &&
Tests: T1 T2 T3
285 mubi4_test_false_strict(rdback_check_q)) begin
286 // Store readback enable into register when bus is idle and no readback is processed.
287 1/1 rdback_en_d = readback_en_i;
Tests: T1 T2 T3
288 end
MISSING_ELSE
289 end
290
291 // Due to the way things are serialized, there is no way for the logic to tell which read
292 // belongs to the partial read unless it flushes all prior transactions. Hence, we wait
293 // here until exactly one outstanding transaction remains (that one is the partial read).
294 StWaitRd: begin
295 1/1 rd_phase = 1'b1;
Tests: T5 T10 T7
296 1/1 stall_host = 1'b1;
Tests: T5 T10 T7
297 1/1 if (pending_txn_cnt == PendingTxnCntW'(1)) begin
Tests: T5 T10 T7
298 1/1 rd_wait = 1'b1;
Tests: T5 T10 T7
299 1/1 if (sram_d_ack) begin
Tests: T5 T10 T7
300 1/1 state_d = StWriteCmd;
Tests: T5 T10 T7
301 end
==> MISSING_ELSE
302 end
MISSING_ELSE
303 end
304
305 StWriteCmd: begin
306 1/1 stall_host = 1'b1;
Tests: T5 T10 T7
307 1/1 wr_phase = 1'b1;
Tests: T5 T10 T7
308
309 1/1 if (sram_a_ack) begin
Tests: T5 T10 T7
310 1/1 state_d = mubi4_test_true_loose(rdback_en_q) ? StByteWrReadBackInit : StPassThru;
Tests: T5 T10 T7
311 1/1 rdback_check_d = mubi4_test_true_loose(rdback_en_q) ? MuBi4True : MuBi4False;
Tests: T5 T10 T7
312 1/1 rdback_data_exp_d = tl_sram_o.a_data;
Tests: T5 T10 T7
313 1/1 rdback_data_exp_intg_d = tl_sram_o.a_user.data_intg;
Tests: T5 T10 T7
314 end
==> MISSING_ELSE
315 end
316
317 StWrReadBackInit: begin
318 // Perform readback after full write. To avoid that we read the holding register
319 // in the readback, wait until the write was processed by the memory module.
320 1/1 if (EnableReadback == 0) begin : gen_inv_state_StWrReadBackInit
Tests: T2 T14 T26
321 // If readback is disabled, we shouldn't be in this state.
322 unreachable alert_o = 1'b1;
323 end
MISSING_ELSE
324
325 // Stall the host to perform the readback in the next cycle.
326 1/1 stall_host = 1'b1;
Tests: T2 T14 T26
327
328 // Need to ensure there's no other transactions in flight before we do the readback (the
329 // initial write we're doing the readback for should be the only one active).
330 1/1 if (pending_txn_cnt == PendingTxnCntW'(1)) begin
Tests: T2 T14 T26
331 1/1 wait_phase = 1'b1;
Tests: T2 T14 T26
332 // Data we're checking against the readback is captured from the write transaction that
333 // was sent.
334 1/1 rdback_check_d = mubi4_test_true_loose(rdback_en_q) ? MuBi4True : MuBi4False;
Tests: T2 T14 T26
335 1/1 rdback_data_exp_d = held_data.a_data;
Tests: T2 T14 T26
336 1/1 rdback_data_exp_intg_d = held_data.a_user.data_intg;
Tests: T2 T14 T26
337 1/1 if (d_ack) begin
Tests: T2 T14 T26
338 // Got an immediate TL-UL write response. Wait for one cycle until the holding
339 // register is flushed and then perform the readback.
340 1/1 state_d = StWrReadBack;
Tests: T2 T14 T26
341 end else begin
342 // No response yet to the initial write.
343 1/1 state_d = StWrReadBackDWait;
Tests: T2 T14 T26
344 end
345 end
MISSING_ELSE
346 end
347
348 StWrReadBack: begin
349 // Perform readback and check response in StPassThru.
350 1/1 if (EnableReadback == 0) begin : gen_inv_state_StWrReadBack
Tests: T2 T14 T26
351 // If readback is disabled, we shouldn't be in this state.
352 unreachable alert_o = 1'b1;
353 end
MISSING_ELSE
354
355 1/1 stall_host = 1'b1;
Tests: T2 T14 T26
356
357 1/1 rdback_phase = 1'b1;
Tests: T2 T14 T26
358
359 1/1 state_d = StPassThru;
Tests: T2 T14 T26
360 end
361
362 StWrReadBackDWait: begin
363 // We have not received the d_valid response of the initial write. Wait
364 // for the valid signal.
365 1/1 if (EnableReadback == 0) begin : gen_inv_state_StWrReadBackDWait
Tests: T47 T48 T46
366 // If readback is disabled, we shouldn't be in this state.
367 unreachable alert_o = 1'b1;
368 end
MISSING_ELSE
369
370 // Wait until we get write response.
371 1/1 wait_phase = 1'b1;
Tests: T47 T48 T46
372
373 1/1 stall_host = 1'b1;
Tests: T47 T48 T46
374
375 1/1 if (d_ack) begin
Tests: T47 T48 T46
376 // Got the TL-UL write response. Wait for one cycle until the holding
377 // register is flushed and then perform the readback.
378 1/1 state_d = StWrReadBack;
Tests: T47 T48 T46
379 end
MISSING_ELSE
380 end
381
382 StByteWrReadBackInit: begin
383 // Perform readback after partial write. To avoid that we read the holding register
384 // in the readback, do the actual readback check in the next FSM state.
385 1/1 if (EnableReadback == 0) begin : gen_inv_state_StByteWrReadBackInit
Tests: T26 T29 T49
386 // If readback is disabled, we shouldn't be in this state.
387 unreachable alert_o = 1'b1;
388 end
MISSING_ELSE
389
390 // Sends out a read to a readback check on a partial write. The host is stalled whilst
391 // this is happening.
392 1/1 stall_host = 1'b1;
Tests: T26 T29 T49
393
394 // Wait until there is a single ongoing transaction.
395 1/1 if (pending_txn_cnt == PendingTxnCntW'(1)) begin
Tests: T26 T29 T49
396 // Wait for one cycle with sending readback request to SRAM to avoid reading from
397 // holding register.
398 1/1 wait_phase = 1'b1;
Tests: T26 T29 T49
399
400 1/1 if (d_ack) begin
Tests: T26 T29 T49
401 // Got an immediate TL-UL write response. Wait for one cycle until the holding
402 // register is flushed and then perform the readback.
403 1/1 state_d = StByteWrReadBack;
Tests: T26 T29 T49
404 end else begin
405 // No response received for initial write. We already can send the
406 // request for the readback in the next cycle but we need to wait
407 // for the response for the initial write before doing the readback
408 // check.
409 1/1 state_d = StByteWrReadBackDWait;
Tests: T26 T49 T50
410 end
411 end
==> MISSING_ELSE
412 end
413
414 StByteWrReadBack: begin
415 // Wait until the memory module has completed the partial write.
416 // Perform readback and check response in StPassThru.
417 1/1 if (EnableReadback == 0) begin : gen_inv_state_StByteWrReadBack
Tests: T26 T29 T49
418 // If readback is disabled, we shouldn't be in this state.
419 unreachable alert_o = 1'b1;
420 end
MISSING_ELSE
421
422 1/1 stall_host = 1'b1;
Tests: T26 T29 T49
423
424 1/1 rdback_phase_wrreadback = 1'b1;
Tests: T26 T29 T49
425
426 1/1 state_d = StPassThru;
Tests: T26 T29 T49
427 end
428
429 StByteWrReadBackDWait: begin
430 1/1 if (EnableReadback == 0) begin : gen_inv_state_StByteWrReadBackDWait
Tests: T26 T50 T46
431 // If readback is disabled, we shouldn't be in this state.
432 unreachable alert_o = 1'b1;
433 end
MISSING_ELSE
434
435 1/1 stall_host = 1'b1;
Tests: T26 T50 T46
436
437 // Wait for one cycle with sending readback request to SRAM.
438 1/1 wait_phase = 1'b1;
Tests: T26 T50 T46
439
440 1/1 if (d_ack) begin
Tests: T26 T50 T46
441 // Got the TL-UL write response. Wait for one cycle until the holding
442 // register is flushed and then perform the readback.
443 1/1 state_d = StByteWrReadBack;
Tests: T26 T50 T46
444 end
MISSING_ELSE
445 end
446
447 StRdReadBack: begin
448 1/1 if (EnableReadback == 0) begin : gen_inv_state_StRdReadBack
Tests: T26 T47 T15
449 // If readback is disabled, we shouldn't be in this state.
450 unreachable alert_o = 1'b1;
451 end
MISSING_ELSE
452
453 // Sends out a read to a readback check on a read. The host is stalled whilst
454 // this is happening.
455 1/1 stall_host = 1'b1;
Tests: T26 T47 T15
456
457 // Need to ensure there's no other transactions in flight before we do the readback (the
458 // read we're doing the readback for should be the only one active).
459 1/1 if (pending_txn_cnt == PendingTxnCntW'(1)) begin
Tests: T26 T47 T15
460 1/1 rdback_phase = 1'b1;
Tests: T26 T47 T15
461
462 1/1 if (d_ack) begin
Tests: T26 T47 T15
463 1/1 state_d = StPassThru;
Tests: T26 T47 T15
464 // Data for the readback check comes from the first read.
465 1/1 rdback_check_d = mubi4_test_true_loose(rdback_en_q) ? MuBi4True : MuBi4False;
Tests: T26 T47 T15
466 1/1 rdback_data_exp_d = tl_o.d_data;
Tests: T26 T47 T15
467 1/1 rdback_data_exp_intg_d = tl_o.d_user.data_intg;
Tests: T26 T47 T15
468 end else begin
469 // No response yet to the initial read, so go wait for it.
470 1/1 state_d = StRdReadBackDWait;
Tests: T26 T47 T15
471 end
472 end
MISSING_ELSE
473 end
474
475 StRdReadBackDWait : begin
476 1/1 if (EnableReadback == 0) begin : gen_inv_state_StRdReadBackDWait
Tests: T47 T15 T48
477 // If readback is disabled, we shouldn't be in this state.
478 unreachable alert_o = 1'b1;
479 end
MISSING_ELSE
480
481 1/1 stall_host = 1'b1;
Tests: T47 T15 T48
482
483 1/1 if (d_ack) begin
Tests: T47 T15 T48
484 // Response received for first read. Now need to await data for the readback check
485 // which is done in the `StPassThru` state.
486 1/1 state_d = StPassThru;
Tests: T47 T15 T48
487 // Data for the readback check comes from the first read.
488 1/1 rdback_check_d = mubi4_test_true_loose(rdback_en_q) ? MuBi4True : MuBi4False;
Tests: T47 T15 T48
489 1/1 rdback_data_exp_d = tl_o.d_data;
Tests: T47 T15 T48
490 1/1 rdback_data_exp_intg_d = tl_o.d_user.data_intg;
Tests: T47 T15 T48
491 end
MISSING_ELSE
492 end
493
494 default: begin
495 alert_o = 1'b1;
496 end
497 endcase // unique case (state_q)
498
499 end
500
501 tl_txn_data_t txn_data;
502 logic fifo_rdy;
503 logic txn_data_wr;
504 localparam int TxnDataWidth = $bits(tl_txn_data_t);
505
506 1/1 assign txn_data = '{
Tests: T1 T2 T3
507 a_param: tl_i.a_param,
508 a_size: tl_i.a_size,
509 a_source: tl_i.a_source,
510 a_address: tl_i.a_address,
511 a_mask: tl_i.a_mask,
512 a_data: tl_i.a_data,
513 a_user: tl_i.a_user
514 };
515
516
517 1/1 assign txn_data_wr = hold_tx_data | byte_req_ack;
Tests: T1 T2 T3
518
519 prim_fifo_sync #(
520 .Width(TxnDataWidth),
521 .Pass(1'b0),
522 .Depth(1),
523 .OutputZeroIfEmpty(1'b0)
524 ) u_sync_fifo (
525 .clk_i,
526 .rst_ni,
527 .clr_i(1'b0),
528 .wvalid_i(txn_data_wr),
529 .wready_o(fifo_rdy),
530 .wdata_i(txn_data),
531 .rvalid_o(),
532 .rready_i(sram_a_ack),
533 .rdata_o(held_data),
534 .full_o(),
535 .depth_o(),
536 .err_o()
537 );
538
539 // captured read data
540 logic [top_pkg::TL_DW-1:0] rsp_data;
541 always_ff @(posedge clk_i) begin
542 1/1 if (sram_d_ack && rd_wait) begin
Tests: T1 T2 T3
543 1/1 rsp_data <= tl_sram_i.d_data;
Tests: T5 T10 T7
544 end
MISSING_ELSE
545 end
546
547 // while we could simply not assert a_ready to ensure the host keeps
548 // the request lines stable, there is no guarantee the hosts (if there are multiple)
549 // do not re-arbitrate on every cycle if its transactions are not accepted.
550 // As a result, it is better to capture the transaction attributes.
551 logic [top_pkg::TL_DW-1:0] combined_data, unused_data;
552 always_comb begin
553 1/1 for (int i = 0; i < top_pkg::TL_DBW; i++) begin
Tests: T2 T5 T10
554 1/1 combined_data[i*8 +: 8] = held_data.a_mask[i] ?
Tests: T2 T5 T10
555 held_data.a_data[i*8 +: 8] :
556 rsp_data[i*8 +: 8];
557 end
558 end
559
560 // Compute updated integrity bits for the data.
561 // Note that the CMD integrity does not have to be correct, since it is not consumed nor
562 // checked further downstream.
563 logic [tlul_pkg::DataIntgWidth-1:0] data_intg;
564
565 tlul_data_integ_enc u_tlul_data_integ_enc (
566 .data_i(combined_data),
567 .data_intg_o({data_intg, unused_data})
568 );
569
570 tl_a_user_t combined_user;
571 always_comb begin
572 1/1 combined_user = held_data.a_user;
Tests: T2 T5 T10
573 1/1 combined_user.data_intg = data_intg;
Tests: T2 T5 T10
574 end
575
576 localparam int unsigned AccessSize = $clog2(top_pkg::TL_DBW);
577 always_comb begin
578 // Pass-through by default
579 1/1 tl_sram_o = tl_i;
Tests: T1 T2 T3
580 // If we're waiting for an internal read for RMW, or a readback read, we force this to 1.
581 1/1 tl_sram_o.d_ready = tl_i.d_ready | rd_wait | rdback_wait;
Tests: T1 T2 T3
582
583 // We take over the TL-UL bus if there is a pending read or write for the RMW transaction.
584 // TL-UL signals are selectively muxed below to reduce complexity and remove long timing
585 // paths through the error_i signal. In particular, we avoid creating paths from error_i
586 // to the address and data output since these may feed into RAM scrambling logic further
587 // downstream.
588
589 // Write transactions for RMW or reads when in readback mode.
590 1/1 if (wr_phase | rdback_phase | rdback_phase_wrreadback) begin
Tests: T1 T2 T3
591 1/1 tl_sram_o.a_valid = 1'b1;
Tests: T2 T5 T10
592 // During a read-modify write, always access the entire word.
593 1/1 tl_sram_o.a_opcode = wr_phase ? PutFullData : Get;
Tests: T2 T5 T10
594 // In either read-modify write or SRAM readback mode, use the mask, size and address
595 // of the original request.
596 1/1 tl_sram_o.a_size =
Tests: T2 T5 T10
597 (wr_phase | rdback_phase_wrreadback) ? top_pkg::TL_SZW'(AccessSize) : held_data.a_size;
598 1/1 tl_sram_o.a_mask =
Tests: T2 T5 T10
599 (wr_phase | rdback_phase_wrreadback) ? '{default: '1} : held_data.a_mask;
600 // override with held / combined data.
601 // need to use word aligned addresses here.
602 1/1 tl_sram_o.a_address = held_data.a_address;
Tests: T2 T5 T10
603 1/1 tl_sram_o.a_address[AccessSize-1:0] =
Tests: T2 T5 T10
604 (wr_phase | rdback_phase_wrreadback) ? '0 : held_data.a_address[AccessSize-1:0];
605 1/1 tl_sram_o.a_source = held_data.a_source;
Tests: T2 T5 T10
606 1/1 tl_sram_o.a_param = held_data.a_param;
Tests: T2 T5 T10
607 1/1 tl_sram_o.a_data = wr_phase ? combined_data : '0;
Tests: T2 T5 T10
608 1/1 tl_sram_o.a_user = wr_phase ? combined_user : '0;
Tests: T2 T5 T10
609 // Read transactions for RMW.
610 1/1 end else if (rd_phase) begin
Tests: T1 T2 T3
611 // need to use word aligned addresses here.
612 1/1 tl_sram_o.a_address[AccessSize-1:0] = '0;
Tests: T5 T10 T7
613 // Only override the control signals if there is no error at the input.
614 1/1 if (!error_i || stall_host) begin
Tests: T5 T10 T7
615 // Since we are performing a read-modify-write operation,
616 // we always access the entire word.
617 1/1 tl_sram_o.a_size = top_pkg::TL_SZW'(AccessSize);
Tests: T5 T10 T7
618 1/1 tl_sram_o.a_mask = '{default: '1};
Tests: T5 T10 T7
619 // use incoming valid as long as we are not stalling the host
620 1/1 tl_sram_o.a_valid = tl_i.a_valid & ~stall_host;
Tests: T5 T10 T7
621 1/1 tl_sram_o.a_opcode = Get;
Tests: T5 T10 T7
622 end
MISSING_ELSE
623 1/1 end else if (wait_phase) begin
Tests: T1 T2 T3
624 // Delay the readback request to avoid that we are reading the holding
625 // register.
626 1/1 tl_sram_o.a_valid = 1'b0;
Tests: T2 T14 T26
627 end
MISSING_ELSE
628 end
629
630 // This assert is necessary for the casting of AccessSize.
631 `ASSERT(TlulSramByteTlSize_A, top_pkg::TL_SZW >= $clog2(AccessSize + 1))
632
633 1/1 assign error_o = error_i & ~stall_host;
Tests: T1 T2 T3
634
635 logic size_fifo_rdy;
636 logic [top_pkg::TL_SZW-1:0] a_size;
637 prim_fifo_sync #(
638 .Width(top_pkg::TL_SZW),
639 .Pass(1'b0),
640 .Depth(Outstanding),
641 .OutputZeroIfEmpty(1'b1)
642 ) u_sync_fifo_a_size (
643 .clk_i,
644 .rst_ni,
645 .clr_i(1'b0),
646 .wvalid_i(a_ack),
647 .wready_o(size_fifo_rdy),
648 .wdata_i(tl_i.a_size),
649 .rvalid_o(),
650 .rready_i(d_ack),
651 .rdata_o(a_size),
652 .full_o(),
653 .depth_o(pending_txn_cnt),
654 .err_o()
655 );
656
657 always_comb begin
658 1/1 tl_o = tl_sram_i;
Tests: T1 T2 T3
659
660 // pass a_ready through directly if we are not stalling
661 1/1 tl_o.a_ready = tl_sram_i.a_ready & ~stall_host & fifo_rdy & size_fifo_rdy;
Tests: T1 T2 T3
662
663 // when internal logic has taken over, do not show response to host during
664 // read phase. During write phase, allow the host to see the completion.
665 1/1 tl_o.d_valid = tl_sram_i.d_valid & ~rd_wait & ~rdback_wait;
Tests: T1 T2 T3
666
667 // the size returned by tl_sram_i does not always correspond to the actual
668 // transaction size in cases where a read modify write operation is
669 // performed. Hence, we always return the registered size here.
670 1/1 tl_o.d_size = a_size;
Tests: T1 T2 T3
671 end // always_comb
672
673 // unused info from tl_sram_i
674 // see explanation in above block
675 logic unused_tl;
676 1/1 assign unused_tl = |tl_sram_i.d_size;
Tests: T1 T2 T3
677
678 // when byte access detected, go to wait read
679 `ASSERT(ByteAccessStateChange_A, a_ack & wr_txn & ~&tl_i.a_mask & ~error_i |=>
680 state_q inside {StWaitRd})
681 // when in wait for read, a successful response should move to write phase
682 `ASSERT(ReadCompleteStateChange_A,
683 (state_q == StWaitRd) && (pending_txn_cnt == 1) && sram_d_ack |=> state_q == StWriteCmd)
684 // The readback logic assumes that any request on the readback channel will be instantly granted
685 // (i.e. after the initial SRAM read or write request from the external requester has been
686 // granted). This helps simplify the logic. It is guaranteed when connected to an SRAM as it
687 // produces no back pressure. When connected to a scrambled SRAM the key going invalid will
688 // cause a_ready to drop. The `compound_txn_in_progress_o` output is provided for this scenario.
689 // When asserted SRAM should not drop `a_ready` even if there is an invalid scrambling key.
690 `ASSERT(ReadbackAccessAlwaysGranted_A, (rdback_phase | rdback_phase_wrreadback) && !error_i
691 |-> tl_sram_i.a_ready)
692
693 // The readback logic assumes the result of a read transaction issues for the readback will get
694 // an immediate response. This can be guaranteed when connected to a SRAM, see above comment.
695 `ASSERT(ReadbackDataImmediatelyAvailable_A, (state_q == StPassThru) &&
696 mubi4_test_true_loose(rdback_en_q) && mubi4_test_true_loose(rdback_check_q) &&
697 !error_i|-> tl_sram_i.d_valid)
698
699 1/1 assign compound_txn_in_progress_o = wr_phase | rdback_phase | rdback_phase_wrreadback;
Tests: T1 T2 T3
700 end else begin : gen_no_integ_handling
701 // In this case we pass everything just through.
702 assign tl_sram_o = tl_i;
703 assign tl_o = tl_sram_i;
704 assign error_o = error_i;
705 assign alert_o = 1'b0;
706 assign compound_txn_in_progress_o = 1'b0;
707
708 // Signal only used in readback mode.
709 mubi4_t unused_readback_en;
710 assign unused_readback_en = readback_en_i;
711
712 end
713
714 // Signals only used for SVA.
715 logic unused_write_pending, unused_wr_collision;
716 1/1 assign unused_write_pending = write_pending_i;
Tests: T1 T2 T3
717 1/1 assign unused_wr_collision = wr_collision_i;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte
| Total | Covered | Percent |
|---|
| Conditions | 94 | 92 | 97.87 |
| Logical | 94 | 92 | 97.87 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 138
EXPRESSION (tl_i.a_valid & tl_o.a_ready)
------1----- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T5,T10 |
| 1 | 1 | Covered | T2,T4,T5 |
LINE 139
EXPRESSION (tl_o.d_valid & tl_i.d_ready)
------1----- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T5,T10 |
| 1 | 1 | Covered | T2,T4,T5 |
LINE 140
EXPRESSION (tl_sram_o.a_valid & tl_sram_i.a_ready)
--------1-------- --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T7,T28,T9 |
| 1 | 1 | Covered | T2,T4,T5 |
LINE 141
EXPRESSION (tl_sram_i.d_valid & tl_sram_o.d_ready)
--------1-------- --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T5,T10 |
| 1 | 1 | Covered | T2,T4,T5 |
LINE 142
EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData))
---------------1-------------- ----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T2,T3,T4 |
| 0 | 1 | Covered | T2,T4,T5 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 142
SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
---------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 142
SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T4,T5 |
LINE 144
EXPRESSION (gen_integ_handling.byte_wr_txn & gen_integ_handling.a_ack & ((~error_i)))
---------------1-------------- ------------2----------- ------3-----
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T2,T4,T5 |
| 1 | 0 | 1 | Covered | T5,T10,T7 |
| 1 | 1 | 0 | Covered | T28,T29,T19 |
| 1 | 1 | 1 | Covered | T5,T10,T7 |
LINE 145
EXPRESSION (tl_i.a_valid & ((~&tl_i.a_mask)) & gen_integ_handling.wr_txn)
------1----- --------2-------- ------------3------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T4,T5 |
| 1 | 1 | 0 | Covered | T5,T10,T7 |
| 1 | 1 | 1 | Covered | T5,T10,T7 |
LINE 156
EXPRESSION (gen_integ_handling.rdback_data_exp_q == tl_sram_i.d_data)
-----------------------------1----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T5,T10 |
LINE 281
EXPRESSION (gen_integ_handling.wr_txn ? StWrReadBackInit : StRdReadBack)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T26,T47,T15 |
| 1 | Covered | T2,T14,T26 |
LINE 297
EXPRESSION (gen_integ_handling.pending_txn_cnt == 2'(1))
----------------------1----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T7,T28,T51 |
| 1 | Covered | T5,T10,T7 |
LINE 330
EXPRESSION (gen_integ_handling.pending_txn_cnt == 2'(1))
----------------------1----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T46,T52,T53 |
| 1 | Covered | T2,T14,T26 |
LINE 395
EXPRESSION (gen_integ_handling.pending_txn_cnt == 2'(1))
----------------------1----------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Covered | T26,T29,T49 |
LINE 459
EXPRESSION (gen_integ_handling.pending_txn_cnt == 2'(1))
----------------------1----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T52,T53 |
| 1 | Covered | T26,T47,T15 |
LINE 517
EXPRESSION (gen_integ_handling.hold_tx_data | gen_integ_handling.byte_req_ack)
---------------1--------------- ---------------2---------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T5,T10,T7 |
| 1 | 0 | Covered | T2,T14,T26 |
LINE 542
EXPRESSION (gen_integ_handling.sram_d_ack && gen_integ_handling.rd_wait)
--------------1-------------- -------------2------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Excluded | |
[UNR] this should not happen because the read latency of prim_ram_1p_scr is always 1 cycle |
| 1 | 0 | Covered | T2,T4,T5 |
| 1 | 1 | Covered | T5,T10,T7 |
LINE 554
EXPRESSION (gen_integ_handling.held_data.a_mask[i] ? gen_integ_handling.held_data.a_data[(i * 8)+:8] : gen_integ_handling.rsp_data[(i * 8)+:8])
-------------------1------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T5,T10,T7 |
| 1 | Covered | T2,T5,T10 |
LINE 581
EXPRESSION (tl_i.d_ready | gen_integ_handling.rd_wait | gen_integ_handling.rdback_wait)
------1----- -------------2------------ ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T2,T14,T26 |
| 0 | 1 | 0 | Covered | T5,T10,T7 |
| 1 | 0 | 0 | Covered | T1,T2,T3 |
LINE 590
EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase | gen_integ_handling.rdback_phase_wrreadback)
-------------1------------- ---------------2--------------- ---------------------3--------------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T26,T29,T49 |
| 0 | 1 | 0 | Covered | T2,T14,T26 |
| 1 | 0 | 0 | Covered | T5,T10,T7 |
LINE 593
EXPRESSION (gen_integ_handling.wr_phase ? PutFullData : Get)
-------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T14,T26 |
| 1 | Covered | T5,T10,T7 |
LINE 596
EXPRESSION
Number Term
1 (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback) ? (2'(gen_integ_handling.AccessSize)) : gen_integ_handling.held_data.a_size)
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T14,T26 |
| 1 | Covered | T5,T10,T7 |
LINE 596
SUB-EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)
-------------1------------- ---------------------2--------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T2,T14,T26 |
| 0 | 1 | Covered | T26,T29,T49 |
| 1 | 0 | Covered | T5,T10,T7 |
LINE 598
EXPRESSION ((gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback) ? ('{(*adjust*)default:'1}) : gen_integ_handling.held_data.a_mask)
-------------------------------------1------------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T14,T26 |
| 1 | Covered | T5,T10,T7 |
LINE 598
SUB-EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)
-------------1------------- ---------------------2--------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T2,T14,T26 |
| 0 | 1 | Covered | T26,T29,T49 |
| 1 | 0 | Covered | T5,T10,T7 |
LINE 603
EXPRESSION
Number Term
1 (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback) ? '0 : gen_integ_handling.held_data.a_address[(gen_integ_handling.AccessSize - 1):0])
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T14,T26 |
| 1 | Covered | T5,T10,T7 |
LINE 603
SUB-EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)
-------------1------------- ---------------------2--------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T2,T14,T26 |
| 0 | 1 | Covered | T26,T29,T49 |
| 1 | 0 | Covered | T5,T10,T7 |
LINE 607
EXPRESSION (gen_integ_handling.wr_phase ? gen_integ_handling.combined_data : '0)
-------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T14,T26 |
| 1 | Covered | T5,T10,T7 |
LINE 608
EXPRESSION (gen_integ_handling.wr_phase ? gen_integ_handling.combined_user : '0)
-------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T14,T26 |
| 1 | Covered | T5,T10,T7 |
LINE 614
EXPRESSION (((!error_i)) || gen_integ_handling.stall_host)
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T28,T29,T19 |
| 0 | 1 | Covered | T5,T10,T7 |
| 1 | 0 | Covered | T5,T10,T7 |
LINE 620
EXPRESSION (tl_i.a_valid & ((~gen_integ_handling.stall_host)))
------1----- -----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T5,T10,T7 |
| 1 | 1 | Covered | T5,T10,T7 |
LINE 633
EXPRESSION (error_i & ((~gen_integ_handling.stall_host)))
---1--- -----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T4,T5 |
| 1 | 0 | Covered | T2,T5,T10 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 661
EXPRESSION (tl_sram_i.a_ready & ((~gen_integ_handling.stall_host)) & gen_integ_handling.fifo_rdy & gen_integ_handling.size_fifo_rdy)
--------1-------- -----------------2---------------- -------------3------------- ----------------4---------------
| -1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T5 |
| 1 | 0 | 1 | 1 | Excluded | T26,T29,T49 |
VC_COV_UNR |
| 1 | 1 | 0 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 665
EXPRESSION (tl_sram_i.d_valid & ((~gen_integ_handling.rd_wait)) & ((~gen_integ_handling.rdback_wait)))
--------1-------- ---------------2--------------- -----------------3-----------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T5,T10,T7 |
| 1 | 1 | 0 | Covered | T2,T14,T26 |
| 1 | 1 | 1 | Covered | T2,T4,T5 |
LINE 699
EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase | gen_integ_handling.rdback_phase_wrreadback)
-------------1------------- ---------------2--------------- ---------------------3--------------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T26,T29,T49 |
| 0 | 1 | 0 | Covered | T2,T14,T26 |
| 1 | 0 | 0 | Covered | T5,T10,T7 |
FSM Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte
Summary for FSM :: gen_integ_handling.state_q
| Total | Covered | Percent | |
| States |
11 |
11 |
100.00 |
(Not included in score) |
| Transitions |
17 |
17 |
100.00 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: gen_integ_handling.state_q
| states | Line No. | Covered | Tests |
| StByteWrReadBack |
403 |
Covered |
T26,T29,T49 |
| StByteWrReadBackDWait |
409 |
Covered |
T26,T50,T46 |
| StByteWrReadBackInit |
310 |
Covered |
T26,T29,T49 |
| StPassThru |
310 |
Covered |
T1,T2,T3 |
| StRdReadBack |
281 |
Covered |
T26,T47,T15 |
| StRdReadBackDWait |
470 |
Covered |
T47,T15,T48 |
| StWaitRd |
274 |
Covered |
T5,T10,T7 |
| StWrReadBack |
340 |
Covered |
T2,T14,T26 |
| StWrReadBackDWait |
343 |
Covered |
T47,T48,T46 |
| StWrReadBackInit |
281 |
Covered |
T2,T14,T26 |
| StWriteCmd |
300 |
Covered |
T5,T10,T7 |
| transitions | Line No. | Covered | Tests |
| StByteWrReadBack->StPassThru |
426 |
Covered |
T26,T29,T49 |
| StByteWrReadBackDWait->StByteWrReadBack |
443 |
Covered |
T26,T50,T46 |
| StByteWrReadBackInit->StByteWrReadBack |
403 |
Covered |
T26,T29,T49 |
| StByteWrReadBackInit->StByteWrReadBackDWait |
409 |
Covered |
T26,T50,T46 |
| StPassThru->StRdReadBack |
281 |
Covered |
T26,T47,T15 |
| StPassThru->StWaitRd |
274 |
Covered |
T5,T10,T7 |
| StPassThru->StWrReadBackInit |
281 |
Covered |
T2,T14,T26 |
| StRdReadBack->StPassThru |
463 |
Covered |
T26,T47,T15 |
| StRdReadBack->StRdReadBackDWait |
470 |
Covered |
T47,T15,T48 |
| StRdReadBackDWait->StPassThru |
486 |
Covered |
T47,T15,T48 |
| StWaitRd->StWriteCmd |
300 |
Covered |
T5,T10,T7 |
| StWrReadBack->StPassThru |
359 |
Covered |
T2,T14,T26 |
| StWrReadBackDWait->StWrReadBack |
378 |
Covered |
T47,T48,T46 |
| StWrReadBackInit->StWrReadBack |
340 |
Covered |
T2,T14,T26 |
| StWrReadBackInit->StWrReadBackDWait |
343 |
Covered |
T47,T48,T46 |
| StWriteCmd->StByteWrReadBackInit |
310 |
Covered |
T26,T29,T49 |
| StWriteCmd->StPassThru |
310 |
Covered |
T5,T10,T7 |
Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte
| Line No. | Total | Covered | Percent |
| Branches |
|
61 |
57 |
93.44 |
| IF |
105 |
2 |
2 |
100.00 |
| CASE |
255 |
39 |
35 |
89.74 |
| IF |
542 |
2 |
2 |
100.00 |
| TERNARY |
554 |
2 |
2 |
100.00 |
| IF |
590 |
16 |
16 |
100.00 |
105 if (!rst_ni) begin
-1-
106 state_q <= StPassThru;
==>
107 end else begin
108 state_q <= state_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
255 unique case (state_q)
-1-
256 StPassThru: begin
257 if (mubi4_test_true_loose(rdback_en_q) && mubi4_test_true_loose(rdback_check_q)) begin
-2-
258 // When we're expecting a readback check that means we'll see a data response from the
259 // SRAM this cycle which we need to check against the readback registers. During this
260 // cycle the data response out (via tl_o) will be squashed to invalid but we can accept
261 // a new transaction (via tl_i).
262 rdback_wait = 1'b1;
263 rdback_check_d = MuBi4False;
264
265 // Perform the readback check.
266 if (!rdback_chk_ok) begin
-3-
267 alert_o = 1'b1;
==>
268 end
MISSING_ELSE
==>
269 end
MISSING_ELSE
==>
270
271 if (byte_wr_txn) begin
-4-
272 rd_phase = 1'b1;
273 if (byte_req_ack) begin
-5-
274 state_d = StWaitRd;
==>
275 end
MISSING_ELSE
==>
276 end else if (a_ack && mubi4_test_true_loose(rdback_en_q) && !error_i) begin
-6-
277 // For reads and full word writes we'll first do the transaction and then do a readback
278 // check. Setting `hold_tx_data` here will preserve the transaction information in
279 // u_sync_fifo for doing the readback transaction.
280 hold_tx_data = 1'b1;
281 state_d = wr_txn ? StWrReadBackInit : StRdReadBack;
-7-
==>
==>
282 end
MISSING_ELSE
==>
283
284 if (!tl_sram_o.a_valid && !tl_o.d_valid &&
-8-
285 mubi4_test_false_strict(rdback_check_q)) begin
286 // Store readback enable into register when bus is idle and no readback is processed.
287 rdback_en_d = readback_en_i;
==>
288 end
MISSING_ELSE
==>
289 end
290
291 // Due to the way things are serialized, there is no way for the logic to tell which read
292 // belongs to the partial read unless it flushes all prior transactions. Hence, we wait
293 // here until exactly one outstanding transaction remains (that one is the partial read).
294 StWaitRd: begin
295 rd_phase = 1'b1;
296 stall_host = 1'b1;
297 if (pending_txn_cnt == PendingTxnCntW'(1)) begin
-9-
298 rd_wait = 1'b1;
299 if (sram_d_ack) begin
-10-
300 state_d = StWriteCmd;
==>
301 end
MISSING_ELSE
==>
302 end
MISSING_ELSE
==>
303 end
304
305 StWriteCmd: begin
306 stall_host = 1'b1;
307 wr_phase = 1'b1;
308
309 if (sram_a_ack) begin
-11-
310 state_d = mubi4_test_true_loose(rdback_en_q) ? StByteWrReadBackInit : StPassThru;
==>
311 rdback_check_d = mubi4_test_true_loose(rdback_en_q) ? MuBi4True : MuBi4False;
312 rdback_data_exp_d = tl_sram_o.a_data;
313 rdback_data_exp_intg_d = tl_sram_o.a_user.data_intg;
314 end
MISSING_ELSE
==>
315 end
316
317 StWrReadBackInit: begin
318 // Perform readback after full write. To avoid that we read the holding register
319 // in the readback, wait until the write was processed by the memory module.
320 if (EnableReadback == 0) begin : gen_inv_state_StWrReadBackInit
-12-
321 // If readback is disabled, we shouldn't be in this state.
322 alert_o = 1'b1;
==> (Unreachable)
323 end
MISSING_ELSE
==>
324
325 // Stall the host to perform the readback in the next cycle.
326 stall_host = 1'b1;
327
328 // Need to ensure there's no other transactions in flight before we do the readback (the
329 // initial write we're doing the readback for should be the only one active).
330 if (pending_txn_cnt == PendingTxnCntW'(1)) begin
-13-
331 wait_phase = 1'b1;
332 // Data we're checking against the readback is captured from the write transaction that
333 // was sent.
334 rdback_check_d = mubi4_test_true_loose(rdback_en_q) ? MuBi4True : MuBi4False;
335 rdback_data_exp_d = held_data.a_data;
336 rdback_data_exp_intg_d = held_data.a_user.data_intg;
337 if (d_ack) begin
-14-
338 // Got an immediate TL-UL write response. Wait for one cycle until the holding
339 // register is flushed and then perform the readback.
340 state_d = StWrReadBack;
==>
341 end else begin
342 // No response yet to the initial write.
343 state_d = StWrReadBackDWait;
==>
344 end
345 end
MISSING_ELSE
==>
346 end
347
348 StWrReadBack: begin
349 // Perform readback and check response in StPassThru.
350 if (EnableReadback == 0) begin : gen_inv_state_StWrReadBack
-15-
351 // If readback is disabled, we shouldn't be in this state.
352 alert_o = 1'b1;
==> (Unreachable)
353 end
MISSING_ELSE
==>
354
355 stall_host = 1'b1;
356
357 rdback_phase = 1'b1;
358
359 state_d = StPassThru;
360 end
361
362 StWrReadBackDWait: begin
363 // We have not received the d_valid response of the initial write. Wait
364 // for the valid signal.
365 if (EnableReadback == 0) begin : gen_inv_state_StWrReadBackDWait
-16-
366 // If readback is disabled, we shouldn't be in this state.
367 alert_o = 1'b1;
==> (Unreachable)
368 end
MISSING_ELSE
==>
369
370 // Wait until we get write response.
371 wait_phase = 1'b1;
372
373 stall_host = 1'b1;
374
375 if (d_ack) begin
-17-
376 // Got the TL-UL write response. Wait for one cycle until the holding
377 // register is flushed and then perform the readback.
378 state_d = StWrReadBack;
==>
379 end
MISSING_ELSE
==>
380 end
381
382 StByteWrReadBackInit: begin
383 // Perform readback after partial write. To avoid that we read the holding register
384 // in the readback, do the actual readback check in the next FSM state.
385 if (EnableReadback == 0) begin : gen_inv_state_StByteWrReadBackInit
-18-
386 // If readback is disabled, we shouldn't be in this state.
387 alert_o = 1'b1;
==> (Unreachable)
388 end
MISSING_ELSE
==>
389
390 // Sends out a read to a readback check on a partial write. The host is stalled whilst
391 // this is happening.
392 stall_host = 1'b1;
393
394 // Wait until there is a single ongoing transaction.
395 if (pending_txn_cnt == PendingTxnCntW'(1)) begin
-19-
396 // Wait for one cycle with sending readback request to SRAM to avoid reading from
397 // holding register.
398 wait_phase = 1'b1;
399
400 if (d_ack) begin
-20-
401 // Got an immediate TL-UL write response. Wait for one cycle until the holding
402 // register is flushed and then perform the readback.
403 state_d = StByteWrReadBack;
==>
404 end else begin
405 // No response received for initial write. We already can send the
406 // request for the readback in the next cycle but we need to wait
407 // for the response for the initial write before doing the readback
408 // check.
409 state_d = StByteWrReadBackDWait;
==>
410 end
411 end
MISSING_ELSE
==>
412 end
413
414 StByteWrReadBack: begin
415 // Wait until the memory module has completed the partial write.
416 // Perform readback and check response in StPassThru.
417 if (EnableReadback == 0) begin : gen_inv_state_StByteWrReadBack
-21-
418 // If readback is disabled, we shouldn't be in this state.
419 alert_o = 1'b1;
==> (Unreachable)
420 end
MISSING_ELSE
==>
421
422 stall_host = 1'b1;
423
424 rdback_phase_wrreadback = 1'b1;
425
426 state_d = StPassThru;
427 end
428
429 StByteWrReadBackDWait: begin
430 if (EnableReadback == 0) begin : gen_inv_state_StByteWrReadBackDWait
-22-
431 // If readback is disabled, we shouldn't be in this state.
432 alert_o = 1'b1;
==> (Unreachable)
433 end
MISSING_ELSE
==>
434
435 stall_host = 1'b1;
436
437 // Wait for one cycle with sending readback request to SRAM.
438 wait_phase = 1'b1;
439
440 if (d_ack) begin
-23-
441 // Got the TL-UL write response. Wait for one cycle until the holding
442 // register is flushed and then perform the readback.
443 state_d = StByteWrReadBack;
==>
444 end
MISSING_ELSE
==>
445 end
446
447 StRdReadBack: begin
448 if (EnableReadback == 0) begin : gen_inv_state_StRdReadBack
-24-
449 // If readback is disabled, we shouldn't be in this state.
450 alert_o = 1'b1;
==> (Unreachable)
451 end
MISSING_ELSE
==>
452
453 // Sends out a read to a readback check on a read. The host is stalled whilst
454 // this is happening.
455 stall_host = 1'b1;
456
457 // Need to ensure there's no other transactions in flight before we do the readback (the
458 // read we're doing the readback for should be the only one active).
459 if (pending_txn_cnt == PendingTxnCntW'(1)) begin
-25-
460 rdback_phase = 1'b1;
461
462 if (d_ack) begin
-26-
463 state_d = StPassThru;
==>
464 // Data for the readback check comes from the first read.
465 rdback_check_d = mubi4_test_true_loose(rdback_en_q) ? MuBi4True : MuBi4False;
466 rdback_data_exp_d = tl_o.d_data;
467 rdback_data_exp_intg_d = tl_o.d_user.data_intg;
468 end else begin
469 // No response yet to the initial read, so go wait for it.
470 state_d = StRdReadBackDWait;
==>
471 end
472 end
MISSING_ELSE
==>
473 end
474
475 StRdReadBackDWait : begin
476 if (EnableReadback == 0) begin : gen_inv_state_StRdReadBackDWait
-27-
477 // If readback is disabled, we shouldn't be in this state.
478 alert_o = 1'b1;
==> (Unreachable)
479 end
MISSING_ELSE
==>
480
481 stall_host = 1'b1;
482
483 if (d_ack) begin
-28-
484 // Response received for first read. Now need to await data for the readback check
485 // which is done in the `StPassThru` state.
486 state_d = StPassThru;
==>
487 // Data for the readback check comes from the first read.
488 rdback_check_d = mubi4_test_true_loose(rdback_en_q) ? MuBi4True : MuBi4False;
489 rdback_data_exp_d = tl_o.d_data;
490 rdback_data_exp_intg_d = tl_o.d_user.data_intg;
491 end
MISSING_ELSE
==>
492 end
493
494 default: begin
495 alert_o = 1'b1;
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | -14- | -15- | -16- | -17- | -18- | -19- | -20- | -21- | -22- | -23- | -24- | -25- | -26- | -27- | -28- | Status | Tests |
| StPassThru |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T14,T15 |
| StPassThru |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T14,T26 |
| StPassThru |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| StPassThru |
- |
- |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T5,T10,T7 |
| StPassThru |
- |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T7,T28,T51 |
| StPassThru |
- |
- |
0 |
- |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T14,T26 |
| StPassThru |
- |
- |
0 |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T26,T47,T15 |
| StPassThru |
- |
- |
0 |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| StPassThru |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| StPassThru |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T4,T5 |
| StWaitRd |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T5,T10,T7 |
| StWaitRd |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
| StWaitRd |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T7,T28,T51 |
| StWriteCmd |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T5,T10,T7 |
| StWriteCmd |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
| StWrReadBackInit |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
|
| StWrReadBackInit |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T14,T26 |
| StWrReadBackInit |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T14,T26 |
| StWrReadBackInit |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T14,T26 |
| StWrReadBackInit |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T46,T52,T53 |
| StWrReadBack |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
|
| StWrReadBack |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T14,T26 |
| StWrReadBackDWait |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
|
| StWrReadBackDWait |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T47,T48,T46 |
| StWrReadBackDWait |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T47,T48,T46 |
| StWrReadBackDWait |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T47,T48,T46 |
| StByteWrReadBackInit |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
|
| StByteWrReadBackInit |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T26,T29,T49 |
| StByteWrReadBackInit |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T26,T29,T49 |
| StByteWrReadBackInit |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T26,T49,T50 |
| StByteWrReadBackInit |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
| StByteWrReadBack |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
|
| StByteWrReadBack |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T26,T29,T49 |
| StByteWrReadBackDWait |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
Unreachable |
|
| StByteWrReadBackDWait |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T26,T50,T46 |
| StByteWrReadBackDWait |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T26,T50,T46 |
| StByteWrReadBackDWait |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
Covered |
T26,T50,T46 |
| StRdReadBack |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
Unreachable |
|
| StRdReadBack |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
Covered |
T26,T47,T15 |
| StRdReadBack |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
- |
- |
Covered |
T26,T47,T15 |
| StRdReadBack |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
Covered |
T26,T47,T15 |
| StRdReadBack |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
Covered |
T52,T53 |
| StRdReadBackDWait |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
Unreachable |
|
| StRdReadBackDWait |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
Covered |
T47,T15,T48 |
| StRdReadBackDWait |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T47,T15,T48 |
| StRdReadBackDWait |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T47,T15,T48 |
| default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
542 if (sram_d_ack && rd_wait) begin
-1-
543 rsp_data <= tl_sram_i.d_data;
==>
544 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T10,T7 |
| 0 |
Covered |
T1,T2,T3 |
554 combined_data[i*8 +: 8] = held_data.a_mask[i] ?
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T5,T10 |
| 0 |
Covered |
T5,T10,T7 |
590 if (wr_phase | rdback_phase | rdback_phase_wrreadback) begin
-1-
591 tl_sram_o.a_valid = 1'b1;
592 // During a read-modify write, always access the entire word.
593 tl_sram_o.a_opcode = wr_phase ? PutFullData : Get;
-2-
==>
==>
594 // In either read-modify write or SRAM readback mode, use the mask, size and address
595 // of the original request.
596 tl_sram_o.a_size =
597 (wr_phase | rdback_phase_wrreadback) ? top_pkg::TL_SZW'(AccessSize) : held_data.a_size;
-3-
==>
==>
598 tl_sram_o.a_mask =
599 (wr_phase | rdback_phase_wrreadback) ? '{default: '1} : held_data.a_mask;
-4-
==>
==>
600 // override with held / combined data.
601 // need to use word aligned addresses here.
602 tl_sram_o.a_address = held_data.a_address;
603 tl_sram_o.a_address[AccessSize-1:0] =
604 (wr_phase | rdback_phase_wrreadback) ? '0 : held_data.a_address[AccessSize-1:0];
-5-
==>
==>
605 tl_sram_o.a_source = held_data.a_source;
606 tl_sram_o.a_param = held_data.a_param;
607 tl_sram_o.a_data = wr_phase ? combined_data : '0;
-6-
==>
==>
608 tl_sram_o.a_user = wr_phase ? combined_user : '0;
-7-
==>
==>
609 // Read transactions for RMW.
610 end else if (rd_phase) begin
-8-
611 // need to use word aligned addresses here.
612 tl_sram_o.a_address[AccessSize-1:0] = '0;
613 // Only override the control signals if there is no error at the input.
614 if (!error_i || stall_host) begin
-9-
615 // Since we are performing a read-modify-write operation,
616 // we always access the entire word.
617 tl_sram_o.a_size = top_pkg::TL_SZW'(AccessSize);
==>
618 tl_sram_o.a_mask = '{default: '1};
619 // use incoming valid as long as we are not stalling the host
620 tl_sram_o.a_valid = tl_i.a_valid & ~stall_host;
621 tl_sram_o.a_opcode = Get;
622 end
MISSING_ELSE
==>
623 end else if (wait_phase) begin
-10-
624 // Delay the readback request to avoid that we are reading the holding
625 // register.
626 tl_sram_o.a_valid = 1'b0;
==>
627 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | Status | Tests |
| 1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T5,T10,T7 |
| 1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T14,T26 |
| 1 |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T5,T10,T7 |
| 1 |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T14,T26 |
| 1 |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T5,T10,T7 |
| 1 |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T2,T14,T26 |
| 1 |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T5,T10,T7 |
| 1 |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
Covered |
T2,T14,T26 |
| 1 |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
Covered |
T5,T10,T7 |
| 1 |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
Covered |
T2,T14,T26 |
| 1 |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
Covered |
T5,T10,T7 |
| 1 |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
Covered |
T2,T14,T26 |
| 0 |
- |
- |
- |
- |
- |
- |
1 |
1 |
- |
Covered |
T5,T10,T7 |
| 0 |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
Covered |
T28,T29,T19 |
| 0 |
- |
- |
- |
- |
- |
- |
0 |
- |
1 |
Covered |
T2,T14,T26 |
| 0 |
- |
- |
- |
- |
- |
- |
0 |
- |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte
Assertion Details
SramReadbackAndIntg
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
944 |
944 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
gen_integ_handling.ByteAccessStateChange_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
339860600 |
6207205 |
0 |
0 |
| T5 |
6298 |
1025 |
0 |
0 |
| T6 |
38390 |
0 |
0 |
0 |
| T7 |
69128 |
5 |
0 |
0 |
| T8 |
17872 |
22 |
0 |
0 |
| T10 |
47016 |
269 |
0 |
0 |
| T11 |
7027 |
306 |
0 |
0 |
| T25 |
23722 |
466 |
0 |
0 |
| T26 |
0 |
1010 |
0 |
0 |
| T27 |
2751 |
0 |
0 |
0 |
| T28 |
0 |
425 |
0 |
0 |
| T32 |
16294 |
1902 |
0 |
0 |
| T36 |
8639 |
0 |
0 |
0 |
| T40 |
0 |
547 |
0 |
0 |
gen_integ_handling.ReadCompleteStateChange_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
339860600 |
6207205 |
0 |
0 |
| T5 |
6298 |
1025 |
0 |
0 |
| T6 |
38390 |
0 |
0 |
0 |
| T7 |
69128 |
5 |
0 |
0 |
| T8 |
17872 |
22 |
0 |
0 |
| T10 |
47016 |
269 |
0 |
0 |
| T11 |
7027 |
306 |
0 |
0 |
| T25 |
23722 |
466 |
0 |
0 |
| T26 |
0 |
1010 |
0 |
0 |
| T27 |
2751 |
0 |
0 |
0 |
| T28 |
0 |
425 |
0 |
0 |
| T32 |
16294 |
1902 |
0 |
0 |
| T36 |
8639 |
0 |
0 |
0 |
| T40 |
0 |
547 |
0 |
0 |
gen_integ_handling.ReadbackAccessAlwaysGranted_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
339860600 |
188964 |
0 |
0 |
| T12 |
859 |
0 |
0 |
0 |
| T16 |
14412 |
0 |
0 |
0 |
| T18 |
219341 |
0 |
0 |
0 |
| T26 |
17939 |
817 |
0 |
0 |
| T28 |
128791 |
0 |
0 |
0 |
| T29 |
0 |
4736 |
0 |
0 |
| T40 |
10524 |
0 |
0 |
0 |
| T47 |
0 |
44 |
0 |
0 |
| T48 |
0 |
197 |
0 |
0 |
| T49 |
0 |
889 |
0 |
0 |
| T54 |
0 |
4094 |
0 |
0 |
| T55 |
0 |
77 |
0 |
0 |
| T56 |
0 |
25088 |
0 |
0 |
| T57 |
0 |
874 |
0 |
0 |
| T58 |
0 |
4094 |
0 |
0 |
| T59 |
170358 |
0 |
0 |
0 |
| T60 |
11556 |
0 |
0 |
0 |
| T61 |
9322 |
0 |
0 |
0 |
| T62 |
4470 |
0 |
0 |
0 |
gen_integ_handling.ReadbackDataImmediatelyAvailable_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
339860600 |
254076 |
0 |
0 |
| T12 |
859 |
0 |
0 |
0 |
| T16 |
14412 |
0 |
0 |
0 |
| T18 |
219341 |
0 |
0 |
0 |
| T26 |
17939 |
933 |
0 |
0 |
| T28 |
128791 |
0 |
0 |
0 |
| T29 |
0 |
4519 |
0 |
0 |
| T40 |
10524 |
0 |
0 |
0 |
| T47 |
0 |
119 |
0 |
0 |
| T48 |
0 |
495 |
0 |
0 |
| T49 |
0 |
869 |
0 |
0 |
| T54 |
0 |
6141 |
0 |
0 |
| T55 |
0 |
225 |
0 |
0 |
| T56 |
0 |
26259 |
0 |
0 |
| T57 |
0 |
871 |
0 |
0 |
| T58 |
0 |
6141 |
0 |
0 |
| T59 |
170358 |
0 |
0 |
0 |
| T60 |
11556 |
0 |
0 |
0 |
| T61 |
9322 |
0 |
0 |
0 |
| T62 |
4470 |
0 |
0 |
0 |
gen_integ_handling.TlulSramByteTlSize_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
339860600 |
339753777 |
0 |
0 |
| T1 |
2648 |
2571 |
0 |
0 |
| T2 |
1170 |
1095 |
0 |
0 |
| T3 |
1447 |
1386 |
0 |
0 |
| T4 |
7305 |
7253 |
0 |
0 |
| T5 |
6298 |
6233 |
0 |
0 |
| T6 |
38390 |
33020 |
0 |
0 |
| T7 |
69128 |
68910 |
0 |
0 |
| T8 |
17872 |
17733 |
0 |
0 |
| T10 |
47016 |
46956 |
0 |
0 |
| T11 |
7027 |
6955 |
0 |
0 |
gen_integ_handling.gen_readback_logic.NoPendingWriteAfterWrite_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
339860600 |
22665 |
0 |
0 |
| T12 |
859 |
0 |
0 |
0 |
| T16 |
14412 |
0 |
0 |
0 |
| T18 |
219341 |
0 |
0 |
0 |
| T26 |
17939 |
1010 |
0 |
0 |
| T28 |
128791 |
0 |
0 |
0 |
| T29 |
0 |
216 |
0 |
0 |
| T40 |
10524 |
0 |
0 |
0 |
| T46 |
0 |
1 |
0 |
0 |
| T49 |
0 |
525 |
0 |
0 |
| T50 |
0 |
222 |
0 |
0 |
| T56 |
0 |
1153 |
0 |
0 |
| T57 |
0 |
518 |
0 |
0 |
| T59 |
170358 |
0 |
0 |
0 |
| T60 |
11556 |
0 |
0 |
0 |
| T61 |
9322 |
0 |
0 |
0 |
| T62 |
4470 |
0 |
0 |
0 |
| T63 |
0 |
544 |
0 |
0 |
| T64 |
0 |
316 |
0 |
0 |
| T65 |
0 |
562 |
0 |
0 |
gen_integ_handling.gen_readback_logic.WRCollisionDuringReadBack_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
339860600 |
363704 |
0 |
0 |
| T12 |
859 |
0 |
0 |
0 |
| T16 |
14412 |
0 |
0 |
0 |
| T18 |
219341 |
0 |
0 |
0 |
| T26 |
17939 |
1968 |
0 |
0 |
| T28 |
128791 |
0 |
0 |
0 |
| T29 |
0 |
4830 |
0 |
0 |
| T40 |
10524 |
0 |
0 |
0 |
| T47 |
0 |
827 |
0 |
0 |
| T48 |
0 |
3253 |
0 |
0 |
| T49 |
0 |
941 |
0 |
0 |
| T54 |
0 |
6142 |
0 |
0 |
| T55 |
0 |
1361 |
0 |
0 |
| T56 |
0 |
26984 |
0 |
0 |
| T57 |
0 |
935 |
0 |
0 |
| T58 |
0 |
6142 |
0 |
0 |
| T59 |
170358 |
0 |
0 |
0 |
| T60 |
11556 |
0 |
0 |
0 |
| T61 |
9322 |
0 |
0 |
0 |
| T62 |
4470 |
0 |
0 |
0 |