Unified Coverage Report :: Module :: sysrst_ctrl

Module : sysrst_ctrl_keyintr

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_keyintr.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sysrst_ctrl_keyintr	100.00	100.00	100.00

Module Instance : tb.dut.u_sysrst_ctrl_keyintr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.67	97.85	93.27		92.86	97.14	97.24

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.34	100.00	96.72	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_keyfsm[0].u_sysrst_ctrl_detect_h2l	99.05	100.00	95.24		100.00	100.00	100.00
gen_keyfsm[0].u_sysrst_ctrl_detect_l2h	91.56	95.65	90.48		83.33	95.00	93.33
gen_keyfsm[1].u_sysrst_ctrl_detect_h2l	99.05	100.00	95.24		100.00	100.00	100.00
gen_keyfsm[1].u_sysrst_ctrl_detect_l2h	91.56	95.65	90.48		83.33	95.00	93.33
gen_keyfsm[2].u_sysrst_ctrl_detect_h2l	91.64	95.65	90.48		83.33	95.00	93.75
gen_keyfsm[2].u_sysrst_ctrl_detect_l2h	91.56	95.65	90.48		83.33	95.00	93.33
gen_keyfsm[3].u_sysrst_ctrl_detect_h2l	91.64	95.65	90.48		83.33	95.00	93.75
gen_keyfsm[3].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
gen_keyfsm[4].u_sysrst_ctrl_detect_h2l	99.05	100.00	95.24		100.00	100.00	100.00
gen_keyfsm[4].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
gen_keyfsm[5].u_sysrst_ctrl_detect_h2l	97.61	97.83	95.24		100.00	95.00	100.00
gen_keyfsm[5].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
gen_keyfsm[6].u_sysrst_ctrl_detect_h2l	90.21	93.48	90.48		83.33	90.00	93.75
gen_keyfsm[6].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : sysrst_ctrl_keyintr

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	31	1	1	100.00
CONT_ASSIGN	40	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	118	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_keyintr.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_keyintr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
40	1	1
49	1	1
101	1	1
109	1	1
118	1	1

Cond Coverage for Module : sysrst_ctrl_keyintr

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       118
 EXPRESSION (((|l2h_met_pulse)) || ((|h2l_met_pulse)))
             ---------1--------    ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T34,T35,T36
0	1	Covered	T12,T16,T17
1	0	Covered	T12,T16,T17