Unified Coverage Report :: Module :: sysrst_ctrl_detect

Module : sysrst_ctrl_detect

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.35	100.00	96.30		100.00	95.45	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l	90.21	93.48	90.48		83.33	90.00	93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h	91.56	95.65	90.48		83.33	95.00	93.33
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h	91.56	95.65	90.48		83.33	95.00	93.33
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h	91.56	95.65	90.48		83.33	95.00	93.33
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l	91.64	95.65	90.48		83.33	95.00	93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l	91.64	95.65	90.48		83.33	95.00	93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l	97.61	97.83	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb	98.89	100.00	94.44		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open	98.89	100.00	94.44		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	LINE
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	LINE
91.64	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	LINE
91.64	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	LINE
97.61	97.83

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	LINE
90.21	93.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

SCORE	LINE
91.56	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	LINE
91.56	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	LINE
91.56	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.67	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T34,T35,T36

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T34,T35,T36

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T36,T13,T15

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T36,T13,T15

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T13,T15,T29

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T35,T36,T13
1	0	Covered	T34,T35,T36
1	1	Covered	T36,T13,T15

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T15,T29
0	1	Covered	T15,T21,T52
1	0	Covered	T67,T68

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T15,T29
0	1	Covered	T13,T15,T20
1	0	Covered	T67,T68

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T15,T29
1	-	Covered	T13,T15,T20

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	COND
91.64	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	COND
91.64	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	COND
97.61	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	COND
90.21	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T34,T35,T36

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T34,T35,T36

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T69,T12,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T69,T12,T25

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T69,T12,T25

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T36,T69,T12
1	0	Covered	T34,T35,T36
1	1	Covered	T69,T12,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T69,T12,T25
0	1	Covered	T50,T48,T70
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T69,T12,T25
0	1	Covered	T69,T12,T25
1	0	Covered	T68

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T69,T12,T25
1	-	Covered	T69,T12,T25

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T34,T35,T27
1	Covered	T34,T35,T36

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T34,T35,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T34,T35,T27

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T34,T35,T27

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T27
1	0	Covered	T29,T20,T44
1	1	Covered	T34,T35,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T34,T35,T27
0	1	Covered	T34,T27,T29
1	0	Covered	T44,T53,T71

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T35,T29,T20
0	1	Covered	T35,T29,T20
1	0	Covered	T72,T73,T74

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T35,T29,T20
1	-	Covered	T35,T29,T20

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.67	93.33

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	16	15	93.75
Logical	16	15	93.75
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T34,T35,T36

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T14,T17,T18

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T14,T17,T18

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T14,T19,T59

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T17,T18
1	0	Covered	T34,T35,T36
1	1	Covered	T14,T17,T18

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T19,T59
0	1	Covered	T75,T76,T77
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T19,T59
0	1	Unreachable
1	0	Covered	T14,T19,T59

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
91.56	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	COND
91.56	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	COND
91.56	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T34,T35,T36

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T34,T35,T36

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T12,T16,T17

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T12,T16,T17

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T12,T16,T17

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T16,T17
1	0	Covered	T34,T35,T36
1	1	Covered	T12,T16,T17

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T16,T17
0	1	Covered	T17,T49,T78
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T16,T17
0	1	Covered	T12,T17,T51
1	0	Covered	T68

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T16,T17
1	-	Covered	T12,T17,T51

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.89	94.44

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T36,T12,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T36,T12,T13
1	1	Covered	T36,T12,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T14,T17,T18

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T14,T17,T18

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T17,T19,T59

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T17,T18
1	0	Covered	T36,T12,T13
1	1	Covered	T14,T17,T18

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T17,T19,T50
0	1	Covered	T59,T48,T79
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T19,T50
0	1	Unreachable
1	0	Covered	T17,T19,T50

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.89	94.44

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T34,T35,T36

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T34,T35,T36

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T14,T17,T18

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T14,T17,T18

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T14,T17,T18

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T17,T18
1	0	Covered	T34,T35,T36
1	1	Covered	T14,T17,T18

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T17,T18
0	1	Covered	T61,T80,T81
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T17,T18
0	1	Unreachable
1	0	Covered	T14,T17,T18

---

FSM Coverage for Module : sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
91.64	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
91.64	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
97.61	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
90.21	90.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCORE	BRANCH
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

SCORE	BRANCH
91.56	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
91.56	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
91.56	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		23	22	95.65
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T69,T12,T25
0	1	Covered	T69,T12,T25
0	0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T69,T12,T25
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T69,T12,T25
IdleSt	0	-	-	-	-	-	-	Covered	T34,T35,T36
DebounceSt	-	1	-	-	-	-	-	Covered	T67,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T69,T12,T25
DebounceSt	-	0	1	0	-	-	-	Covered	T25,T50,T61
DebounceSt	-	0	0	-	-	-	-	Covered	T69,T12,T25
DetectSt	-	-	-	-	1	-	-	Covered	T59,T50,T61
DetectSt	-	-	-	-	0	1	-	Covered	T69,T12,T25
DetectSt	-	-	-	-	0	0	-	Covered	T13,T15,T29
StableSt	-	-	-	-	-	-	1	Covered	T69,T12,T25
StableSt	-	-	-	-	-	-	0	Covered	T69,T12,T25
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

---

Branch Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
98.67	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T34,T35,T27
0	1	Covered	T34,T35,T27
0	0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T27
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T34,T35,T27
IdleSt	0	-	-	-	-	-	-	Covered	T34,T35,T36
DebounceSt	-	1	-	-	-	-	-	Covered	T67,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T34,T35,T27
DebounceSt	-	0	1	0	-	-	-	Covered	T35,T17,T18
DebounceSt	-	0	0	-	-	-	-	Covered	T34,T35,T27
DetectSt	-	-	-	-	1	-	-	Covered	T34,T27,T82
DetectSt	-	-	-	-	0	1	-	Covered	T35,T14,T29
DetectSt	-	-	-	-	0	0	-	Covered	T34,T35,T27
StableSt	-	-	-	-	-	-	1	Covered	T35,T14,T29
StableSt	-	-	-	-	-	-	0	Covered	T35,T14,T29
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

---

Assert Coverage for Module : sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	206572444	17358	0	0
CntIncr_A	206572444	2549503	0	0
CntNoWrap_A	206572444	189229622	0	0
DetectStDropOut_A	206572444	2273	0	0
DetectedOut_A	206572444	1173093	0	0
DetectedPulseOut_A	206572444	5497	0	0
DisabledIdleSt_A	206572444	179654745	0	0
DisabledNoDetection_A	206572444	179711809	0	0
EnterDebounceSt_A	206572444	9012	0	0
EnterDetectSt_A	206572444	8381	0	0
EnterStableSt_A	206572444	5497	0	0
PulseIsPulse_A	206572444	5497	0	0
StayInStableSt	206572444	1166801	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	71505846	52026	0	0
gen_high_event_sva.HighLevelEvent_A	39725470	36405435	0	0
gen_high_level_sva.HighLevelEvent_A	135066598	123778479	0	0
gen_low_level_sva.LowLevelEvent_A	71505846	65529783	0	0
gen_not_sticky_sva.StableStDropOut_A	182737162	4498	0	0
gen_sticky_sva.StableStDropOut_A	23835282	778900	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206572444	17358	0	0
T12	16730	2	0	0
T13	83132	2	0	0
T14	4752	0	0	0
T15	52352	7	0	0
T16	488	0	0	0
T17	114965	0	0	0
T18	2225	0	0	0
T20	29027	66	0	0
T21	0	8	0	0
T24	3682	0	0	0
T25	5005	3	0	0
T26	4746	2	0	0
T27	31955	0	0	0
T28	1644	0	0	0
T29	75522	64	0	0
T34	16263	32	0	0
T35	37245	0	0	0
T36	13968	1	0	0
T39	0	2	0	0
T44	0	24	0	0
T50	0	1	0	0
T52	0	5	0	0
T54	0	2	0	0
T56	1206	0	0	0
T57	422	0	0	0
T58	615	0	0	0
T69	3485	2	0	0
T83	0	6	0	0
T84	0	4	0	0
T85	0	4	0	0
T86	0	4	0	0
T87	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206572444	2549503	0	0
T12	16730	100	0	0
T13	83132	91	0	0
T14	4752	0	0	0
T15	52352	587	0	0
T16	488	0	0	0
T17	114965	0	0	0
T18	2225	0	0	0
T20	29027	2718	0	0
T21	0	472	0	0
T24	3682	0	0	0
T25	5005	183	0	0
T26	4746	84	0	0
T27	31955	0	0	0
T28	1644	0	0	0
T29	75522	2392	0	0
T34	16263	888	0	0
T35	37245	0	0	0
T36	13968	20	0	0
T39	0	25	0	0
T44	0	500	0	0
T50	0	20	0	0
T52	0	135	0	0
T54	0	68	0	0
T56	1206	0	0	0
T57	422	0	0	0
T58	615	0	0	0
T69	3485	71	0	0
T83	0	190	0	0
T84	0	100	0	0
T85	0	173	0	0
T86	0	134	0	0
T87	0	58217	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206572444	189229622	0	0
T12	86996	34852	0	0
T13	308776	245972	0	0
T24	13676	3250	0	0
T25	18590	8161	0	0
T26	17628	7200	0	0
T27	118690	108173	0	0
T34	140946	130400	0	0
T35	322790	312269	0	0
T36	90792	11803	0	0
T69	18122	7694	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206572444	2273	0	0
T27	0	5	0	0
T34	5421	16	0	0
T43	23062	3	0	0
T45	163943	1	0	0
T52	31582	1	0	0
T53	0	22	0	0
T61	7777	0	0	0
T70	15936	1	0	0
T82	0	23	0	0
T88	0	7	0	0
T89	0	25	0	0
T90	0	10	0	0
T91	0	7	0	0
T92	0	8	0	0
T93	0	1	0	0
T94	0	1	0	0
T95	0	2	0	0
T96	0	5	0	0
T97	0	2	0	0
T98	0	6	0	0
T99	0	1	0	0
T100	0	1	0	0
T101	450	0	0	0
T102	583	0	0	0
T103	522	0	0	0
T104	505	0	0	0
T105	497	0	0	0
T106	616	0	0	0
T107	697	0	0	0
T108	22954	0	0	0
T109	686	0	0	0
T110	678	0	0	0
T111	693	0	0	0
T112	29772	0	0	0
T113	522	0	0	0
T114	715	0	0	0
T115	15724	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206572444	1173093	0	0
T12	13384	1	0	0
T13	83132	78	0	0
T14	4752	0	0	0
T15	65440	33	0	0
T16	488	0	0	0
T17	114965	0	0	0
T18	2225	0	0	0
T20	29027	4854	0	0
T21	0	31	0	0
T24	3682	0	0	0
T25	5005	8	0	0
T26	4746	3	0	0
T27	31955	0	0	0
T28	2877	0	0	0
T29	100696	3920	0	0
T35	37245	611	0	0
T36	10476	0	0	0
T39	0	5	0	0
T40	0	1861	0	0
T44	0	687	0	0
T52	0	3	0	0
T54	0	62	0	0
T56	1608	0	0	0
T57	422	0	0	0
T58	615	0	0	0
T69	2788	7	0	0
T83	0	24	0	0
T84	0	18	0	0
T85	0	12	0	0
T86	0	7	0	0
T87	0	6	0	0
T116	0	2993	0	0
T117	8410	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206572444	5497	0	0
T12	13384	1	0	0
T13	83132	1	0	0
T14	4752	0	0	0
T15	65440	3	0	0
T16	488	0	0	0
T17	114965	0	0	0
T18	2225	0	0	0
T20	29027	33	0	0
T21	0	4	0	0
T24	3682	0	0	0
T25	5005	1	0	0
T26	4746	1	0	0
T27	31955	0	0	0
T28	2877	0	0	0
T29	100696	32	0	0
T35	37245	5	0	0
T36	10476	0	0	0
T39	0	1	0	0
T40	0	28	0	0
T44	0	12	0	0
T52	0	1	0	0
T54	0	2	0	0
T56	1608	0	0	0
T57	422	0	0	0
T58	615	0	0	0
T69	2788	1	0	0
T83	0	3	0	0
T84	0	2	0	0
T85	0	2	0	0
T86	0	2	0	0
T87	0	2	0	0
T116	0	25	0	0
T117	8410	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206572444	179654745	0	0
T12	86996	27529	0	0
T13	308776	231838	0	0
T24	13676	3250	0	0
T25	18590	7921	0	0
T26	17628	7065	0	0
T27	118690	99668	0	0
T34	140946	118496	0	0
T35	322790	267106	0	0
T36	90792	11167	0	0
T69	18122	7585	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206572444	179711809	0	0
T12	86996	27618	0	0
T13	308776	231988	0	0
T24	13676	3276	0	0
T25	18590	7946	0	0
T26	17628	7091	0	0
T27	118690	99690	0	0
T34	140946	118518	0	0
T35	322790	267128	0	0
T36	90792	11344	0	0
T69	18122	7611	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206572444	9012	0	0
T12	16730	1	0	0
T13	83132	1	0	0
T14	4752	0	0	0
T15	52352	4	0	0
T16	488	0	0	0
T17	114965	0	0	0
T18	2225	0	0	0
T20	29027	33	0	0
T21	0	4	0	0
T24	3682	0	0	0
T25	5005	2	0	0
T26	4746	1	0	0
T27	31955	0	0	0
T28	1644	0	0	0
T29	75522	32	0	0
T34	16263	16	0	0
T35	37245	0	0	0
T36	13968	1	0	0
T39	0	1	0	0
T44	0	12	0	0
T50	0	1	0	0
T52	0	3	0	0
T54	0	1	0	0
T56	1206	0	0	0
T57	422	0	0	0
T58	615	0	0	0
T69	3485	1	0	0
T83	0	3	0	0
T84	0	2	0	0
T85	0	2	0	0
T86	0	2	0	0
T87	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206572444	8381	0	0
T12	13384	1	0	0
T13	83132	1	0	0
T14	4752	0	0	0
T15	65440	3	0	0
T16	488	0	0	0
T17	114965	0	0	0
T18	2225	0	0	0
T20	29027	33	0	0
T21	0	4	0	0
T24	3682	0	0	0
T25	5005	1	0	0
T26	4746	1	0	0
T27	31955	0	0	0
T28	1644	0	0	0
T29	100696	32	0	0
T34	16263	16	0	0
T35	37245	5	0	0
T36	10476	0	0	0
T39	0	1	0	0
T40	0	28	0	0
T44	0	12	0	0
T52	0	2	0	0
T54	0	2	0	0
T56	1608	0	0	0
T57	422	0	0	0
T58	615	0	0	0
T69	2788	1	0	0
T83	0	3	0	0
T84	0	2	0	0
T85	0	2	0	0
T86	0	2	0	0
T87	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206572444	5497	0	0
T12	13384	1	0	0
T13	83132	1	0	0
T14	4752	0	0	0
T15	65440	3	0	0
T16	488	0	0	0
T17	114965	0	0	0
T18	2225	0	0	0
T20	29027	33	0	0
T21	0	4	0	0
T24	3682	0	0	0
T25	5005	1	0	0
T26	4746	1	0	0
T27	31955	0	0	0
T28	2877	0	0	0
T29	100696	32	0	0
T35	37245	5	0	0
T36	10476	0	0	0
T39	0	1	0	0
T40	0	28	0	0
T44	0	12	0	0
T52	0	1	0	0
T54	0	2	0	0
T56	1608	0	0	0
T57	422	0	0	0
T58	615	0	0	0
T69	2788	1	0	0
T83	0	3	0	0
T84	0	2	0	0
T85	0	2	0	0
T86	0	2	0	0
T87	0	2	0	0
T116	0	25	0	0
T117	8410	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206572444	5497	0	0
T12	13384	1	0	0
T13	83132	1	0	0
T14	4752	0	0	0
T15	65440	3	0	0
T16	488	0	0	0
T17	114965	0	0	0
T18	2225	0	0	0
T20	29027	33	0	0
T21	0	4	0	0
T24	3682	0	0	0
T25	5005	1	0	0
T26	4746	1	0	0
T27	31955	0	0	0
T28	2877	0	0	0
T29	100696	32	0	0
T35	37245	5	0	0
T36	10476	0	0	0
T39	0	1	0	0
T40	0	28	0	0
T44	0	12	0	0
T52	0	1	0	0
T54	0	2	0	0
T56	1608	0	0	0
T57	422	0	0	0
T58	615	0	0	0
T69	2788	1	0	0
T83	0	3	0	0
T84	0	2	0	0
T85	0	2	0	0
T86	0	2	0	0
T87	0	2	0	0
T116	0	25	0	0
T117	8410	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	206572444	1166801	0	0
T12	13384	0	0	0
T13	83132	77	0	0
T14	4752	0	0	0
T15	65440	30	0	0
T16	488	0	0	0
T17	114965	0	0	0
T18	2225	0	0	0
T20	29027	4817	0	0
T21	0	27	0	0
T24	3682	0	0	0
T25	5005	7	0	0
T26	4746	2	0	0
T27	31955	0	0	0
T28	2877	0	0	0
T29	100696	3876	0	0
T35	37245	606	0	0
T36	10476	0	0	0
T39	0	4	0	0
T40	0	1833	0	0
T44	0	673	0	0
T45	0	9	0	0
T52	0	2	0	0
T54	0	60	0	0
T56	1608	0	0	0
T57	422	0	0	0
T58	615	0	0	0
T69	2788	6	0	0
T83	0	21	0	0
T84	0	16	0	0
T85	0	10	0	0
T86	0	5	0	0
T87	0	4	0	0
T116	0	2967	0	0
T117	8410	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71505846	52026	0	0
T12	30114	34	0	0
T13	106884	94	0	0
T14	2376	12	0	0
T15	0	9	0	0
T16	0	2	0	0
T17	0	47	0	0
T19	0	25	0	0
T24	4734	2	0	0
T25	6435	3	0	0
T26	6102	3	0	0
T27	41085	48	0	0
T28	822	0	0	0
T34	37947	53	0	0
T35	86905	52	0	0
T36	31428	68	0	0
T57	0	6	0	0
T58	0	4	0	0
T63	0	10	0	0
T69	6273	3	0	0
T118	0	2	0	0
T119	0	7	0	0
T120	0	18	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39725470	36405435	0	0
T12	16730	6730	0	0
T13	59380	47335	0	0
T24	2630	630	0	0
T25	3575	1575	0	0
T26	3390	1390	0	0
T27	22825	20825	0	0
T34	27105	25105	0	0
T35	62075	60075	0	0
T36	17460	2305	0	0
T69	3485	1485	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135066598	123778479	0	0
T12	56882	22882	0	0
T13	201892	160939	0	0
T24	8942	2142	0	0
T25	12155	5355	0	0
T26	11526	4726	0	0
T27	77605	70805	0	0
T34	92157	85357	0	0
T35	211055	204255	0	0
T36	59364	7837	0	0
T69	11849	5049	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71505846	65529783	0	0
T12	30114	12114	0	0
T13	106884	85203	0	0
T24	4734	1134	0	0
T25	6435	2835	0	0
T26	6102	2502	0	0
T27	41085	37485	0	0
T34	48789	45189	0	0
T35	111735	108135	0	0
T36	31428	4149	0	0
T69	6273	2673	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	182737162	4498	0	0
T12	13384	1	0	0
T13	83132	1	0	0
T14	4752	0	0	0
T15	65440	3	0	0
T16	488	0	0	0
T17	114965	0	0	0
T18	2225	0	0	0
T20	29027	29	0	0
T21	0	4	0	0
T24	3682	0	0	0
T25	5005	1	0	0
T26	4746	1	0	0
T27	31955	0	0	0
T28	2877	0	0	0
T29	100696	20	0	0
T35	37245	5	0	0
T36	10476	0	0	0
T39	0	1	0	0
T40	0	28	0	0
T42	0	3	0	0
T44	0	10	0	0
T52	0	1	0	0
T54	0	2	0	0
T56	1608	0	0	0
T57	422	0	0	0
T58	615	0	0	0
T69	2788	1	0	0
T83	0	3	0	0
T84	0	2	0	0
T85	0	2	0	0
T86	0	2	0	0
T87	0	2	0	0
T117	8410	0	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23835282	778900	0	0
T14	2376	489	0	0
T15	26176	0	0	0
T16	976	0	0	0
T17	344895	708	0	0
T18	6675	353	0	0
T19	18993	214	0	0
T20	29027	0	0	0
T21	13600	0	0	0
T29	50348	0	0	0
T48	0	982	0	0
T50	0	34	0	0
T56	804	0	0	0
T57	1266	0	0	0
T58	1845	0	0	0
T59	0	424	0	0
T60	0	299	0	0
T61	0	287	0	0
T62	0	1244	0	0
T70	0	134	0	0
T75	0	252	0	0
T78	0	1088	0	0
T80	0	48	0	0
T81	0	32431	0	0
T117	8410	0	0	0
T119	522	0	0	0
T120	2373	0	0	0
T121	0	262549	0	0