Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T34,T35,T27
1	Covered	T34,T35,T36

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T34,T35,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T34,T35,T27

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T34,T35,T27

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T27
1	0	Covered	T29,T20,T44
1	1	Covered	T34,T35,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T34,T35,T27
0	1	Covered	T34,T27,T82
1	0	Covered	T53,T90,T232

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T35,T29,T20
0	1	Covered	T35,T29,T20
1	0	Covered	T72

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T35,T29,T20
1	-	Covered	T35,T29,T20

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T34,T35,T27
0	1	Covered	T34,T35,T27
0	0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T27
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T34,T35,T27
IdleSt	0	-	-	-	-	-	-	Covered	T34,T35,T27
DebounceSt	-	1	-	-	-	-	-	Covered	T67,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T34,T35,T27
DebounceSt	-	0	1	0	-	-	-	Covered	T35,T67,T68
DebounceSt	-	0	0	-	-	-	-	Covered	T34,T35,T27
DetectSt	-	-	-	-	1	-	-	Covered	T34,T27,T82
DetectSt	-	-	-	-	0	1	-	Covered	T35,T29,T20
DetectSt	-	-	-	-	0	0	-	Covered	T34,T35,T27
StableSt	-	-	-	-	-	-	1	Covered	T35,T29,T20
StableSt	-	-	-	-	-	-	0	Covered	T35,T29,T20
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7945094	2995	0	0
CntIncr_A	7945094	106815	0	0
CntNoWrap_A	7945094	7275735	0	0
DetectStDropOut_A	7945094	466	0	0
DetectedOut_A	7945094	92931	0	0
DetectedPulseOut_A	7945094	885	0	0
DisabledIdleSt_A	7945094	6793438	0	0
DisabledNoDetection_A	7945094	6795589	0	0
EnterDebounceSt_A	7945094	1513	0	0
EnterDetectSt_A	7945094	1482	0	0
EnterStableSt_A	7945094	885	0	0
PulseIsPulse_A	7945094	885	0	0
StayInStableSt	7945094	91934	0	0
gen_high_event_sva.HighLevelEvent_A	7945094	7281087	0	0
gen_high_level_sva.HighLevelEvent_A	7945094	7281087	0	0
gen_not_sticky_sva.StableStDropOut_A	7945094	752	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	2995	0	0
T12	3346	0	0	0
T13	11876	0	0	0
T20	0	54	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	10	0	0
T29	0	52	0	0
T34	5421	32	0	0
T35	12415	15	0	0
T36	3492	0	0	0
T40	0	52	0	0
T44	0	20	0	0
T53	0	66	0	0
T69	697	0	0	0
T82	0	46	0	0
T116	0	50	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	106815	0	0
T12	3346	0	0	0
T13	11876	0	0	0
T20	0	2160	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	192	0	0
T29	0	1846	0	0
T34	5421	888	0	0
T35	12415	2385	0	0
T36	3492	0	0	0
T40	0	2496	0	0
T44	0	390	0	0
T53	0	1658	0	0
T69	697	0	0	0
T82	0	7432	0	0
T116	0	1300	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7275735	0	0
T12	3346	1342	0	0
T13	11876	9461	0	0
T24	526	125	0	0
T25	715	314	0	0
T26	678	277	0	0
T27	4565	4154	0	0
T34	5421	4988	0	0
T35	12415	11999	0	0
T36	3492	454	0	0
T69	697	296	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	466	0	0
T12	3346	0	0	0
T13	11876	0	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	5	0	0
T34	5421	16	0	0
T35	12415	0	0	0
T36	3492	0	0	0
T53	0	22	0	0
T69	697	0	0	0
T82	0	23	0	0
T88	0	7	0	0
T89	0	25	0	0
T90	0	10	0	0
T92	0	8	0	0
T232	0	11	0	0
T233	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	92931	0	0
T12	3346	0	0	0
T13	11876	0	0	0
T20	0	4104	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	0	3593	0	0
T35	12415	611	0	0
T36	3492	0	0	0
T40	0	1685	0	0
T44	0	569	0	0
T69	697	0	0	0
T71	0	834	0	0
T115	0	13	0	0
T116	0	2993	0	0
T234	0	2608	0	0
T235	0	2388	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	885	0	0
T12	3346	0	0	0
T13	11876	0	0	0
T20	0	27	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	0	26	0	0
T35	12415	5	0	0
T36	3492	0	0	0
T40	0	26	0	0
T44	0	10	0	0
T69	697	0	0	0
T71	0	6	0	0
T115	0	6	0	0
T116	0	25	0	0
T234	0	19	0	0
T235	0	26	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	6793438	0	0
T12	3346	1342	0	0
T13	11876	9461	0	0
T24	526	125	0	0
T25	715	314	0	0
T26	678	277	0	0
T27	4565	2015	0	0
T34	5421	2014	0	0
T35	12415	2015	0	0
T36	3492	454	0	0
T69	697	296	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	6795589	0	0
T12	3346	1346	0	0
T13	11876	9467	0	0
T24	526	126	0	0
T25	715	315	0	0
T26	678	278	0	0
T27	4565	2015	0	0
T34	5421	2014	0	0
T35	12415	2015	0	0
T36	3492	461	0	0
T69	697	297	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	1513	0	0
T12	3346	0	0	0
T13	11876	0	0	0
T20	0	27	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	5	0	0
T29	0	26	0	0
T34	5421	16	0	0
T35	12415	10	0	0
T36	3492	0	0	0
T40	0	26	0	0
T44	0	10	0	0
T53	0	33	0	0
T69	697	0	0	0
T82	0	23	0	0
T116	0	25	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	1482	0	0
T12	3346	0	0	0
T13	11876	0	0	0
T20	0	27	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	5	0	0
T29	0	26	0	0
T34	5421	16	0	0
T35	12415	5	0	0
T36	3492	0	0	0
T40	0	26	0	0
T44	0	10	0	0
T53	0	33	0	0
T69	697	0	0	0
T82	0	23	0	0
T116	0	25	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	885	0	0
T12	3346	0	0	0
T13	11876	0	0	0
T20	0	27	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	0	26	0	0
T35	12415	5	0	0
T36	3492	0	0	0
T40	0	26	0	0
T44	0	10	0	0
T69	697	0	0	0
T71	0	6	0	0
T115	0	6	0	0
T116	0	25	0	0
T234	0	19	0	0
T235	0	26	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	885	0	0
T12	3346	0	0	0
T13	11876	0	0	0
T20	0	27	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	0	26	0	0
T35	12415	5	0	0
T36	3492	0	0	0
T40	0	26	0	0
T44	0	10	0	0
T69	697	0	0	0
T71	0	6	0	0
T115	0	6	0	0
T116	0	25	0	0
T234	0	19	0	0
T235	0	26	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	91934	0	0
T12	3346	0	0	0
T13	11876	0	0	0
T20	0	4073	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	0	3561	0	0
T35	12415	606	0	0
T36	3492	0	0	0
T40	0	1659	0	0
T44	0	557	0	0
T69	697	0	0	0
T71	0	828	0	0
T115	0	7	0	0
T116	0	2967	0	0
T234	0	2588	0	0
T235	0	2362	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7281087	0	0
T12	3346	1346	0	0
T13	11876	9467	0	0
T24	526	126	0	0
T25	715	315	0	0
T26	678	278	0	0
T27	4565	4165	0	0
T34	5421	5021	0	0
T35	12415	12015	0	0
T36	3492	461	0	0
T69	697	297	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7281087	0	0
T12	3346	1346	0	0
T13	11876	9467	0	0
T24	526	126	0	0
T25	715	315	0	0
T26	678	278	0	0
T27	4565	4165	0	0
T34	5421	5021	0	0
T35	12415	12015	0	0
T36	3492	461	0	0
T69	697	297	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	752	0	0
T12	3346	0	0	0
T13	11876	0	0	0
T20	0	23	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	0	20	0	0
T35	12415	5	0	0
T36	3492	0	0	0
T40	0	26	0	0
T44	0	8	0	0
T69	697	0	0	0
T71	0	6	0	0
T115	0	6	0	0
T116	0	24	0	0
T234	0	18	0	0
T235	0	26	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T34,T35,T36

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T34,T35,T36

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T36,T13,T15

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T34,T35,T36	VC_COV_UNR
1	Covered	T36,T13,T15

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T13,T15,T29

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T35,T36,T13
1	0	Covered	T34,T35,T36
1	1	Covered	T36,T13,T15

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T15,T29
0	1	Covered	T52,T43,T45
1	0	Covered	T67,T68

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T15,T29
0	1	Covered	T13,T15,T20
1	0	Covered	T67

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T15,T29
1	-	Covered	T13,T15,T20

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T36,T13,T15
0	1	Covered	T36,T13,T15
0	0	Excluded	T34,T35,T36	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T15,T29
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T36,T13,T15
IdleSt	0	-	-	-	-	-	-	Covered	T34,T35,T36
DebounceSt	-	1	-	-	-	-	-	Covered	T67,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T15,T29
DebounceSt	-	0	1	0	-	-	-	Covered	T36,T15,T50
DebounceSt	-	0	0	-	-	-	-	Covered	T36,T13,T15
DetectSt	-	-	-	-	1	-	-	Covered	T52,T43,T45
DetectSt	-	-	-	-	0	1	-	Covered	T13,T15,T29
DetectSt	-	-	-	-	0	0	-	Covered	T13,T15,T29
StableSt	-	-	-	-	-	-	1	Covered	T13,T15,T20
StableSt	-	-	-	-	-	-	0	Covered	T13,T15,T29
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7945094	951	0	0
CntIncr_A	7945094	49012	0	0
CntNoWrap_A	7945094	7277779	0	0
DetectStDropOut_A	7945094	39	0	0
DetectedOut_A	7945094	18126	0	0
DetectedPulseOut_A	7945094	395	0	0
DisabledIdleSt_A	7945094	6890091	0	0
DisabledNoDetection_A	7945094	6891693	0	0
EnterDebounceSt_A	7945094	515	0	0
EnterDetectSt_A	7945094	439	0	0
EnterStableSt_A	7945094	395	0	0
PulseIsPulse_A	7945094	395	0	0
StayInStableSt	7945094	17690	0	0
gen_high_level_sva.HighLevelEvent_A	7945094	7281087	0	0
gen_not_sticky_sva.StableStDropOut_A	7945094	350	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	951	0	0
T12	3346	0	0	0
T13	11876	2	0	0
T14	1188	0	0	0
T15	0	7	0	0
T20	0	12	0	0
T21	0	8	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	0	12	0	0
T36	3492	1	0	0
T39	0	2	0	0
T44	0	4	0	0
T50	0	1	0	0
T52	0	5	0	0
T69	697	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	49012	0	0
T12	3346	0	0	0
T13	11876	91	0	0
T14	1188	0	0	0
T15	0	587	0	0
T20	0	558	0	0
T21	0	472	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	0	546	0	0
T36	3492	20	0	0
T39	0	25	0	0
T44	0	110	0	0
T50	0	20	0	0
T52	0	135	0	0
T69	697	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7277779	0	0
T12	3346	1342	0	0
T13	11876	9459	0	0
T24	526	125	0	0
T25	715	314	0	0
T26	678	277	0	0
T27	4565	4164	0	0
T34	5421	5020	0	0
T35	12415	12014	0	0
T36	3492	453	0	0
T69	697	296	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	39	0	0
T43	23062	3	0	0
T45	163943	1	0	0
T52	31582	1	0	0
T61	7777	0	0	0
T91	0	7	0	0
T93	0	1	0	0
T95	0	2	0	0
T96	0	5	0	0
T97	0	2	0	0
T98	0	6	0	0
T99	0	1	0	0
T101	450	0	0	0
T102	583	0	0	0
T103	522	0	0	0
T104	505	0	0	0
T105	497	0	0	0
T106	616	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	18126	0	0
T13	11876	78	0	0
T14	1188	0	0	0
T15	13088	33	0	0
T20	0	750	0	0
T21	0	31	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	327	0	0
T39	0	5	0	0
T40	0	176	0	0
T44	0	118	0	0
T52	0	3	0	0
T54	0	53	0	0
T56	402	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	395	0	0
T13	11876	1	0	0
T14	1188	0	0	0
T15	13088	3	0	0
T20	0	6	0	0
T21	0	4	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	6	0	0
T39	0	1	0	0
T40	0	2	0	0
T44	0	2	0	0
T52	0	1	0	0
T54	0	1	0	0
T56	402	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	6890091	0	0
T12	3346	1342	0	0
T13	11876	4745	0	0
T24	526	125	0	0
T25	715	314	0	0
T26	678	277	0	0
T27	4565	4164	0	0
T34	5421	5020	0	0
T35	12415	11403	0	0
T36	3492	417	0	0
T69	697	296	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	6891693	0	0
T12	3346	1346	0	0
T13	11876	4749	0	0
T24	526	126	0	0
T25	715	315	0	0
T26	678	278	0	0
T27	4565	4165	0	0
T34	5421	5021	0	0
T35	12415	11404	0	0
T36	3492	423	0	0
T69	697	297	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	515	0	0
T12	3346	0	0	0
T13	11876	1	0	0
T14	1188	0	0	0
T15	0	4	0	0
T20	0	6	0	0
T21	0	4	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	0	6	0	0
T36	3492	1	0	0
T39	0	1	0	0
T44	0	2	0	0
T50	0	1	0	0
T52	0	3	0	0
T69	697	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	439	0	0
T13	11876	1	0	0
T14	1188	0	0	0
T15	13088	3	0	0
T20	0	6	0	0
T21	0	4	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	6	0	0
T39	0	1	0	0
T40	0	2	0	0
T44	0	2	0	0
T52	0	2	0	0
T54	0	1	0	0
T56	402	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	395	0	0
T13	11876	1	0	0
T14	1188	0	0	0
T15	13088	3	0	0
T20	0	6	0	0
T21	0	4	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	6	0	0
T39	0	1	0	0
T40	0	2	0	0
T44	0	2	0	0
T52	0	1	0	0
T54	0	1	0	0
T56	402	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	395	0	0
T13	11876	1	0	0
T14	1188	0	0	0
T15	13088	3	0	0
T20	0	6	0	0
T21	0	4	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	6	0	0
T39	0	1	0	0
T40	0	2	0	0
T44	0	2	0	0
T52	0	1	0	0
T54	0	1	0	0
T56	402	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	17690	0	0
T13	11876	77	0	0
T14	1188	0	0	0
T15	13088	30	0	0
T20	0	744	0	0
T21	0	27	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	315	0	0
T39	0	4	0	0
T40	0	174	0	0
T44	0	116	0	0
T52	0	2	0	0
T54	0	52	0	0
T56	402	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7281087	0	0
T12	3346	1346	0	0
T13	11876	9467	0	0
T24	526	126	0	0
T25	715	315	0	0
T26	678	278	0	0
T27	4565	4165	0	0
T34	5421	5021	0	0
T35	12415	12015	0	0
T36	3492	461	0	0
T69	697	297	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	350	0	0
T13	11876	1	0	0
T14	1188	0	0	0
T15	13088	3	0	0
T20	0	6	0	0
T21	0	4	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T42	0	3	0	0
T44	0	2	0	0
T52	0	1	0	0
T54	0	1	0	0
T56	402	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T34,T35,T27
1	Covered	T34,T35,T36

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T34,T35,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T34,T35,T27

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T34,T35,T27

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T27
1	0	Covered	T29,T20,T44
1	1	Covered	T34,T35,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T34,T35,T27
0	1	Covered	T34,T27,T82
1	0	Covered	T53,T115,T90

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T35,T29,T20
0	1	Covered	T35,T29,T20
1	0	Covered	T74

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T35,T29,T20
1	-	Covered	T35,T29,T20

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T34,T35,T27
0	1	Covered	T34,T35,T27
0	0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T27
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T34,T35,T27
IdleSt	0	-	-	-	-	-	-	Covered	T34,T35,T27
DebounceSt	-	1	-	-	-	-	-	Covered	T67,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T34,T35,T27
DebounceSt	-	0	1	0	-	-	-	Covered	T35,T67,T68
DebounceSt	-	0	0	-	-	-	-	Covered	T34,T35,T27
DetectSt	-	-	-	-	1	-	-	Covered	T34,T27,T82
DetectSt	-	-	-	-	0	1	-	Covered	T35,T29,T20
DetectSt	-	-	-	-	0	0	-	Covered	T34,T35,T27
StableSt	-	-	-	-	-	-	1	Covered	T35,T29,T20
StableSt	-	-	-	-	-	-	0	Covered	T35,T29,T20
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7945094	3035	0	0
CntIncr_A	7945094	112504	0	0
CntNoWrap_A	7945094	7275695	0	0
DetectStDropOut_A	7945094	491	0	0
DetectedOut_A	7945094	73027	0	0
DetectedPulseOut_A	7945094	885	0	0
DisabledIdleSt_A	7945094	6805035	0	0
DisabledNoDetection_A	7945094	6807197	0	0
EnterDebounceSt_A	7945094	1534	0	0
EnterDetectSt_A	7945094	1503	0	0
EnterStableSt_A	7945094	885	0	0
PulseIsPulse_A	7945094	885	0	0
StayInStableSt	7945094	72040	0	0
gen_high_event_sva.HighLevelEvent_A	7945094	7281087	0	0
gen_high_level_sva.HighLevelEvent_A	7945094	7281087	0	0
gen_not_sticky_sva.StableStDropOut_A	7945094	773	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	3035	0	0
T12	3346	0	0	0
T13	11876	0	0	0
T20	0	54	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	41	0	0
T29	0	14	0	0
T34	5421	20	0	0
T35	12415	19	0	0
T36	3492	0	0	0
T40	0	40	0	0
T44	0	30	0	0
T53	0	26	0	0
T69	697	0	0	0
T82	0	12	0	0
T116	0	62	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	112504	0	0
T12	3346	0	0	0
T13	11876	0	0	0
T20	0	2160	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	819	0	0
T29	0	658	0	0
T34	5421	554	0	0
T35	12415	2946	0	0
T36	3492	0	0	0
T40	0	1660	0	0
T44	0	495	0	0
T53	0	655	0	0
T69	697	0	0	0
T82	0	1935	0	0
T116	0	1550	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7275695	0	0
T12	3346	1342	0	0
T13	11876	9461	0	0
T24	526	125	0	0
T25	715	314	0	0
T26	678	277	0	0
T27	4565	4123	0	0
T34	5421	5000	0	0
T35	12415	11995	0	0
T36	3492	454	0	0
T69	697	296	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	491	0	0
T12	3346	0	0	0
T13	11876	0	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	20	0	0
T34	5421	10	0	0
T35	12415	0	0	0
T36	3492	0	0	0
T53	0	2	0	0
T69	697	0	0	0
T82	0	6	0	0
T88	0	25	0	0
T89	0	21	0	0
T90	0	8	0	0
T92	0	22	0	0
T115	0	8	0	0
T233	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	73027	0	0
T12	3346	0	0	0
T13	11876	0	0	0
T20	0	3179	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	0	902	0	0
T35	12415	1042	0	0
T36	3492	0	0	0
T40	0	2424	0	0
T44	0	1695	0	0
T69	697	0	0	0
T71	0	2845	0	0
T116	0	3553	0	0
T234	0	184	0	0
T235	0	146	0	0
T236	0	97	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	885	0	0
T12	3346	0	0	0
T13	11876	0	0	0
T20	0	27	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	0	7	0	0
T35	12415	7	0	0
T36	3492	0	0	0
T40	0	20	0	0
T44	0	15	0	0
T69	697	0	0	0
T71	0	21	0	0
T116	0	31	0	0
T234	0	3	0	0
T235	0	11	0	0
T236	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	6805035	0	0
T12	3346	1342	0	0
T13	11876	9461	0	0
T24	526	125	0	0
T25	715	314	0	0
T26	678	277	0	0
T27	4565	2015	0	0
T34	5421	2014	0	0
T35	12415	2015	0	0
T36	3492	454	0	0
T69	697	296	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	6807197	0	0
T12	3346	1346	0	0
T13	11876	9467	0	0
T24	526	126	0	0
T25	715	315	0	0
T26	678	278	0	0
T27	4565	2015	0	0
T34	5421	2014	0	0
T35	12415	2015	0	0
T36	3492	461	0	0
T69	697	297	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	1534	0	0
T12	3346	0	0	0
T13	11876	0	0	0
T20	0	27	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	21	0	0
T29	0	7	0	0
T34	5421	10	0	0
T35	12415	13	0	0
T36	3492	0	0	0
T40	0	20	0	0
T44	0	15	0	0
T53	0	13	0	0
T69	697	0	0	0
T82	0	6	0	0
T116	0	31	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	1503	0	0
T12	3346	0	0	0
T13	11876	0	0	0
T20	0	27	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	21	0	0
T29	0	7	0	0
T34	5421	10	0	0
T35	12415	7	0	0
T36	3492	0	0	0
T40	0	20	0	0
T44	0	15	0	0
T53	0	13	0	0
T69	697	0	0	0
T82	0	6	0	0
T116	0	31	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	885	0	0
T12	3346	0	0	0
T13	11876	0	0	0
T20	0	27	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	0	7	0	0
T35	12415	7	0	0
T36	3492	0	0	0
T40	0	20	0	0
T44	0	15	0	0
T69	697	0	0	0
T71	0	21	0	0
T116	0	31	0	0
T234	0	3	0	0
T235	0	11	0	0
T236	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	885	0	0
T12	3346	0	0	0
T13	11876	0	0	0
T20	0	27	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	0	7	0	0
T35	12415	7	0	0
T36	3492	0	0	0
T40	0	20	0	0
T44	0	15	0	0
T69	697	0	0	0
T71	0	21	0	0
T116	0	31	0	0
T234	0	3	0	0
T235	0	11	0	0
T236	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	72040	0	0
T12	3346	0	0	0
T13	11876	0	0	0
T20	0	3145	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	0	892	0	0
T35	12415	1035	0	0
T36	3492	0	0	0
T40	0	2404	0	0
T44	0	1678	0	0
T69	697	0	0	0
T71	0	2822	0	0
T116	0	3520	0	0
T234	0	181	0	0
T235	0	135	0	0
T236	0	93	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7281087	0	0
T12	3346	1346	0	0
T13	11876	9467	0	0
T24	526	126	0	0
T25	715	315	0	0
T26	678	278	0	0
T27	4565	4165	0	0
T34	5421	5021	0	0
T35	12415	12015	0	0
T36	3492	461	0	0
T69	697	297	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7281087	0	0
T12	3346	1346	0	0
T13	11876	9467	0	0
T24	526	126	0	0
T25	715	315	0	0
T26	678	278	0	0
T27	4565	4165	0	0
T34	5421	5021	0	0
T35	12415	12015	0	0
T36	3492	461	0	0
T69	697	297	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	773	0	0
T12	3346	0	0	0
T13	11876	0	0	0
T20	0	20	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	0	4	0	0
T35	12415	7	0	0
T36	3492	0	0	0
T40	0	20	0	0
T44	0	13	0	0
T69	697	0	0	0
T71	0	19	0	0
T116	0	29	0	0
T234	0	3	0	0
T235	0	11	0	0
T236	0	4	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T34,T35,T13
1	Covered	T34,T35,T36

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T13
1	0	Covered	T34,T35,T36
1	1	Covered	T34,T35,T36

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T13,T15,T29

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T34,T35,T36	VC_COV_UNR
1	Covered	T13,T15,T29

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T13,T15,T29

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T35,T13,T15
1	0	Covered	T34,T35,T36
1	1	Covered	T13,T15,T29

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T15,T29
0	1	Covered	T15,T21,T52
1	0	Covered	T67,T68

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T29,T20
0	1	Covered	T13,T44,T40
1	0	Covered	T67

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T29,T20
1	-	Covered	T13,T44,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T13,T15,T29
0	1	Covered	T13,T15,T29
0	0	Excluded	T34,T35,T36	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T15,T29
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T13,T15,T29
IdleSt	0	-	-	-	-	-	-	Covered	T34,T35,T36
DebounceSt	-	1	-	-	-	-	-	Covered	T67,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T15,T29
DebounceSt	-	0	1	0	-	-	-	Covered	T52,T40,T129
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T15,T29
DetectSt	-	-	-	-	1	-	-	Covered	T15,T21,T52
DetectSt	-	-	-	-	0	1	-	Covered	T13,T29,T20
DetectSt	-	-	-	-	0	0	-	Covered	T13,T15,T29
StableSt	-	-	-	-	-	-	1	Covered	T13,T44,T40
StableSt	-	-	-	-	-	-	0	Covered	T13,T29,T20
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7945094	823	0	0
CntIncr_A	7945094	43920	0	0
CntNoWrap_A	7945094	7277907	0	0
DetectStDropOut_A	7945094	65	0	0
DetectedOut_A	7945094	15105	0	0
DetectedPulseOut_A	7945094	318	0	0
DisabledIdleSt_A	7945094	6928543	0	0
DisabledNoDetection_A	7945094	6930246	0	0
EnterDebounceSt_A	7945094	437	0	0
EnterDetectSt_A	7945094	388	0	0
EnterStableSt_A	7945094	318	0	0
PulseIsPulse_A	7945094	318	0	0
StayInStableSt	7945094	14747	0	0
gen_high_level_sva.HighLevelEvent_A	7945094	7281087	0	0
gen_not_sticky_sva.StableStDropOut_A	7945094	274	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	823	0	0
T13	11876	2	0	0
T14	1188	0	0	0
T15	13088	4	0	0
T20	0	6	0	0
T21	0	6	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	2	0	0
T40	0	5	0	0
T43	0	6	0	0
T44	0	10	0	0
T52	0	17	0	0
T54	0	2	0	0
T56	402	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	43920	0	0
T13	11876	113	0	0
T14	1188	0	0	0
T15	13088	351	0	0
T20	0	318	0	0
T21	0	377	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	99	0	0
T40	0	215	0	0
T43	0	183	0	0
T44	0	270	0	0
T52	0	746	0	0
T54	0	86	0	0
T56	402	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7277907	0	0
T12	3346	1342	0	0
T13	11876	9459	0	0
T24	526	125	0	0
T25	715	314	0	0
T26	678	277	0	0
T27	4565	4164	0	0
T34	5421	5020	0	0
T35	12415	12014	0	0
T36	3492	454	0	0
T69	697	296	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	65	0	0
T15	13088	2	0	0
T16	488	0	0	0
T17	114965	0	0	0
T18	2225	0	0	0
T21	13600	3	0	0
T29	25174	0	0	0
T52	0	8	0	0
T56	402	0	0	0
T57	422	0	0	0
T58	615	0	0	0
T97	0	5	0	0
T120	2373	0	0	0
T193	0	5	0	0
T237	0	1	0	0
T238	0	1	0	0
T239	0	1	0	0
T240	0	6	0	0
T241	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	15105	0	0
T13	11876	56	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T20	0	330	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	196	0	0
T40	0	128	0	0
T43	0	21	0	0
T44	0	300	0	0
T45	0	11	0	0
T54	0	72	0	0
T56	402	0	0	0
T71	0	137	0	0
T129	0	112	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	318	0	0
T13	11876	1	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T20	0	3	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	1	0	0
T40	0	2	0	0
T43	0	3	0	0
T44	0	5	0	0
T45	0	1	0	0
T54	0	1	0	0
T56	402	0	0	0
T71	0	2	0	0
T129	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	6928543	0	0
T12	3346	1342	0	0
T13	11876	4745	0	0
T24	526	125	0	0
T25	715	314	0	0
T26	678	277	0	0
T27	4565	4164	0	0
T34	5421	5020	0	0
T35	12415	10972	0	0
T36	3492	454	0	0
T69	697	296	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	6930246	0	0
T12	3346	1346	0	0
T13	11876	4749	0	0
T24	526	126	0	0
T25	715	315	0	0
T26	678	278	0	0
T27	4565	4165	0	0
T34	5421	5021	0	0
T35	12415	10973	0	0
T36	3492	461	0	0
T69	697	297	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	437	0	0
T13	11876	1	0	0
T14	1188	0	0	0
T15	13088	2	0	0
T20	0	3	0	0
T21	0	3	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	1	0	0
T40	0	3	0	0
T43	0	3	0	0
T44	0	5	0	0
T52	0	9	0	0
T54	0	1	0	0
T56	402	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	388	0	0
T13	11876	1	0	0
T14	1188	0	0	0
T15	13088	2	0	0
T20	0	3	0	0
T21	0	3	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	1	0	0
T40	0	2	0	0
T43	0	3	0	0
T44	0	5	0	0
T52	0	8	0	0
T54	0	1	0	0
T56	402	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	318	0	0
T13	11876	1	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T20	0	3	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	1	0	0
T40	0	2	0	0
T43	0	3	0	0
T44	0	5	0	0
T45	0	1	0	0
T54	0	1	0	0
T56	402	0	0	0
T71	0	2	0	0
T129	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	318	0	0
T13	11876	1	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T20	0	3	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	1	0	0
T40	0	2	0	0
T43	0	3	0	0
T44	0	5	0	0
T45	0	1	0	0
T54	0	1	0	0
T56	402	0	0	0
T71	0	2	0	0
T129	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	14747	0	0
T13	11876	55	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T20	0	324	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	194	0	0
T40	0	126	0	0
T43	0	18	0	0
T44	0	295	0	0
T45	0	10	0	0
T54	0	71	0	0
T56	402	0	0	0
T71	0	133	0	0
T129	0	109	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7281087	0	0
T12	3346	1346	0	0
T13	11876	9467	0	0
T24	526	126	0	0
T25	715	315	0	0
T26	678	278	0	0
T27	4565	4165	0	0
T34	5421	5021	0	0
T35	12415	12015	0	0
T36	3492	461	0	0
T69	697	297	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	274	0	0
T13	11876	1	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T40	0	2	0	0
T41	0	10	0	0
T43	0	3	0	0
T44	0	5	0	0
T45	0	1	0	0
T54	0	1	0	0
T56	402	0	0	0
T70	0	2	0	0
T129	0	3	0	0
T167	0	4	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T34,T35,T27
1	Covered	T34,T35,T36

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T34,T35,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T34,T35,T27

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T34,T35,T27

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T27
1	0	Covered	T29,T20,T44
1	1	Covered	T34,T35,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T34,T35,T29
0	1	Covered	T34,T27,T82
1	0	Covered	T44,T53,T71

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T35,T29,T20
0	1	Covered	T35,T29,T20
1	0	Covered	T242

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T35,T29,T20
1	-	Covered	T35,T29,T20

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T34,T35,T27
0	1	Covered	T34,T35,T27
0	0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T27
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T34,T35,T27
IdleSt	0	-	-	-	-	-	-	Covered	T34,T35,T27
DebounceSt	-	1	-	-	-	-	-	Covered	T67,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T34,T35,T27
DebounceSt	-	0	1	0	-	-	-	Covered	T35,T67,T68
DebounceSt	-	0	0	-	-	-	-	Covered	T34,T35,T27
DetectSt	-	-	-	-	1	-	-	Covered	T34,T27,T82
DetectSt	-	-	-	-	0	1	-	Covered	T35,T29,T20
DetectSt	-	-	-	-	0	0	-	Covered	T34,T35,T29
StableSt	-	-	-	-	-	-	1	Covered	T35,T29,T20
StableSt	-	-	-	-	-	-	0	Covered	T35,T29,T20
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7945094	2997	0	0
CntIncr_A	7945094	108841	0	0
CntNoWrap_A	7945094	7275733	0	0
DetectStDropOut_A	7945094	577	0	0
DetectedOut_A	7945094	56191	0	0
DetectedPulseOut_A	7945094	679	0	0
DisabledIdleSt_A	7945094	6817282	0	0
DisabledNoDetection_A	7945094	6819479	0	0
EnterDebounceSt_A	7945094	1515	0	0
EnterDetectSt_A	7945094	1483	0	0
EnterStableSt_A	7945094	679	0	0
PulseIsPulse_A	7945094	679	0	0
StayInStableSt	7945094	55444	0	0
gen_high_event_sva.HighLevelEvent_A	7945094	7281087	0	0
gen_high_level_sva.HighLevelEvent_A	7945094	7281087	0	0
gen_not_sticky_sva.StableStDropOut_A	7945094	610	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	2997	0	0
T12	3346	0	0	0
T13	11876	0	0	0
T20	0	54	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	2	0	0
T29	0	28	0	0
T34	5421	52	0	0
T35	12415	28	0	0
T36	3492	0	0	0
T40	0	28	0	0
T44	0	42	0	0
T53	0	42	0	0
T69	697	0	0	0
T82	0	22	0	0
T116	0	42	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	108841	0	0
T12	3346	0	0	0
T13	11876	0	0	0
T20	0	2457	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	38	0	0
T29	0	1064	0	0
T34	5421	1455	0	0
T35	12415	4254	0	0
T36	3492	0	0	0
T40	0	1288	0	0
T44	0	1209	0	0
T53	0	1061	0	0
T69	697	0	0	0
T82	0	3550	0	0
T116	0	1239	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7275733	0	0
T12	3346	1342	0	0
T13	11876	9461	0	0
T24	526	125	0	0
T25	715	314	0	0
T26	678	277	0	0
T27	4565	4162	0	0
T34	5421	4968	0	0
T35	12415	11986	0	0
T36	3492	454	0	0
T69	697	296	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	577	0	0
T12	3346	0	0	0
T13	11876	0	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	1	0	0
T34	5421	26	0	0
T35	12415	0	0	0
T36	3492	0	0	0
T44	0	7	0	0
T53	0	10	0	0
T69	697	0	0	0
T71	0	8	0	0
T82	0	11	0	0
T88	0	4	0	0
T89	0	24	0	0
T90	0	9	0	0
T92	0	19	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	56191	0	0
T12	3346	0	0	0
T13	11876	0	0	0
T20	0	2882	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	0	1028	0	0
T35	12415	1350	0	0
T36	3492	0	0	0
T40	0	713	0	0
T65	0	1877	0	0
T69	697	0	0	0
T115	0	1993	0	0
T116	0	2371	0	0
T234	0	1388	0	0
T235	0	83	0	0
T236	0	3964	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	679	0	0
T12	3346	0	0	0
T13	11876	0	0	0
T20	0	27	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	0	14	0	0
T35	12415	9	0	0
T36	3492	0	0	0
T40	0	14	0	0
T65	0	10	0	0
T69	697	0	0	0
T115	0	25	0	0
T116	0	21	0	0
T234	0	11	0	0
T235	0	10	0	0
T236	0	30	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	6817282	0	0
T12	3346	1342	0	0
T13	11876	9461	0	0
T24	526	125	0	0
T25	715	314	0	0
T26	678	277	0	0
T27	4565	2015	0	0
T34	5421	2014	0	0
T35	12415	2015	0	0
T36	3492	454	0	0
T69	697	296	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	6819479	0	0
T12	3346	1346	0	0
T13	11876	9467	0	0
T24	526	126	0	0
T25	715	315	0	0
T26	678	278	0	0
T27	4565	2015	0	0
T34	5421	2014	0	0
T35	12415	2015	0	0
T36	3492	461	0	0
T69	697	297	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	1515	0	0
T12	3346	0	0	0
T13	11876	0	0	0
T20	0	27	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	1	0	0
T29	0	14	0	0
T34	5421	26	0	0
T35	12415	19	0	0
T36	3492	0	0	0
T40	0	14	0	0
T44	0	21	0	0
T53	0	21	0	0
T69	697	0	0	0
T82	0	11	0	0
T116	0	21	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	1483	0	0
T12	3346	0	0	0
T13	11876	0	0	0
T20	0	27	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	1	0	0
T29	0	14	0	0
T34	5421	26	0	0
T35	12415	9	0	0
T36	3492	0	0	0
T40	0	14	0	0
T44	0	21	0	0
T53	0	21	0	0
T69	697	0	0	0
T82	0	11	0	0
T116	0	21	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	679	0	0
T12	3346	0	0	0
T13	11876	0	0	0
T20	0	27	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	0	14	0	0
T35	12415	9	0	0
T36	3492	0	0	0
T40	0	14	0	0
T65	0	10	0	0
T69	697	0	0	0
T115	0	25	0	0
T116	0	21	0	0
T234	0	11	0	0
T235	0	10	0	0
T236	0	30	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	679	0	0
T12	3346	0	0	0
T13	11876	0	0	0
T20	0	27	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	0	14	0	0
T35	12415	9	0	0
T36	3492	0	0	0
T40	0	14	0	0
T65	0	10	0	0
T69	697	0	0	0
T115	0	25	0	0
T116	0	21	0	0
T234	0	11	0	0
T235	0	10	0	0
T236	0	30	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	55444	0	0
T12	3346	0	0	0
T13	11876	0	0	0
T20	0	2848	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	0	1013	0	0
T35	12415	1341	0	0
T36	3492	0	0	0
T40	0	699	0	0
T65	0	1862	0	0
T69	697	0	0	0
T115	0	1964	0	0
T116	0	2350	0	0
T234	0	1377	0	0
T235	0	73	0	0
T236	0	3932	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7281087	0	0
T12	3346	1346	0	0
T13	11876	9467	0	0
T24	526	126	0	0
T25	715	315	0	0
T26	678	278	0	0
T27	4565	4165	0	0
T34	5421	5021	0	0
T35	12415	12015	0	0
T36	3492	461	0	0
T69	697	297	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7281087	0	0
T12	3346	1346	0	0
T13	11876	9467	0	0
T24	526	126	0	0
T25	715	315	0	0
T26	678	278	0	0
T27	4565	4165	0	0
T34	5421	5021	0	0
T35	12415	12015	0	0
T36	3492	461	0	0
T69	697	297	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	610	0	0
T12	3346	0	0	0
T13	11876	0	0	0
T20	0	20	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	0	13	0	0
T35	12415	9	0	0
T36	3492	0	0	0
T40	0	14	0	0
T65	0	5	0	0
T69	697	0	0	0
T115	0	21	0	0
T116	0	21	0	0
T234	0	11	0	0
T235	0	10	0	0
T236	0	28	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T34,T35,T13
1	Covered	T34,T35,T36

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T13
1	0	Covered	T34,T35,T36
1	1	Covered	T34,T35,T36

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T13,T29,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T34,T35,T36	VC_COV_UNR
1	Covered	T13,T29,T20

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T13,T29,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T35,T13,T15
1	0	Covered	T34,T35,T36
1	1	Covered	T13,T29,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T29,T20
0	1	Covered	T21,T108,T203
1	0	Covered	T67,T68

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T29,T20
0	1	Covered	T13,T20,T52
1	0	Covered	T68

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T29,T20
1	-	Covered	T13,T20,T52

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T13,T29,T20
0	1	Covered	T13,T29,T20
0	0	Excluded	T34,T35,T36	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T29,T20
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T13,T29,T20
IdleSt	0	-	-	-	-	-	-	Covered	T34,T35,T36
DebounceSt	-	1	-	-	-	-	-	Covered	T67,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T29,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T29,T21,T52
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T29,T20
DetectSt	-	-	-	-	1	-	-	Covered	T21,T108,T203
DetectSt	-	-	-	-	0	1	-	Covered	T13,T29,T20
DetectSt	-	-	-	-	0	0	-	Covered	T13,T29,T20
StableSt	-	-	-	-	-	-	1	Covered	T13,T20,T52
StableSt	-	-	-	-	-	-	0	Covered	T13,T29,T20
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7945094	893	0	0
CntIncr_A	7945094	52552	0	0
CntNoWrap_A	7945094	7277837	0	0
DetectStDropOut_A	7945094	51	0	0
DetectedOut_A	7945094	12325	0	0
DetectedPulseOut_A	7945094	368	0	0
DisabledIdleSt_A	7945094	6926325	0	0
DisabledNoDetection_A	7945094	6928033	0	0
EnterDebounceSt_A	7945094	472	0	0
EnterDetectSt_A	7945094	424	0	0
EnterStableSt_A	7945094	368	0	0
PulseIsPulse_A	7945094	368	0	0
StayInStableSt	7945094	11926	0	0
gen_high_level_sva.HighLevelEvent_A	7945094	7281087	0	0
gen_not_sticky_sva.StableStDropOut_A	7945094	332	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	893	0	0
T13	11876	10	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T20	0	10	0	0
T21	0	24	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	3	0	0
T42	0	2	0	0
T43	0	14	0	0
T45	0	4	0	0
T52	0	25	0	0
T56	402	0	0	0
T116	0	2	0	0
T129	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	52552	0	0
T13	11876	705	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T20	0	410	0	0
T21	0	1477	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	123	0	0
T42	0	170	0	0
T43	0	336	0	0
T45	0	154	0	0
T52	0	1046	0	0
T56	402	0	0	0
T116	0	77	0	0
T129	0	83	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7277837	0	0
T12	3346	1342	0	0
T13	11876	9451	0	0
T24	526	125	0	0
T25	715	314	0	0
T26	678	277	0	0
T27	4565	4164	0	0
T34	5421	5020	0	0
T35	12415	12014	0	0
T36	3492	454	0	0
T69	697	296	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	51	0	0
T21	13600	11	0	0
T50	9079	0	0	0
T51	1020	0	0	0
T59	1120	0	0	0
T82	18777	0	0	0
T108	0	6	0	0
T120	2373	0	0	0
T132	522	0	0	0
T133	419	0	0	0
T134	522	0	0	0
T135	503	0	0	0
T155	0	3	0	0
T203	0	10	0	0
T243	0	8	0	0
T244	0	1	0	0
T245	0	11	0	0
T246	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	12325	0	0
T13	11876	143	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T20	0	677	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	73	0	0
T42	0	16	0	0
T43	0	145	0	0
T45	0	37	0	0
T52	0	64	0	0
T56	402	0	0	0
T116	0	210	0	0
T129	0	68	0	0
T238	0	52	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	368	0	0
T13	11876	5	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T20	0	5	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	1	0	0
T42	0	1	0	0
T43	0	7	0	0
T45	0	2	0	0
T52	0	12	0	0
T56	402	0	0	0
T116	0	1	0	0
T129	0	1	0	0
T238	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	6926325	0	0
T12	3346	1342	0	0
T13	11876	4745	0	0
T24	526	125	0	0
T25	715	314	0	0
T26	678	277	0	0
T27	4565	4164	0	0
T34	5421	5020	0	0
T35	12415	10664	0	0
T36	3492	454	0	0
T69	697	296	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	6928033	0	0
T12	3346	1346	0	0
T13	11876	4749	0	0
T24	526	126	0	0
T25	715	315	0	0
T26	678	278	0	0
T27	4565	4165	0	0
T34	5421	5021	0	0
T35	12415	10665	0	0
T36	3492	461	0	0
T69	697	297	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	472	0	0
T13	11876	5	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T20	0	5	0	0
T21	0	13	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	2	0	0
T42	0	1	0	0
T43	0	7	0	0
T45	0	2	0	0
T52	0	13	0	0
T56	402	0	0	0
T116	0	1	0	0
T129	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	424	0	0
T13	11876	5	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T20	0	5	0	0
T21	0	11	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	1	0	0
T42	0	1	0	0
T43	0	7	0	0
T45	0	2	0	0
T52	0	12	0	0
T56	402	0	0	0
T116	0	1	0	0
T129	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	368	0	0
T13	11876	5	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T20	0	5	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	1	0	0
T42	0	1	0	0
T43	0	7	0	0
T45	0	2	0	0
T52	0	12	0	0
T56	402	0	0	0
T116	0	1	0	0
T129	0	1	0	0
T238	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	368	0	0
T13	11876	5	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T20	0	5	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	1	0	0
T42	0	1	0	0
T43	0	7	0	0
T45	0	2	0	0
T52	0	12	0	0
T56	402	0	0	0
T116	0	1	0	0
T129	0	1	0	0
T238	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	11926	0	0
T13	11876	138	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T20	0	670	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	71	0	0
T42	0	15	0	0
T43	0	138	0	0
T45	0	35	0	0
T52	0	52	0	0
T56	402	0	0	0
T116	0	209	0	0
T129	0	67	0	0
T238	0	51	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7281087	0	0
T12	3346	1346	0	0
T13	11876	9467	0	0
T24	526	126	0	0
T25	715	315	0	0
T26	678	278	0	0
T27	4565	4165	0	0
T34	5421	5021	0	0
T35	12415	12015	0	0
T36	3492	461	0	0
T69	697	297	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	332	0	0
T13	11876	5	0	0
T14	1188	0	0	0
T15	13088	0	0	0
T20	0	3	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T29	25174	0	0	0
T42	0	1	0	0
T43	0	7	0	0
T45	0	2	0	0
T52	0	12	0	0
T56	402	0	0	0
T116	0	1	0	0
T129	0	1	0	0
T238	0	1	0	0
T247	0	1	0	0