Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T34,T35,T27
1	Covered	T34,T35,T36

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T34,T35,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T34,T35,T27

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T34,T35,T27

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T27
1	0	Covered	T29,T20,T44
1	1	Covered	T34,T35,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T34,T35,T27
0	1	Covered	T34,T27,T29
1	0	Covered	T29,T115,T232

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T35,T20,T44
0	1	Covered	T35,T20,T44
1	0	Covered	T73

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T35,T20,T44
1	-	Covered	T35,T20,T44

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T34,T35,T27
0	1	Covered	T34,T35,T27
0	0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T27
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T34,T35,T27
IdleSt	0	-	-	-	-	-	-	Covered	T34,T35,T27
DebounceSt	-	1	-	-	-	-	-	Covered	T67,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T34,T35,T27
DebounceSt	-	0	1	0	-	-	-	Covered	T35,T67,T68
DebounceSt	-	0	0	-	-	-	-	Covered	T34,T35,T27
DetectSt	-	-	-	-	1	-	-	Covered	T34,T27,T29
DetectSt	-	-	-	-	0	1	-	Covered	T35,T20,T44
DetectSt	-	-	-	-	0	0	-	Covered	T34,T35,T27
StableSt	-	-	-	-	-	-	1	Covered	T35,T20,T44
StableSt	-	-	-	-	-	-	0	Covered	T35,T20,T44
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7945094	2733	0	0
CntIncr_A	7945094	97139	0	0
CntNoWrap_A	7945094	7275997	0	0
DetectStDropOut_A	7945094	438	0	0
DetectedOut_A	7945094	76307	0	0
DetectedPulseOut_A	7945094	797	0	0
DisabledIdleSt_A	7945094	6806282	0	0
DisabledNoDetection_A	7945094	6808458	0	0
EnterDebounceSt_A	7945094	1394	0	0
EnterDetectSt_A	7945094	1341	0	0
EnterStableSt_A	7945094	797	0	0
PulseIsPulse_A	7945094	797	0	0
StayInStableSt	7945094	75423	0	0
gen_high_event_sva.HighLevelEvent_A	7945094	7281087	0	0
gen_high_level_sva.HighLevelEvent_A	7945094	7281087	0	0
gen_not_sticky_sva.StableStDropOut_A	7945094	709	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	2733	0	0
T12	3346	0	0	0
T13	11876	0	0	0
T20	0	22	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	38	0	0
T29	0	32	0	0
T34	5421	16	0	0
T35	12415	33	0	0
T36	3492	0	0	0
T40	0	28	0	0
T44	0	20	0	0
T53	0	22	0	0
T69	697	0	0	0
T82	0	10	0	0
T116	0	46	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	97139	0	0
T12	3346	0	0	0
T13	11876	0	0	0
T20	0	825	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	743	0	0
T29	0	1841	0	0
T34	5421	445	0	0
T35	12415	4507	0	0
T36	3492	0	0	0
T40	0	1218	0	0
T44	0	360	0	0
T53	0	517	0	0
T69	697	0	0	0
T82	0	1611	0	0
T116	0	1035	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7275997	0	0
T12	3346	1342	0	0
T13	11876	9461	0	0
T24	526	125	0	0
T25	715	314	0	0
T26	678	277	0	0
T27	4565	4126	0	0
T34	5421	5004	0	0
T35	12415	11981	0	0
T36	3492	454	0	0
T69	697	296	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	438	0	0
T12	3346	0	0	0
T13	11876	0	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	19	0	0
T29	0	5	0	0
T34	5421	8	0	0
T35	12415	0	0	0
T36	3492	0	0	0
T69	697	0	0	0
T82	0	5	0	0
T88	0	9	0	0
T89	0	24	0	0
T92	0	13	0	0
T115	0	13	0	0
T233	0	3	0	0
T248	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	76307	0	0
T12	3346	0	0	0
T13	11876	0	0	0
T20	0	1206	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T35	12415	2259	0	0
T36	3492	0	0	0
T40	0	783	0	0
T44	0	1076	0	0
T53	0	1945	0	0
T69	697	0	0	0
T71	0	6505	0	0
T90	0	1225	0	0
T116	0	2486	0	0
T234	0	1418	0	0
T235	0	499	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	797	0	0
T12	3346	0	0	0
T13	11876	0	0	0
T20	0	11	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T35	12415	14	0	0
T36	3492	0	0	0
T40	0	14	0	0
T44	0	10	0	0
T53	0	11	0	0
T69	697	0	0	0
T71	0	25	0	0
T90	0	6	0	0
T116	0	23	0	0
T234	0	18	0	0
T235	0	25	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	6806282	0	0
T12	3346	1342	0	0
T13	11876	9461	0	0
T24	526	125	0	0
T25	715	314	0	0
T26	678	277	0	0
T27	4565	2015	0	0
T34	5421	2014	0	0
T35	12415	2015	0	0
T36	3492	454	0	0
T69	697	296	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	6808458	0	0
T12	3346	1346	0	0
T13	11876	9467	0	0
T24	526	126	0	0
T25	715	315	0	0
T26	678	278	0	0
T27	4565	2015	0	0
T34	5421	2014	0	0
T35	12415	2015	0	0
T36	3492	461	0	0
T69	697	297	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	1394	0	0
T12	3346	0	0	0
T13	11876	0	0	0
T20	0	11	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	19	0	0
T29	0	16	0	0
T34	5421	8	0	0
T35	12415	20	0	0
T36	3492	0	0	0
T40	0	14	0	0
T44	0	10	0	0
T53	0	11	0	0
T69	697	0	0	0
T82	0	5	0	0
T116	0	23	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	1341	0	0
T12	3346	0	0	0
T13	11876	0	0	0
T20	0	11	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	19	0	0
T29	0	16	0	0
T34	5421	8	0	0
T35	12415	14	0	0
T36	3492	0	0	0
T40	0	14	0	0
T44	0	10	0	0
T53	0	11	0	0
T69	697	0	0	0
T82	0	5	0	0
T116	0	23	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	797	0	0
T12	3346	0	0	0
T13	11876	0	0	0
T20	0	11	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T35	12415	14	0	0
T36	3492	0	0	0
T40	0	14	0	0
T44	0	10	0	0
T53	0	11	0	0
T69	697	0	0	0
T71	0	25	0	0
T90	0	6	0	0
T116	0	23	0	0
T234	0	18	0	0
T235	0	25	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	797	0	0
T12	3346	0	0	0
T13	11876	0	0	0
T20	0	11	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T35	12415	14	0	0
T36	3492	0	0	0
T40	0	14	0	0
T44	0	10	0	0
T53	0	11	0	0
T69	697	0	0	0
T71	0	25	0	0
T90	0	6	0	0
T116	0	23	0	0
T234	0	18	0	0
T235	0	25	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	75423	0	0
T12	3346	0	0	0
T13	11876	0	0	0
T20	0	1193	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T35	12415	2245	0	0
T36	3492	0	0	0
T40	0	769	0	0
T44	0	1063	0	0
T53	0	1931	0	0
T69	697	0	0	0
T71	0	6478	0	0
T90	0	1219	0	0
T116	0	2461	0	0
T234	0	1398	0	0
T235	0	474	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7281087	0	0
T12	3346	1346	0	0
T13	11876	9467	0	0
T24	526	126	0	0
T25	715	315	0	0
T26	678	278	0	0
T27	4565	4165	0	0
T34	5421	5021	0	0
T35	12415	12015	0	0
T36	3492	461	0	0
T69	697	297	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7281087	0	0
T12	3346	1346	0	0
T13	11876	9467	0	0
T24	526	126	0	0
T25	715	315	0	0
T26	678	278	0	0
T27	4565	4165	0	0
T34	5421	5021	0	0
T35	12415	12015	0	0
T36	3492	461	0	0
T69	697	297	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	709	0	0
T12	3346	0	0	0
T13	11876	0	0	0
T20	0	9	0	0
T24	526	0	0	0
T25	715	0	0	0
T26	678	0	0	0
T27	4565	0	0	0
T28	411	0	0	0
T35	12415	14	0	0
T36	3492	0	0	0
T40	0	14	0	0
T44	0	7	0	0
T53	0	8	0	0
T69	697	0	0	0
T71	0	23	0	0
T90	0	6	0	0
T116	0	21	0	0
T234	0	16	0	0
T235	0	25	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T34,T35,T27
1	Covered	T34,T35,T36

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T27
1	0	Covered	T34,T35,T36
1	1	Covered	T34,T35,T36

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T15,T20,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T34,T35,T36	VC_COV_UNR
1	Covered	T15,T20,T21

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T15,T20,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T35,T15,T20
1	0	Covered	T34,T35,T36
1	1	Covered	T15,T20,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T20,T21
0	1	Covered	T45,T129,T48
1	0	Covered	T67,T68

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T20,T21
0	1	Covered	T15,T20,T21
1	0	Covered	T67,T68

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T15,T20,T21
1	-	Covered	T15,T20,T21

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T15,T20,T21
0	1	Covered	T15,T20,T21
0	0	Excluded	T34,T35,T36	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T20,T21
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T15,T20,T21
IdleSt	0	-	-	-	-	-	-	Covered	T34,T35,T36
DebounceSt	-	1	-	-	-	-	-	Covered	T67,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T20,T21
DebounceSt	-	0	1	0	-	-	-	Covered	T53,T43,T45
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T20,T21
DetectSt	-	-	-	-	1	-	-	Covered	T45,T129,T48
DetectSt	-	-	-	-	0	1	-	Covered	T15,T20,T21
DetectSt	-	-	-	-	0	0	-	Covered	T15,T20,T21
StableSt	-	-	-	-	-	-	1	Covered	T15,T20,T21
StableSt	-	-	-	-	-	-	0	Covered	T15,T20,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T34,T35,T36

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7945094	852	0	0
CntIncr_A	7945094	47946	0	0
CntNoWrap_A	7945094	7277878	0	0
DetectStDropOut_A	7945094	74	0	0
DetectedOut_A	7945094	15176	0	0
DetectedPulseOut_A	7945094	325	0	0
DisabledIdleSt_A	7945094	6910556	0	0
DisabledNoDetection_A	7945094	6912247	0	0
EnterDebounceSt_A	7945094	451	0	0
EnterDetectSt_A	7945094	404	0	0
EnterStableSt_A	7945094	325	0	0
PulseIsPulse_A	7945094	325	0	0
StayInStableSt	7945094	14819	0	0
gen_high_level_sva.HighLevelEvent_A	7945094	7281087	0	0
gen_not_sticky_sva.StableStDropOut_A	7945094	287	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	852	0	0
T15	13088	18	0	0
T16	488	0	0	0
T17	114965	0	0	0
T18	2225	0	0	0
T20	29027	4	0	0
T21	0	6	0	0
T29	25174	0	0	0
T42	0	16	0	0
T43	0	11	0	0
T44	0	6	0	0
T45	0	5	0	0
T52	0	10	0	0
T53	0	7	0	0
T54	0	2	0	0
T56	402	0	0	0
T57	422	0	0	0
T58	615	0	0	0
T117	8410	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	47946	0	0
T15	13088	1422	0	0
T16	488	0	0	0
T17	114965	0	0	0
T18	2225	0	0	0
T20	29027	116	0	0
T21	0	267	0	0
T29	25174	0	0	0
T42	0	752	0	0
T43	0	296	0	0
T44	0	207	0	0
T45	0	216	0	0
T52	0	350	0	0
T53	0	246	0	0
T54	0	112	0	0
T56	402	0	0	0
T57	422	0	0	0
T58	615	0	0	0
T117	8410	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7277878	0	0
T12	3346	1342	0	0
T13	11876	9461	0	0
T24	526	125	0	0
T25	715	314	0	0
T26	678	277	0	0
T27	4565	4164	0	0
T34	5421	5020	0	0
T35	12415	12014	0	0
T36	3492	454	0	0
T69	697	296	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	74	0	0
T45	163943	2	0	0
T47	1027	0	0	0
T48	0	1	0	0
T61	7777	0	0	0
T62	1883	0	0	0
T70	0	6	0	0
T78	0	10	0	0
T93	0	2	0	0
T103	522	0	0	0
T104	505	0	0	0
T105	497	0	0	0
T106	616	0	0	0
T128	440	0	0	0
T129	16674	3	0	0
T239	0	2	0	0
T240	0	2	0	0
T249	0	6	0	0
T250	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	15176	0	0
T15	13088	165	0	0
T16	488	0	0	0
T17	114965	0	0	0
T18	2225	0	0	0
T20	29027	320	0	0
T21	0	110	0	0
T29	25174	0	0	0
T42	0	740	0	0
T43	0	55	0	0
T44	0	136	0	0
T52	0	92	0	0
T53	0	210	0	0
T54	0	47	0	0
T56	402	0	0	0
T57	422	0	0	0
T58	615	0	0	0
T116	0	474	0	0
T117	8410	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	325	0	0
T15	13088	9	0	0
T16	488	0	0	0
T17	114965	0	0	0
T18	2225	0	0	0
T20	29027	2	0	0
T21	0	3	0	0
T29	25174	0	0	0
T42	0	8	0	0
T43	0	5	0	0
T44	0	3	0	0
T52	0	5	0	0
T53	0	3	0	0
T54	0	1	0	0
T56	402	0	0	0
T57	422	0	0	0
T58	615	0	0	0
T116	0	2	0	0
T117	8410	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	6910556	0	0
T12	3346	1342	0	0
T13	11876	9461	0	0
T24	526	125	0	0
T25	715	314	0	0
T26	678	277	0	0
T27	4565	4164	0	0
T34	5421	5020	0	0
T35	12415	9755	0	0
T36	3492	454	0	0
T69	697	296	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	6912247	0	0
T12	3346	1346	0	0
T13	11876	9467	0	0
T24	526	126	0	0
T25	715	315	0	0
T26	678	278	0	0
T27	4565	4165	0	0
T34	5421	5021	0	0
T35	12415	9756	0	0
T36	3492	461	0	0
T69	697	297	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	451	0	0
T15	13088	9	0	0
T16	488	0	0	0
T17	114965	0	0	0
T18	2225	0	0	0
T20	29027	2	0	0
T21	0	3	0	0
T29	25174	0	0	0
T42	0	8	0	0
T43	0	6	0	0
T44	0	3	0	0
T45	0	3	0	0
T52	0	5	0	0
T53	0	4	0	0
T54	0	1	0	0
T56	402	0	0	0
T57	422	0	0	0
T58	615	0	0	0
T117	8410	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	404	0	0
T15	13088	9	0	0
T16	488	0	0	0
T17	114965	0	0	0
T18	2225	0	0	0
T20	29027	2	0	0
T21	0	3	0	0
T29	25174	0	0	0
T42	0	8	0	0
T43	0	5	0	0
T44	0	3	0	0
T45	0	2	0	0
T52	0	5	0	0
T53	0	3	0	0
T54	0	1	0	0
T56	402	0	0	0
T57	422	0	0	0
T58	615	0	0	0
T117	8410	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	325	0	0
T15	13088	9	0	0
T16	488	0	0	0
T17	114965	0	0	0
T18	2225	0	0	0
T20	29027	2	0	0
T21	0	3	0	0
T29	25174	0	0	0
T42	0	8	0	0
T43	0	5	0	0
T44	0	3	0	0
T52	0	5	0	0
T53	0	3	0	0
T54	0	1	0	0
T56	402	0	0	0
T57	422	0	0	0
T58	615	0	0	0
T116	0	2	0	0
T117	8410	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	325	0	0
T15	13088	9	0	0
T16	488	0	0	0
T17	114965	0	0	0
T18	2225	0	0	0
T20	29027	2	0	0
T21	0	3	0	0
T29	25174	0	0	0
T42	0	8	0	0
T43	0	5	0	0
T44	0	3	0	0
T52	0	5	0	0
T53	0	3	0	0
T54	0	1	0	0
T56	402	0	0	0
T57	422	0	0	0
T58	615	0	0	0
T116	0	2	0	0
T117	8410	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	14819	0	0
T15	13088	156	0	0
T16	488	0	0	0
T17	114965	0	0	0
T18	2225	0	0	0
T20	29027	318	0	0
T21	0	107	0	0
T29	25174	0	0	0
T42	0	732	0	0
T43	0	50	0	0
T44	0	133	0	0
T52	0	87	0	0
T53	0	207	0	0
T54	0	46	0	0
T56	402	0	0	0
T57	422	0	0	0
T58	615	0	0	0
T116	0	471	0	0
T117	8410	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	7281087	0	0
T12	3346	1346	0	0
T13	11876	9467	0	0
T24	526	126	0	0
T25	715	315	0	0
T26	678	278	0	0
T27	4565	4165	0	0
T34	5421	5021	0	0
T35	12415	12015	0	0
T36	3492	461	0	0
T69	697	297	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7945094	287	0	0
T15	13088	9	0	0
T16	488	0	0	0
T17	114965	0	0	0
T18	2225	0	0	0
T20	29027	2	0	0
T21	0	3	0	0
T29	25174	0	0	0
T42	0	8	0	0
T43	0	5	0	0
T44	0	3	0	0
T52	0	5	0	0
T53	0	3	0	0
T54	0	1	0	0
T56	402	0	0	0
T57	422	0	0	0
T58	615	0	0	0
T116	0	1	0	0
T117	8410	0	0	0