Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T40,T41,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T40,T41,T13
1	0	Covered	T40,T41,T13
1	1	Covered	T40,T41,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T29,T90,T79

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T40,T41,T13	VC_COV_UNR
1	Covered	T29,T90,T79

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T29,T90,T79

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T29,T90,T79
1	0	Covered	T40,T41,T13
1	1	Covered	T29,T90,T79

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T29,T90,T79
0	1	Covered	T87
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T29,T90,T79
0	1	Covered	T29,T90,T79
1	0	Covered	T85

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T29,T90,T79
1	-	Covered	T29,T90,T79

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4
DetectSt	168	Covered	T4
IdleSt	163	Covered	T4
StableSt	191	Covered	T4

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4
DebounceSt->IdleSt	163	Covered	T4
DetectSt->IdleSt	186	Covered	T4
DetectSt->StableSt	191	Covered	T4
IdleSt->DebounceSt	148	Covered	T4
StableSt->IdleSt	206	Covered	T4

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T29,T90,T79
0	1	Covered	T29,T90,T79
0	0	Excluded	T40,T41,T13	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T29,T90,T79
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T29,T90,T79
IdleSt	0	-	-	-	-	-	-	Covered	T40,T41,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T84
DebounceSt	-	0	1	1	-	-	-	Covered	T29,T90,T79
DebounceSt	-	0	1	0	-	-	-	Covered	T45,T99,T100
DebounceSt	-	0	0	-	-	-	-	Covered	T29,T90,T79
DetectSt	-	-	-	-	1	-	-	Covered	T87
DetectSt	-	-	-	-	0	1	-	Covered	T29,T90,T79
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T29,T90,T79
StableSt	-	-	-	-	-	-	0	Covered	T29,T90,T79
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7780736	255	0	0
CntIncr_A	7780736	298837	0	0
CntNoWrap_A	7780736	7116270	0	0
DetectStDropOut_A	7780736	1	0	0
DetectedOut_A	7780736	755	0	0
DetectedPulseOut_A	7780736	115	0	0
DisabledIdleSt_A	7780736	6811669	0	0
DisabledNoDetection_A	7780736	6813932	0	0
EnterDebounceSt_A	7780736	147	0	0
EnterDetectSt_A	7780736	116	0	0
EnterStableSt_A	7780736	115	0	0
PulseIsPulse_A	7780736	115	0	0
StayInStableSt	7780736	640	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7780736	6979	0	0
gen_low_level_sva.LowLevelEvent_A	7780736	7118843	0	0
gen_not_sticky_sva.StableStDropOut_A	7780736	114	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	255	0	0
T16	23425	0	0	0
T21	0	2	0	0
T29	586	2	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T45	0	13	0	0
T63	0	4	0	0
T66	494	0	0	0
T67	422	0	0	0
T68	631	0	0	0
T69	510	0	0	0
T79	0	2	0	0
T90	0	2	0	0
T99	0	1	0	0
T100	0	1	0	0
T101	0	4	0	0
T103	0	4	0	0
T104	502	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	298837	0	0
T16	23425	0	0	0
T21	0	25566	0	0
T29	586	17	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T45	0	38710	0	0
T63	0	137	0	0
T66	494	0	0	0
T67	422	0	0	0
T68	631	0	0	0
T69	510	0	0	0
T79	0	53	0	0
T90	0	90	0	0
T99	0	25900	0	0
T100	0	21	0	0
T101	0	93	0	0
T103	0	144	0	0
T104	502	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7116270	0	0
T13	2154	551	0	0
T14	569	168	0	0
T15	27039	26570	0	0
T26	99226	98825	0	0
T27	502	101	0	0
T28	659	258	0	0
T29	586	183	0	0
T30	548	147	0	0
T40	46119	45682	0	0
T41	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	1	0	0
T87	745	1	0	0
T113	8000	0	0	0
T127	5917	0	0	0
T128	423	0	0	0
T129	404	0	0	0
T130	422	0	0	0
T131	431	0	0	0
T132	6581	0	0	0
T133	502	0	0	0
T134	534	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	755	0	0
T16	23425	0	0	0
T21	0	6	0	0
T29	586	9	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T45	0	41	0	0
T63	0	22	0	0
T66	494	0	0	0
T67	422	0	0	0
T68	631	0	0	0
T69	510	0	0	0
T79	0	9	0	0
T90	0	10	0	0
T101	0	19	0	0
T103	0	8	0	0
T104	502	0	0	0
T137	0	11	0	0
T138	0	12	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	115	0	0
T16	23425	0	0	0
T21	0	1	0	0
T29	586	1	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T45	0	6	0	0
T63	0	2	0	0
T66	494	0	0	0
T67	422	0	0	0
T68	631	0	0	0
T69	510	0	0	0
T79	0	1	0	0
T90	0	1	0	0
T101	0	2	0	0
T103	0	2	0	0
T104	502	0	0	0
T137	0	1	0	0
T138	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	6811669	0	0
T13	2154	551	0	0
T14	569	168	0	0
T15	27039	26570	0	0
T26	99226	98825	0	0
T27	502	101	0	0
T28	659	258	0	0
T29	586	128	0	0
T30	548	147	0	0
T40	46119	45682	0	0
T41	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	6813932	0	0
T13	2154	554	0	0
T14	569	169	0	0
T15	27039	26581	0	0
T26	99226	98826	0	0
T27	502	102	0	0
T28	659	259	0	0
T29	586	129	0	0
T30	548	148	0	0
T40	46119	45688	0	0
T41	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	147	0	0
T16	23425	0	0	0
T21	0	2	0	0
T29	586	1	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T45	0	8	0	0
T63	0	2	0	0
T66	494	0	0	0
T67	422	0	0	0
T68	631	0	0	0
T69	510	0	0	0
T79	0	1	0	0
T90	0	2	0	0
T99	0	1	0	0
T100	0	1	0	0
T101	0	2	0	0
T103	0	2	0	0
T104	502	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	116	0	0
T16	23425	0	0	0
T21	0	1	0	0
T29	586	1	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T45	0	6	0	0
T63	0	2	0	0
T66	494	0	0	0
T67	422	0	0	0
T68	631	0	0	0
T69	510	0	0	0
T79	0	1	0	0
T90	0	1	0	0
T101	0	2	0	0
T103	0	2	0	0
T104	502	0	0	0
T137	0	1	0	0
T138	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	115	0	0
T16	23425	0	0	0
T21	0	1	0	0
T29	586	1	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T45	0	6	0	0
T63	0	2	0	0
T66	494	0	0	0
T67	422	0	0	0
T68	631	0	0	0
T69	510	0	0	0
T79	0	1	0	0
T90	0	1	0	0
T101	0	2	0	0
T103	0	2	0	0
T104	502	0	0	0
T137	0	1	0	0
T138	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	115	0	0
T16	23425	0	0	0
T21	0	1	0	0
T29	586	1	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T45	0	6	0	0
T63	0	2	0	0
T66	494	0	0	0
T67	422	0	0	0
T68	631	0	0	0
T69	510	0	0	0
T79	0	1	0	0
T90	0	1	0	0
T101	0	2	0	0
T103	0	2	0	0
T104	502	0	0	0
T137	0	1	0	0
T138	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	640	0	0
T16	23425	0	0	0
T21	0	5	0	0
T29	586	8	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T45	0	35	0	0
T63	0	20	0	0
T66	494	0	0	0
T67	422	0	0	0
T68	631	0	0	0
T69	510	0	0	0
T79	0	8	0	0
T90	0	9	0	0
T101	0	17	0	0
T103	0	6	0	0
T104	502	0	0	0
T137	0	10	0	0
T138	0	11	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	6979	0	0
T13	2154	5	0	0
T14	569	0	0	0
T15	27039	11	0	0
T16	0	31	0	0
T26	99226	0	0	0
T27	502	4	0	0
T28	659	0	0	0
T29	586	3	0	0
T30	548	0	0	0
T31	0	6	0	0
T32	0	27	0	0
T40	46119	28	0	0
T41	522	4	0	0
T66	0	7	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7118843	0	0
T13	2154	554	0	0
T14	569	169	0	0
T15	27039	26581	0	0
T26	99226	98826	0	0
T27	502	102	0	0
T28	659	259	0	0
T29	586	186	0	0
T30	548	148	0	0
T40	46119	45688	0	0
T41	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	114	0	0
T16	23425	0	0	0
T21	0	1	0	0
T29	586	1	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T45	0	6	0	0
T63	0	2	0	0
T66	494	0	0	0
T67	422	0	0	0
T68	631	0	0	0
T69	510	0	0	0
T79	0	1	0	0
T90	0	1	0	0
T101	0	2	0	0
T103	0	2	0	0
T104	502	0	0	0
T137	0	1	0	0
T138	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T40,T41,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T40,T41,T13
1	0	Covered	T40,T41,T13
1	1	Covered	T40,T41,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T17,T18,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T40,T41,T13	VC_COV_UNR
1	Covered	T17,T18,T44

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T17,T18,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T44
1	0	Covered	T40,T41,T13
1	1	Covered	T17,T18,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T17,T18,T44
0	1	Covered	T75,T97,T98
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T18,T44
0	1	Unreachable
1	0	Covered	T17,T18,T44

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4
DetectSt	168	Covered	T4
IdleSt	163	Covered	T4
StableSt	191	Covered	T4

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4
DebounceSt->IdleSt	163	Covered	T4
DetectSt->IdleSt	186	Covered	T4
DetectSt->StableSt	191	Covered	T4
IdleSt->DebounceSt	148	Covered	T4
StableSt->IdleSt	206	Covered	T4

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T17,T18,T44
0	1	Covered	T17,T18,T44
0	0	Excluded	T40,T41,T13	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T18,T44
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T17,T18,T44
IdleSt	0	-	-	-	-	-	-	Covered	T40,T41,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T84,T85
DebounceSt	-	0	1	1	-	-	-	Covered	T17,T18,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T44,T75,T76
DebounceSt	-	0	0	-	-	-	-	Covered	T17,T18,T44
DetectSt	-	-	-	-	1	-	-	Covered	T75,T97,T98
DetectSt	-	-	-	-	0	1	-	Covered	T17,T18,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T17,T18,T44
StableSt	-	-	-	-	-	-	0	Covered	T17,T18,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7780736	163	0	0
CntIncr_A	7780736	92339	0	0
CntNoWrap_A	7780736	7116362	0	0
DetectStDropOut_A	7780736	12	0	0
DetectedOut_A	7780736	266016	0	0
DetectedPulseOut_A	7780736	50	0	0
DisabledIdleSt_A	7780736	5578371	0	0
DisabledNoDetection_A	7780736	5580688	0	0
EnterDebounceSt_A	7780736	101	0	0
EnterDetectSt_A	7780736	62	0	0
EnterStableSt_A	7780736	50	0	0
PulseIsPulse_A	7780736	50	0	0
StayInStableSt	7780736	265966	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7780736	6979	0	0
gen_low_level_sva.LowLevelEvent_A	7780736	7118843	0	0
gen_sticky_sva.StableStDropOut_A	7780736	975290	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	163	0	0
T17	1648	4	0	0
T18	63755	2	0	0
T19	23904	0	0	0
T20	670	0	0	0
T44	0	3	0	0
T62	33073	0	0	0
T63	0	2	0	0
T70	445	0	0	0
T71	421	0	0	0
T72	0	2	0	0
T73	0	2	0	0
T74	0	4	0	0
T75	0	6	0	0
T76	0	10	0	0
T77	0	2	0	0
T78	502	0	0	0
T79	780	0	0	0
T80	496	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	92339	0	0
T17	1648	52	0	0
T18	63755	15	0	0
T19	23904	0	0	0
T20	670	0	0	0
T44	0	192	0	0
T62	33073	0	0	0
T63	0	85	0	0
T70	445	0	0	0
T71	421	0	0	0
T72	0	52	0	0
T73	0	52681	0	0
T74	0	46	0	0
T75	0	296	0	0
T76	0	980	0	0
T77	0	69	0	0
T78	502	0	0	0
T79	780	0	0	0
T80	496	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7116362	0	0
T13	2154	551	0	0
T14	569	168	0	0
T15	27039	26570	0	0
T26	99226	98825	0	0
T27	502	101	0	0
T28	659	258	0	0
T29	586	185	0	0
T30	548	147	0	0
T40	46119	45682	0	0
T41	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	12	0	0
T75	1593	1	0	0
T97	20197	2	0	0
T98	0	2	0	0
T103	760	0	0	0
T145	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0
T148	0	2	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	565	0	0	0
T152	8324	0	0	0
T153	406	0	0	0
T154	2288	0	0	0
T155	459	0	0	0
T156	426	0	0	0
T157	31877	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	266016	0	0
T17	1648	108	0	0
T18	63755	11	0	0
T19	23904	0	0	0
T20	670	0	0	0
T44	0	195	0	0
T62	33073	0	0	0
T63	0	420	0	0
T70	445	0	0	0
T71	421	0	0	0
T72	0	350	0	0
T73	0	206321	0	0
T74	0	194	0	0
T75	0	1	0	0
T77	0	91	0	0
T78	502	0	0	0
T79	780	0	0	0
T80	496	0	0	0
T140	0	249	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	50	0	0
T17	1648	2	0	0
T18	63755	1	0	0
T19	23904	0	0	0
T20	670	0	0	0
T44	0	1	0	0
T62	33073	0	0	0
T63	0	1	0	0
T70	445	0	0	0
T71	421	0	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	2	0	0
T75	0	1	0	0
T77	0	1	0	0
T78	502	0	0	0
T79	780	0	0	0
T80	496	0	0	0
T140	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	5578371	0	0
T13	2154	551	0	0
T14	569	168	0	0
T15	27039	26570	0	0
T26	99226	98825	0	0
T27	502	101	0	0
T28	659	258	0	0
T29	586	185	0	0
T30	548	147	0	0
T40	46119	45682	0	0
T41	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	5580688	0	0
T13	2154	554	0	0
T14	569	169	0	0
T15	27039	26581	0	0
T26	99226	98826	0	0
T27	502	102	0	0
T28	659	259	0	0
T29	586	186	0	0
T30	548	148	0	0
T40	46119	45688	0	0
T41	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	101	0	0
T17	1648	2	0	0
T18	63755	1	0	0
T19	23904	0	0	0
T20	670	0	0	0
T44	0	2	0	0
T62	33073	0	0	0
T63	0	1	0	0
T70	445	0	0	0
T71	421	0	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	2	0	0
T75	0	4	0	0
T76	0	10	0	0
T77	0	1	0	0
T78	502	0	0	0
T79	780	0	0	0
T80	496	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	62	0	0
T17	1648	2	0	0
T18	63755	1	0	0
T19	23904	0	0	0
T20	670	0	0	0
T44	0	1	0	0
T62	33073	0	0	0
T63	0	1	0	0
T70	445	0	0	0
T71	421	0	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	2	0	0
T75	0	2	0	0
T77	0	1	0	0
T78	502	0	0	0
T79	780	0	0	0
T80	496	0	0	0
T140	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	50	0	0
T17	1648	2	0	0
T18	63755	1	0	0
T19	23904	0	0	0
T20	670	0	0	0
T44	0	1	0	0
T62	33073	0	0	0
T63	0	1	0	0
T70	445	0	0	0
T71	421	0	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	2	0	0
T75	0	1	0	0
T77	0	1	0	0
T78	502	0	0	0
T79	780	0	0	0
T80	496	0	0	0
T140	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	50	0	0
T17	1648	2	0	0
T18	63755	1	0	0
T19	23904	0	0	0
T20	670	0	0	0
T44	0	1	0	0
T62	33073	0	0	0
T63	0	1	0	0
T70	445	0	0	0
T71	421	0	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	2	0	0
T75	0	1	0	0
T77	0	1	0	0
T78	502	0	0	0
T79	780	0	0	0
T80	496	0	0	0
T140	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	265966	0	0
T17	1648	106	0	0
T18	63755	10	0	0
T19	23904	0	0	0
T20	670	0	0	0
T44	0	194	0	0
T62	33073	0	0	0
T63	0	419	0	0
T70	445	0	0	0
T71	421	0	0	0
T72	0	349	0	0
T73	0	206320	0	0
T74	0	192	0	0
T77	0	90	0	0
T78	502	0	0	0
T79	780	0	0	0
T80	496	0	0	0
T140	0	248	0	0
T141	0	27	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	6979	0	0
T13	2154	5	0	0
T14	569	0	0	0
T15	27039	11	0	0
T16	0	31	0	0
T26	99226	0	0	0
T27	502	4	0	0
T28	659	0	0	0
T29	586	3	0	0
T30	548	0	0	0
T31	0	6	0	0
T32	0	27	0	0
T40	46119	28	0	0
T41	522	4	0	0
T66	0	7	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7118843	0	0
T13	2154	554	0	0
T14	569	169	0	0
T15	27039	26581	0	0
T26	99226	98826	0	0
T27	502	102	0	0
T28	659	259	0	0
T29	586	186	0	0
T30	548	148	0	0
T40	46119	45688	0	0
T41	522	122	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	975290	0	0
T17	1648	426	0	0
T18	63755	63284	0	0
T19	23904	0	0	0
T20	670	0	0	0
T44	0	243	0	0
T62	33073	0	0	0
T63	0	202263	0	0
T70	445	0	0	0
T71	421	0	0	0
T72	0	241	0	0
T73	0	63	0	0
T74	0	1114	0	0
T75	0	23	0	0
T77	0	89	0	0
T78	502	0	0	0
T79	780	0	0	0
T80	496	0	0	0
T140	0	155	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T41,T13,T27

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T40,T41,T13
1	0	Covered	T41,T13,T27
1	1	Covered	T41,T13,T27

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T17,T18,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T40,T41,T13	VC_COV_UNR
1	Covered	T17,T18,T44

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T17,T18,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T44
1	0	Covered	T41,T13,T27
1	1	Covered	T17,T18,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T18,T44,T72
0	1	Covered	T17,T75,T96
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T18,T44,T72
0	1	Unreachable
1	0	Covered	T18,T44,T72

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4
DetectSt	168	Covered	T4
IdleSt	163	Covered	T4
StableSt	191	Covered	T4

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4
DebounceSt->IdleSt	163	Covered	T4
DetectSt->IdleSt	186	Covered	T4
DetectSt->StableSt	191	Covered	T4
IdleSt->DebounceSt	148	Covered	T4
StableSt->IdleSt	206	Covered	T4

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T17,T18,T44
0	1	Covered	T17,T18,T44
0	0	Excluded	T40,T41,T13	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T18,T44
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T17,T18,T44
IdleSt	0	-	-	-	-	-	-	Covered	T41,T13,T27
DebounceSt	-	1	-	-	-	-	-	Covered	T84,T85
DebounceSt	-	0	1	1	-	-	-	Covered	T17,T18,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T17,T72,T63
DebounceSt	-	0	0	-	-	-	-	Covered	T17,T18,T44
DetectSt	-	-	-	-	1	-	-	Covered	T17,T75,T96
DetectSt	-	-	-	-	0	1	-	Covered	T18,T44,T72
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T18,T44,T72
StableSt	-	-	-	-	-	-	0	Covered	T18,T44,T72
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7780736	162	0	0
CntIncr_A	7780736	160342	0	0
CntNoWrap_A	7780736	7116363	0	0
DetectStDropOut_A	7780736	18	0	0
DetectedOut_A	7780736	137698	0	0
DetectedPulseOut_A	7780736	49	0	0
DisabledIdleSt_A	7780736	5578371	0	0
DisabledNoDetection_A	7780736	5580688	0	0
EnterDebounceSt_A	7780736	95	0	0
EnterDetectSt_A	7780736	67	0	0
EnterStableSt_A	7780736	49	0	0
PulseIsPulse_A	7780736	49	0	0
StayInStableSt	7780736	137649	0	0
gen_high_level_sva.HighLevelEvent_A	7780736	7118843	0	0
gen_sticky_sva.StableStDropOut_A	7780736	991167	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	162	0	0
T17	1648	8	0	0
T18	63755	2	0	0
T19	23904	0	0	0
T20	670	0	0	0
T44	0	2	0	0
T62	33073	0	0	0
T63	0	4	0	0
T70	445	0	0	0
T71	421	0	0	0
T72	0	3	0	0
T73	0	2	0	0
T74	0	4	0	0
T75	0	8	0	0
T76	0	6	0	0
T77	0	2	0	0
T78	502	0	0	0
T79	780	0	0	0
T80	496	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	160342	0	0
T17	1648	465	0	0
T18	63755	18	0	0
T19	23904	0	0	0
T20	670	0	0	0
T44	0	88	0	0
T62	33073	0	0	0
T63	0	124	0	0
T70	445	0	0	0
T71	421	0	0	0
T72	0	64	0	0
T73	0	61	0	0
T74	0	192	0	0
T75	0	152	0	0
T76	0	81	0	0
T77	0	60	0	0
T78	502	0	0	0
T79	780	0	0	0
T80	496	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7116363	0	0
T13	2154	551	0	0
T14	569	168	0	0
T15	27039	26570	0	0
T26	99226	98825	0	0
T27	502	101	0	0
T28	659	258	0	0
T29	586	185	0	0
T30	548	147	0	0
T40	46119	45682	0	0
T41	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	18	0	0
T17	1648	3	0	0
T18	63755	0	0	0
T19	23904	0	0	0
T20	670	0	0	0
T62	33073	0	0	0
T70	445	0	0	0
T71	421	0	0	0
T75	0	4	0	0
T78	502	0	0	0
T79	780	0	0	0
T80	496	0	0	0
T94	0	3	0	0
T96	0	1	0	0
T98	0	3	0	0
T158	0	2	0	0
T159	0	1	0	0
T160	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	137698	0	0
T18	63755	12	0	0
T19	23904	0	0	0
T20	670	0	0	0
T21	33629	0	0	0
T44	0	532	0	0
T62	33073	0	0	0
T71	421	0	0	0
T72	0	99	0	0
T73	0	213	0	0
T74	0	1000	0	0
T76	0	265	0	0
T77	0	153	0	0
T78	502	0	0	0
T79	780	0	0	0
T80	496	0	0	0
T141	0	78	0	0
T142	0	177	0	0
T143	0	260	0	0
T144	491	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	49	0	0
T18	63755	1	0	0
T19	23904	0	0	0
T20	670	0	0	0
T21	33629	0	0	0
T44	0	1	0	0
T62	33073	0	0	0
T71	421	0	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	2	0	0
T76	0	3	0	0
T77	0	1	0	0
T78	502	0	0	0
T79	780	0	0	0
T80	496	0	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0
T144	491	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	5578371	0	0
T13	2154	551	0	0
T14	569	168	0	0
T15	27039	26570	0	0
T26	99226	98825	0	0
T27	502	101	0	0
T28	659	258	0	0
T29	586	185	0	0
T30	548	147	0	0
T40	46119	45682	0	0
T41	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	5580688	0	0
T13	2154	554	0	0
T14	569	169	0	0
T15	27039	26581	0	0
T26	99226	98826	0	0
T27	502	102	0	0
T28	659	259	0	0
T29	586	186	0	0
T30	548	148	0	0
T40	46119	45688	0	0
T41	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	95	0	0
T17	1648	5	0	0
T18	63755	1	0	0
T19	23904	0	0	0
T20	670	0	0	0
T44	0	1	0	0
T62	33073	0	0	0
T63	0	4	0	0
T70	445	0	0	0
T71	421	0	0	0
T72	0	2	0	0
T73	0	1	0	0
T74	0	2	0	0
T75	0	4	0	0
T76	0	3	0	0
T77	0	1	0	0
T78	502	0	0	0
T79	780	0	0	0
T80	496	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	67	0	0
T17	1648	3	0	0
T18	63755	1	0	0
T19	23904	0	0	0
T20	670	0	0	0
T44	0	1	0	0
T62	33073	0	0	0
T70	445	0	0	0
T71	421	0	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	2	0	0
T75	0	4	0	0
T76	0	3	0	0
T77	0	1	0	0
T78	502	0	0	0
T79	780	0	0	0
T80	496	0	0	0
T141	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	49	0	0
T18	63755	1	0	0
T19	23904	0	0	0
T20	670	0	0	0
T21	33629	0	0	0
T44	0	1	0	0
T62	33073	0	0	0
T71	421	0	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	2	0	0
T76	0	3	0	0
T77	0	1	0	0
T78	502	0	0	0
T79	780	0	0	0
T80	496	0	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0
T144	491	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	49	0	0
T18	63755	1	0	0
T19	23904	0	0	0
T20	670	0	0	0
T21	33629	0	0	0
T44	0	1	0	0
T62	33073	0	0	0
T71	421	0	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	2	0	0
T76	0	3	0	0
T77	0	1	0	0
T78	502	0	0	0
T79	780	0	0	0
T80	496	0	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0
T144	491	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	137649	0	0
T18	63755	11	0	0
T19	23904	0	0	0
T20	670	0	0	0
T21	33629	0	0	0
T44	0	531	0	0
T62	33073	0	0	0
T71	421	0	0	0
T72	0	98	0	0
T73	0	212	0	0
T74	0	998	0	0
T76	0	262	0	0
T77	0	152	0	0
T78	502	0	0	0
T79	780	0	0	0
T80	496	0	0	0
T141	0	77	0	0
T142	0	176	0	0
T143	0	259	0	0
T144	491	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7118843	0	0
T13	2154	554	0	0
T14	569	169	0	0
T15	27039	26581	0	0
T26	99226	98826	0	0
T27	502	102	0	0
T28	659	259	0	0
T29	586	186	0	0
T30	548	148	0	0
T40	46119	45688	0	0
T41	522	122	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	991167	0	0
T18	63755	63292	0	0
T19	23904	0	0	0
T20	670	0	0	0
T21	33629	0	0	0
T44	0	79	0	0
T62	33073	0	0	0
T71	421	0	0	0
T72	0	378	0	0
T73	0	258799	0	0
T74	0	171	0	0
T76	0	919	0	0
T77	0	43	0	0
T78	502	0	0	0
T79	780	0	0	0
T80	496	0	0	0
T141	0	78	0	0
T142	0	68	0	0
T143	0	86	0	0
T144	491	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T40,T41,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T17,T18,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T40,T41,T13	VC_COV_UNR
1	Covered	T17,T18,T44

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T17,T44,T63

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T44
1	0	Covered	T40,T41,T13
1	1	Covered	T17,T18,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T17,T44,T63
0	1	Covered	T17,T93,T94
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T44,T63
0	1	Unreachable
1	0	Covered	T17,T44,T63

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4
DetectSt	168	Covered	T4
IdleSt	163	Covered	T4
StableSt	191	Covered	T4

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4
DebounceSt->IdleSt	163	Covered	T4
DetectSt->IdleSt	186	Covered	T4
DetectSt->StableSt	191	Covered	T4
IdleSt->DebounceSt	148	Covered	T4
StableSt->IdleSt	206	Covered	T4

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T17,T18,T44
0	1	Covered	T17,T18,T44
0	0	Excluded	T40,T41,T13	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T44,T63
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T17,T18,T44
IdleSt	0	-	-	-	-	-	-	Covered	T40,T41,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T84,T85
DebounceSt	-	0	1	1	-	-	-	Covered	T17,T44,T63
DebounceSt	-	0	1	0	-	-	-	Covered	T17,T18,T72
DebounceSt	-	0	0	-	-	-	-	Covered	T17,T18,T44
DetectSt	-	-	-	-	1	-	-	Covered	T17,T93,T94
DetectSt	-	-	-	-	0	1	-	Covered	T17,T44,T63
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T17,T44,T63
StableSt	-	-	-	-	-	-	0	Covered	T17,T44,T63
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7780736	173	0	0
CntIncr_A	7780736	485132	0	0
CntNoWrap_A	7780736	7116352	0	0
DetectStDropOut_A	7780736	18	0	0
DetectedOut_A	7780736	415172	0	0
DetectedPulseOut_A	7780736	44	0	0
DisabledIdleSt_A	7780736	5578371	0	0
DisabledNoDetection_A	7780736	5580688	0	0
EnterDebounceSt_A	7780736	111	0	0
EnterDetectSt_A	7780736	62	0	0
EnterStableSt_A	7780736	44	0	0
PulseIsPulse_A	7780736	44	0	0
StayInStableSt	7780736	415128	0	0
gen_high_event_sva.HighLevelEvent_A	7780736	7118843	0	0
gen_high_level_sva.HighLevelEvent_A	7780736	7118843	0	0
gen_sticky_sva.StableStDropOut_A	7780736	572438	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	173	0	0
T17	1648	5	0	0
T18	63755	1	0	0
T19	23904	0	0	0
T20	670	0	0	0
T44	0	2	0	0
T62	33073	0	0	0
T63	0	2	0	0
T70	445	0	0	0
T71	421	0	0	0
T72	0	5	0	0
T73	0	2	0	0
T74	0	4	0	0
T75	0	2	0	0
T76	0	10	0	0
T77	0	2	0	0
T78	502	0	0	0
T79	780	0	0	0
T80	496	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	485132	0	0
T17	1648	276	0	0
T18	63755	63292	0	0
T19	23904	0	0	0
T20	670	0	0	0
T44	0	66	0	0
T62	33073	0	0	0
T63	0	29759	0	0
T70	445	0	0	0
T71	421	0	0	0
T72	0	390	0	0
T73	0	86	0	0
T74	0	116	0	0
T75	0	35	0	0
T76	0	820	0	0
T77	0	15	0	0
T78	502	0	0	0
T79	780	0	0	0
T80	496	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7116352	0	0
T13	2154	551	0	0
T14	569	168	0	0
T15	27039	26570	0	0
T26	99226	98825	0	0
T27	502	101	0	0
T28	659	258	0	0
T29	586	185	0	0
T30	548	147	0	0
T40	46119	45682	0	0
T41	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	18	0	0
T17	1648	1	0	0
T18	63755	0	0	0
T19	23904	0	0	0
T20	670	0	0	0
T62	33073	0	0	0
T70	445	0	0	0
T71	421	0	0	0
T78	502	0	0	0
T79	780	0	0	0
T80	496	0	0	0
T93	0	4	0	0
T94	0	5	0	0
T145	0	1	0	0
T161	0	1	0	0
T162	0	3	0	0
T163	0	2	0	0
T164	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	415172	0	0
T17	1648	188	0	0
T18	63755	0	0	0
T19	23904	0	0	0
T20	670	0	0	0
T44	0	321	0	0
T62	33073	0	0	0
T63	0	172920	0	0
T70	445	0	0	0
T71	421	0	0	0
T73	0	181	0	0
T74	0	467	0	0
T75	0	238	0	0
T77	0	20	0	0
T78	502	0	0	0
T79	780	0	0	0
T80	496	0	0	0
T140	0	367	0	0
T142	0	79	0	0
T143	0	236	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	44	0	0
T17	1648	1	0	0
T18	63755	0	0	0
T19	23904	0	0	0
T20	670	0	0	0
T44	0	1	0	0
T62	33073	0	0	0
T63	0	1	0	0
T70	445	0	0	0
T71	421	0	0	0
T73	0	1	0	0
T74	0	2	0	0
T75	0	1	0	0
T77	0	1	0	0
T78	502	0	0	0
T79	780	0	0	0
T80	496	0	0	0
T140	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	5578371	0	0
T13	2154	551	0	0
T14	569	168	0	0
T15	27039	26570	0	0
T26	99226	98825	0	0
T27	502	101	0	0
T28	659	258	0	0
T29	586	185	0	0
T30	548	147	0	0
T40	46119	45682	0	0
T41	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	5580688	0	0
T13	2154	554	0	0
T14	569	169	0	0
T15	27039	26581	0	0
T26	99226	98826	0	0
T27	502	102	0	0
T28	659	259	0	0
T29	586	186	0	0
T30	548	148	0	0
T40	46119	45688	0	0
T41	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	111	0	0
T17	1648	3	0	0
T18	63755	1	0	0
T19	23904	0	0	0
T20	670	0	0	0
T44	0	1	0	0
T62	33073	0	0	0
T63	0	1	0	0
T70	445	0	0	0
T71	421	0	0	0
T72	0	5	0	0
T73	0	1	0	0
T74	0	2	0	0
T75	0	1	0	0
T76	0	10	0	0
T77	0	1	0	0
T78	502	0	0	0
T79	780	0	0	0
T80	496	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	62	0	0
T17	1648	2	0	0
T18	63755	0	0	0
T19	23904	0	0	0
T20	670	0	0	0
T44	0	1	0	0
T62	33073	0	0	0
T63	0	1	0	0
T70	445	0	0	0
T71	421	0	0	0
T73	0	1	0	0
T74	0	2	0	0
T75	0	1	0	0
T77	0	1	0	0
T78	502	0	0	0
T79	780	0	0	0
T80	496	0	0	0
T140	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	44	0	0
T17	1648	1	0	0
T18	63755	0	0	0
T19	23904	0	0	0
T20	670	0	0	0
T44	0	1	0	0
T62	33073	0	0	0
T63	0	1	0	0
T70	445	0	0	0
T71	421	0	0	0
T73	0	1	0	0
T74	0	2	0	0
T75	0	1	0	0
T77	0	1	0	0
T78	502	0	0	0
T79	780	0	0	0
T80	496	0	0	0
T140	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	44	0	0
T17	1648	1	0	0
T18	63755	0	0	0
T19	23904	0	0	0
T20	670	0	0	0
T44	0	1	0	0
T62	33073	0	0	0
T63	0	1	0	0
T70	445	0	0	0
T71	421	0	0	0
T73	0	1	0	0
T74	0	2	0	0
T75	0	1	0	0
T77	0	1	0	0
T78	502	0	0	0
T79	780	0	0	0
T80	496	0	0	0
T140	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	415128	0	0
T17	1648	187	0	0
T18	63755	0	0	0
T19	23904	0	0	0
T20	670	0	0	0
T44	0	320	0	0
T62	33073	0	0	0
T63	0	172919	0	0
T70	445	0	0	0
T71	421	0	0	0
T73	0	180	0	0
T74	0	465	0	0
T75	0	237	0	0
T77	0	19	0	0
T78	502	0	0	0
T79	780	0	0	0
T80	496	0	0	0
T140	0	366	0	0
T142	0	78	0	0
T143	0	235	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7118843	0	0
T13	2154	554	0	0
T14	569	169	0	0
T15	27039	26581	0	0
T26	99226	98826	0	0
T27	502	102	0	0
T28	659	259	0	0
T29	586	186	0	0
T30	548	148	0	0
T40	46119	45688	0	0
T41	522	122	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7118843	0	0
T13	2154	554	0	0
T14	569	169	0	0
T15	27039	26581	0	0
T26	99226	98826	0	0
T27	502	102	0	0
T28	659	259	0	0
T29	586	186	0	0
T30	548	148	0	0
T40	46119	45688	0	0
T41	522	122	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	572438	0	0
T17	1648	91	0	0
T18	63755	0	0	0
T19	23904	0	0	0
T20	670	0	0	0
T44	0	316	0	0
T62	33073	0	0	0
T63	0	97	0	0
T70	445	0	0	0
T71	421	0	0	0
T73	0	258810	0	0
T74	0	802	0	0
T75	0	114	0	0
T77	0	231	0	0
T78	502	0	0	0
T79	780	0	0	0
T80	496	0	0	0
T140	0	66	0	0
T142	0	180	0	0
T143	0	122	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T40,T41,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T40,T41,T13
1	0	Covered	T40,T41,T13
1	1	Covered	T40,T41,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T22,T45,T60

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T40,T41,T13	VC_COV_UNR
1	Covered	T22,T45,T60

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T22,T45,T60

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T20
1	0	Covered	T40,T41,T13
1	1	Covered	T22,T45,T60

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T22,T45,T60
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T22,T45,T60
0	1	Covered	T165,T166,T94
1	0	Covered	T85

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T22,T45,T60
1	-	Covered	T165,T166,T94

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4
DetectSt	168	Covered	T4
IdleSt	163	Covered	T4
StableSt	191	Covered	T4

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4
DebounceSt->IdleSt	163	Covered	T4
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T4
IdleSt->DebounceSt	148	Covered	T4
StableSt->IdleSt	206	Covered	T4

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T22,T45,T60
0	1	Covered	T22,T45,T60
0	0	Excluded	T40,T41,T13	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T22,T45,T60
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T22,T45,T60
IdleSt	0	-	-	-	-	-	-	Covered	T40,T41,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T84
DebounceSt	-	0	1	1	-	-	-	Covered	T22,T45,T60
DebounceSt	-	0	1	0	-	-	-	Covered	T167,T117
DebounceSt	-	0	0	-	-	-	-	Covered	T22,T45,T60
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T22,T45,T60
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T165,T166,T94
StableSt	-	-	-	-	-	-	0	Covered	T22,T45,T60
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7780736	71	0	0
CntIncr_A	7780736	31068	0	0
CntNoWrap_A	7780736	7116454	0	0
DetectStDropOut_A	7780736	0	0	0
DetectedOut_A	7780736	52281	0	0
DetectedPulseOut_A	7780736	34	0	0
DisabledIdleSt_A	7780736	6889209	0	0
DisabledNoDetection_A	7780736	6891475	0	0
EnterDebounceSt_A	7780736	38	0	0
EnterDetectSt_A	7780736	34	0	0
EnterStableSt_A	7780736	34	0	0
PulseIsPulse_A	7780736	34	0	0
StayInStableSt	7780736	52226	0	0
gen_high_level_sva.HighLevelEvent_A	7780736	7118843	0	0
gen_not_sticky_sva.StableStDropOut_A	7780736	12	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	71	0	0
T22	481	2	0	0
T44	1139	0	0	0
T45	102206	2	0	0
T46	18603	0	0	0
T52	0	2	0	0
T60	0	2	0	0
T84	0	1	0	0
T101	718	0	0	0
T132	0	2	0	0
T165	0	2	0	0
T168	0	2	0	0
T169	0	2	0	0
T170	0	2	0	0
T171	424	0	0	0
T172	439	0	0	0
T173	420	0	0	0
T174	411	0	0	0
T175	424	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	31068	0	0
T22	481	17	0	0
T44	1139	0	0	0
T45	102206	43	0	0
T46	18603	0	0	0
T52	0	78	0	0
T60	0	22	0	0
T84	0	15	0	0
T101	718	0	0	0
T132	0	39	0	0
T165	0	19	0	0
T168	0	15	0	0
T169	0	63	0	0
T170	0	53	0	0
T171	424	0	0	0
T172	439	0	0	0
T173	420	0	0	0
T174	411	0	0	0
T175	424	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7116454	0	0
T13	2154	551	0	0
T14	569	168	0	0
T15	27039	26570	0	0
T26	99226	98825	0	0
T27	502	101	0	0
T28	659	258	0	0
T29	586	185	0	0
T30	548	147	0	0
T40	46119	45682	0	0
T41	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	52281	0	0
T22	481	42	0	0
T44	1139	0	0	0
T45	102206	51	0	0
T46	18603	0	0	0
T52	0	42	0	0
T60	0	69	0	0
T101	718	0	0	0
T132	0	66	0	0
T165	0	3	0	0
T168	0	59	0	0
T169	0	38	0	0
T170	0	41	0	0
T171	424	0	0	0
T172	439	0	0	0
T173	420	0	0	0
T174	411	0	0	0
T175	424	0	0	0
T176	0	40	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	34	0	0
T22	481	1	0	0
T44	1139	0	0	0
T45	102206	1	0	0
T46	18603	0	0	0
T52	0	1	0	0
T60	0	1	0	0
T101	718	0	0	0
T132	0	1	0	0
T165	0	1	0	0
T168	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	424	0	0	0
T172	439	0	0	0
T173	420	0	0	0
T174	411	0	0	0
T175	424	0	0	0
T176	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	6889209	0	0
T13	2154	460	0	0
T14	569	4	0	0
T15	27039	26570	0	0
T26	99226	98825	0	0
T27	502	101	0	0
T28	659	258	0	0
T29	586	185	0	0
T30	548	147	0	0
T40	46119	45682	0	0
T41	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	6891475	0	0
T13	2154	462	0	0
T14	569	4	0	0
T15	27039	26581	0	0
T26	99226	98826	0	0
T27	502	102	0	0
T28	659	259	0	0
T29	586	186	0	0
T30	548	148	0	0
T40	46119	45688	0	0
T41	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	38	0	0
T22	481	1	0	0
T44	1139	0	0	0
T45	102206	1	0	0
T46	18603	0	0	0
T52	0	1	0	0
T60	0	1	0	0
T84	0	1	0	0
T101	718	0	0	0
T132	0	1	0	0
T165	0	1	0	0
T168	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	424	0	0	0
T172	439	0	0	0
T173	420	0	0	0
T174	411	0	0	0
T175	424	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	34	0	0
T22	481	1	0	0
T44	1139	0	0	0
T45	102206	1	0	0
T46	18603	0	0	0
T52	0	1	0	0
T60	0	1	0	0
T101	718	0	0	0
T132	0	1	0	0
T165	0	1	0	0
T168	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	424	0	0	0
T172	439	0	0	0
T173	420	0	0	0
T174	411	0	0	0
T175	424	0	0	0
T176	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	34	0	0
T22	481	1	0	0
T44	1139	0	0	0
T45	102206	1	0	0
T46	18603	0	0	0
T52	0	1	0	0
T60	0	1	0	0
T101	718	0	0	0
T132	0	1	0	0
T165	0	1	0	0
T168	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	424	0	0	0
T172	439	0	0	0
T173	420	0	0	0
T174	411	0	0	0
T175	424	0	0	0
T176	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	34	0	0
T22	481	1	0	0
T44	1139	0	0	0
T45	102206	1	0	0
T46	18603	0	0	0
T52	0	1	0	0
T60	0	1	0	0
T101	718	0	0	0
T132	0	1	0	0
T165	0	1	0	0
T168	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	424	0	0	0
T172	439	0	0	0
T173	420	0	0	0
T174	411	0	0	0
T175	424	0	0	0
T176	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	52226	0	0
T22	481	40	0	0
T44	1139	0	0	0
T45	102206	49	0	0
T46	18603	0	0	0
T52	0	40	0	0
T60	0	67	0	0
T101	718	0	0	0
T132	0	64	0	0
T165	0	2	0	0
T168	0	57	0	0
T169	0	36	0	0
T170	0	39	0	0
T171	424	0	0	0
T172	439	0	0	0
T173	420	0	0	0
T174	411	0	0	0
T175	424	0	0	0
T176	0	38	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7118843	0	0
T13	2154	554	0	0
T14	569	169	0	0
T15	27039	26581	0	0
T26	99226	98826	0	0
T27	502	102	0	0
T28	659	259	0	0
T29	586	186	0	0
T30	548	148	0	0
T40	46119	45688	0	0
T41	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	12	0	0
T87	745	0	0	0
T94	0	1	0	0
T117	0	1	0	0
T127	5917	0	0	0
T128	423	0	0	0
T129	404	0	0	0
T130	422	0	0	0
T131	431	0	0	0
T132	6581	0	0	0
T165	617	1	0	0
T166	0	2	0	0
T177	0	1	0	0
T178	0	1	0	0
T179	0	1	0	0
T180	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0
T183	495	0	0	0
T184	713	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T40,T41,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T40,T41,T13
1	0	Covered	T40,T41,T13
1	1	Covered	T40,T41,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T20,T21,T54

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T40,T41,T13	VC_COV_UNR
1	Covered	T20,T21,T54

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T20,T21,T54

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T54
1	0	Covered	T40,T41,T13
1	1	Covered	T20,T21,T54

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T20,T21,T54
0	1	Covered	T88,T89,T185
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T20,T21,T54
0	1	Covered	T21,T45,T186
1	0	Covered	T85

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T20,T21,T54
1	-	Covered	T21,T45,T186

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4
DetectSt	168	Covered	T4
IdleSt	163	Covered	T4
StableSt	191	Covered	T4

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4
DebounceSt->IdleSt	163	Covered	T4
DetectSt->IdleSt	186	Covered	T4
DetectSt->StableSt	191	Covered	T4
IdleSt->DebounceSt	148	Covered	T4
StableSt->IdleSt	206	Covered	T4

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T20,T21,T54
0	1	Covered	T20,T21,T54
0	0	Excluded	T40,T41,T13	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T54
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T20,T21,T54
IdleSt	0	-	-	-	-	-	-	Covered	T40,T41,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T84
DebounceSt	-	0	1	1	-	-	-	Covered	T20,T21,T54
DebounceSt	-	0	1	0	-	-	-	Covered	T187,T176,T177
DebounceSt	-	0	0	-	-	-	-	Covered	T20,T21,T54
DetectSt	-	-	-	-	1	-	-	Covered	T88,T89,T185
DetectSt	-	-	-	-	0	1	-	Covered	T20,T21,T54
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T21,T45,T186
StableSt	-	-	-	-	-	-	0	Covered	T20,T21,T54
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7780736	136	0	0
CntIncr_A	7780736	33193	0	0
CntNoWrap_A	7780736	7116389	0	0
DetectStDropOut_A	7780736	4	0	0
DetectedOut_A	7780736	5122	0	0
DetectedPulseOut_A	7780736	60	0	0
DisabledIdleSt_A	7780736	6986293	0	0
DisabledNoDetection_A	7780736	6988546	0	0
EnterDebounceSt_A	7780736	72	0	0
EnterDetectSt_A	7780736	64	0	0
EnterStableSt_A	7780736	60	0	0
PulseIsPulse_A	7780736	60	0	0
StayInStableSt	7780736	5036	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7780736	2720	0	0
gen_low_level_sva.LowLevelEvent_A	7780736	7118843	0	0
gen_not_sticky_sva.StableStDropOut_A	7780736	33	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	136	0	0
T20	670	2	0	0
T21	33629	4	0	0
T45	0	2	0	0
T51	0	2	0	0
T54	0	2	0	0
T56	0	2	0	0
T59	0	2	0	0
T79	780	0	0	0
T80	496	0	0	0
T144	491	0	0	0
T169	0	2	0	0
T186	0	2	0	0
T188	0	6	0	0
T189	491	0	0	0
T190	506	0	0	0
T191	448	0	0	0
T192	492	0	0	0
T193	2538	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	33193	0	0
T20	670	81	0	0
T21	33629	162	0	0
T45	0	43	0	0
T51	0	71	0	0
T54	0	37	0	0
T56	0	58	0	0
T59	0	47	0	0
T79	780	0	0	0
T80	496	0	0	0
T144	491	0	0	0
T169	0	63	0	0
T186	0	94	0	0
T188	0	174	0	0
T189	491	0	0	0
T190	506	0	0	0
T191	448	0	0	0
T192	492	0	0	0
T193	2538	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7116389	0	0
T13	2154	551	0	0
T14	569	168	0	0
T15	27039	26570	0	0
T26	99226	98825	0	0
T27	502	101	0	0
T28	659	258	0	0
T29	586	185	0	0
T30	548	147	0	0
T40	46119	45682	0	0
T41	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	4	0	0
T88	516	1	0	0
T89	0	1	0	0
T114	8847	0	0	0
T185	0	1	0	0
T194	0	1	0	0
T195	747	0	0	0
T196	5415	0	0	0
T197	502	0	0	0
T198	509	0	0	0
T199	17376	0	0	0
T200	846	0	0	0
T201	403	0	0	0
T202	29707	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	5122	0	0
T20	670	38	0	0
T21	33629	106	0	0
T45	0	139	0	0
T51	0	256	0	0
T54	0	97	0	0
T56	0	45	0	0
T59	0	241	0	0
T79	780	0	0	0
T80	496	0	0	0
T144	491	0	0	0
T169	0	17	0	0
T186	0	24	0	0
T188	0	188	0	0
T189	491	0	0	0
T190	506	0	0	0
T191	448	0	0	0
T192	492	0	0	0
T193	2538	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	60	0	0
T20	670	1	0	0
T21	33629	2	0	0
T45	0	1	0	0
T51	0	1	0	0
T54	0	1	0	0
T56	0	1	0	0
T59	0	1	0	0
T79	780	0	0	0
T80	496	0	0	0
T144	491	0	0	0
T169	0	1	0	0
T186	0	1	0	0
T188	0	3	0	0
T189	491	0	0	0
T190	506	0	0	0
T191	448	0	0	0
T192	492	0	0	0
T193	2538	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	6986293	0	0
T13	2154	551	0	0
T14	569	168	0	0
T15	27039	26570	0	0
T26	99226	98825	0	0
T27	502	101	0	0
T28	659	258	0	0
T29	586	185	0	0
T30	548	147	0	0
T40	46119	45682	0	0
T41	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	6988546	0	0
T13	2154	554	0	0
T14	569	169	0	0
T15	27039	26581	0	0
T26	99226	98826	0	0
T27	502	102	0	0
T28	659	259	0	0
T29	586	186	0	0
T30	548	148	0	0
T40	46119	45688	0	0
T41	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	72	0	0
T20	670	1	0	0
T21	33629	2	0	0
T45	0	1	0	0
T51	0	1	0	0
T54	0	1	0	0
T56	0	1	0	0
T59	0	1	0	0
T79	780	0	0	0
T80	496	0	0	0
T144	491	0	0	0
T169	0	1	0	0
T186	0	1	0	0
T188	0	3	0	0
T189	491	0	0	0
T190	506	0	0	0
T191	448	0	0	0
T192	492	0	0	0
T193	2538	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	64	0	0
T20	670	1	0	0
T21	33629	2	0	0
T45	0	1	0	0
T51	0	1	0	0
T54	0	1	0	0
T56	0	1	0	0
T59	0	1	0	0
T79	780	0	0	0
T80	496	0	0	0
T144	491	0	0	0
T169	0	1	0	0
T186	0	1	0	0
T188	0	3	0	0
T189	491	0	0	0
T190	506	0	0	0
T191	448	0	0	0
T192	492	0	0	0
T193	2538	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	60	0	0
T20	670	1	0	0
T21	33629	2	0	0
T45	0	1	0	0
T51	0	1	0	0
T54	0	1	0	0
T56	0	1	0	0
T59	0	1	0	0
T79	780	0	0	0
T80	496	0	0	0
T144	491	0	0	0
T169	0	1	0	0
T186	0	1	0	0
T188	0	3	0	0
T189	491	0	0	0
T190	506	0	0	0
T191	448	0	0	0
T192	492	0	0	0
T193	2538	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	60	0	0
T20	670	1	0	0
T21	33629	2	0	0
T45	0	1	0	0
T51	0	1	0	0
T54	0	1	0	0
T56	0	1	0	0
T59	0	1	0	0
T79	780	0	0	0
T80	496	0	0	0
T144	491	0	0	0
T169	0	1	0	0
T186	0	1	0	0
T188	0	3	0	0
T189	491	0	0	0
T190	506	0	0	0
T191	448	0	0	0
T192	492	0	0	0
T193	2538	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	5036	0	0
T20	670	36	0	0
T21	33629	103	0	0
T45	0	138	0	0
T51	0	255	0	0
T54	0	95	0	0
T56	0	43	0	0
T59	0	239	0	0
T79	780	0	0	0
T80	496	0	0	0
T144	491	0	0	0
T169	0	16	0	0
T186	0	23	0	0
T188	0	184	0	0
T189	491	0	0	0
T190	506	0	0	0
T191	448	0	0	0
T192	492	0	0	0
T193	2538	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	2720	0	0
T13	2154	5	0	0
T14	569	0	0	0
T15	27039	0	0	0
T26	99226	0	0	0
T27	502	4	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	6	0	0
T41	522	5	0	0
T66	0	4	0	0
T67	0	2	0	0
T69	0	5	0	0
T70	0	5	0	0
T90	0	23	0	0
T104	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7118843	0	0
T13	2154	554	0	0
T14	569	169	0	0
T15	27039	26581	0	0
T26	99226	98826	0	0
T27	502	102	0	0
T28	659	259	0	0
T29	586	186	0	0
T30	548	148	0	0
T40	46119	45688	0	0
T41	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	33	0	0
T21	33629	1	0	0
T22	481	0	0	0
T45	0	1	0	0
T51	0	1	0	0
T61	18429	0	0	0
T132	0	2	0	0
T144	491	0	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	424	0	0	0
T186	0	1	0	0
T188	0	2	0	0
T189	491	0	0	0
T190	506	0	0	0
T191	448	0	0	0
T192	492	0	0	0
T193	2538	0	0	0
T203	0	1	0	0
T204	0	1	0	0