Unified Coverage Report :: Module :: sysrst_ctrl_detect

Module : sysrst_ctrl_detect

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.35	100.00	96.30		100.00	95.45	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l	90.21	93.48	90.48		83.33	90.00	93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h	91.56	95.65	90.48		83.33	95.00	93.33
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h	91.56	95.65	90.48		83.33	95.00	93.33
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l	91.64	95.65	90.48		83.33	95.00	93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l	91.64	95.65	90.48		83.33	95.00	93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l	91.64	95.65	90.48		83.33	95.00	93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l	91.64	95.65	90.48		83.33	95.00	93.75
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre	97.99	100.00	94.74		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb	98.89	100.00	94.44		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open	98.89	100.00	94.44		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	LINE
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	LINE
91.64	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	LINE
91.64	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	LINE
90.21	93.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	LINE
91.64	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	LINE
91.64	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

SCORE	LINE
91.56	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	LINE
91.56	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.67	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	LINE
97.99	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T40,T15,T31
1	Covered	T40,T41,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T40,T15,T31
1	0	Covered	T40,T41,T13
1	1	Covered	T40,T41,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T40,T15,T31

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T40,T15,T31

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T40,T15,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T40,T15,T31
1	0	Covered	T40,T13,T15
1	1	Covered	T40,T15,T31

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T40,T15,T32
0	1	Covered	T15,T48,T83
1	0	Covered	T84,T85

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T40,T15,T32
0	1	Covered	T15,T32,T16
1	0	Covered	T46,T86

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T40,T15,T32
1	-	Covered	T15,T32,T16

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	COND
91.64	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	COND
91.64	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	COND
90.21	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	COND
91.64	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	COND
91.64	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T40,T41,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T40,T41,T13
1	0	Covered	T40,T41,T13
1	1	Covered	T40,T41,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T13,T14,T29

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T13,T14,T29

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T13,T14,T29

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T29
1	0	Covered	T40,T41,T13
1	1	Covered	T13,T14,T29

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T29
0	1	Covered	T87,T88,T89
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T29
0	1	Covered	T29,T90,T79
1	0	Covered	T85

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T14,T29
1	-	Covered	T29,T90,T79

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	COND
97.99	94.74

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T40,T32,T16
1	Covered	T40,T41,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T40,T32,T16

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T40,T32,T16

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T40,T32,T16

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T40,T32,T16
1	0	Covered	T40,T32,T16
1	1	Covered	T40,T32,T16

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T40,T32,T16
0	1	Covered	T32,T16,T91
1	0	Covered	T32,T16,T19

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T40,T32,T16
0	1	Covered	T40,T32,T16
1	0	Covered	T64,T92,T85

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T40,T32,T16
1	-	Covered	T40,T32,T16

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.67	93.33

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	16	15	93.75
Logical	16	15	93.75
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T40,T41,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T17,T18,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T17,T18,T44

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T17,T44,T63

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T44
1	0	Covered	T40,T41,T13
1	1	Covered	T17,T18,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T17,T44,T63
0	1	Covered	T17,T93,T94
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T44,T63
0	1	Unreachable
1	0	Covered	T17,T44,T63

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
91.56	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	COND
91.56	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T40,T41,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T40,T41,T13
1	0	Covered	T40,T41,T13
1	1	Covered	T40,T41,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T13,T22,T57

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T13,T22,T57

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T13,T22,T57

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T20
1	0	Covered	T40,T41,T13
1	1	Covered	T13,T22,T57

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T22,T57
0	1	Covered	T60,T52,T95
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T22,T57
0	1	Covered	T58,T55,T59
1	0	Covered	T85

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T22,T57
1	-	Covered	T58,T55,T59

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.89	94.44

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T41,T13,T27

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T40,T41,T13
1	0	Covered	T41,T13,T27
1	1	Covered	T41,T13,T27

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T17,T18,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T17,T18,T44

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T17,T18,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T44
1	0	Covered	T41,T13,T27
1	1	Covered	T17,T18,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T18,T44,T72
0	1	Covered	T17,T75,T96
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T18,T44,T72
0	1	Unreachable
1	0	Covered	T18,T44,T72

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.89	94.44

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T40,T41,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T40,T41,T13
1	0	Covered	T40,T41,T13
1	1	Covered	T40,T41,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T17,T18,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T17,T18,T44

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T17,T18,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T44
1	0	Covered	T40,T41,T13
1	1	Covered	T17,T18,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T17,T18,T44
0	1	Covered	T75,T97,T98
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T18,T44
0	1	Unreachable
1	0	Covered	T17,T18,T44

---

FSM Coverage for Module : sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4
DetectSt	168	Covered	T4
IdleSt	163	Covered	T4
StableSt	191	Covered	T4

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4
DebounceSt->IdleSt	163	Covered	T4
DetectSt->IdleSt	186	Covered	T4
DetectSt->StableSt	191	Covered	T4
IdleSt->DebounceSt	148	Covered	T4
StableSt->IdleSt	206	Covered	T4

---

Branch Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
91.64	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
91.64	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
90.21	90.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
91.64	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
91.64	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCORE	BRANCH
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

SCORE	BRANCH
91.56	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
91.56	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		23	22	95.65
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T13,T14,T29
0	1	Covered	T13,T14,T29
0	0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T29
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T13,T14,T29
IdleSt	0	-	-	-	-	-	-	Covered	T40,T41,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T84,T85
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T14,T29
DebounceSt	-	0	1	0	-	-	-	Covered	T45,T99,T100
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T14,T29
DetectSt	-	-	-	-	1	-	-	Covered	T17,T75,T87
DetectSt	-	-	-	-	0	1	-	Covered	T13,T14,T29
DetectSt	-	-	-	-	0	0	-	Covered	T40,T15,T32
StableSt	-	-	-	-	-	-	1	Covered	T29,T90,T79
StableSt	-	-	-	-	-	-	0	Covered	T13,T14,T29
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

---

Branch Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
98.67	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
97.99	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T40,T32,T16
0	1	Covered	T40,T32,T16
0	0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T40,T32,T16
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T40,T32,T16
IdleSt	0	-	-	-	-	-	-	Covered	T40,T41,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T84,T85
DebounceSt	-	0	1	1	-	-	-	Covered	T40,T32,T16
DebounceSt	-	0	1	0	-	-	-	Covered	T17,T18,T72
DebounceSt	-	0	0	-	-	-	-	Covered	T40,T32,T16
DetectSt	-	-	-	-	1	-	-	Covered	T32,T16,T91
DetectSt	-	-	-	-	0	1	-	Covered	T40,T32,T16
DetectSt	-	-	-	-	0	0	-	Covered	T40,T32,T16
StableSt	-	-	-	-	-	-	1	Covered	T40,T32,T16
StableSt	-	-	-	-	-	-	0	Covered	T40,T32,T16
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

---

Assert Coverage for Module : sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	202299136	17604	0	0
CntIncr_A	202299136	2661970	0	0
CntNoWrap_A	202299136	185012046	0	0
DetectStDropOut_A	202299136	2218	0	0
DetectedOut_A	202299136	1628080	0	0
DetectedPulseOut_A	202299136	5622	0	0
DisabledIdleSt_A	202299136	173121208	0	0
DisabledNoDetection_A	202299136	173177305	0	0
EnterDebounceSt_A	202299136	9064	0	0
EnterDetectSt_A	202299136	8566	0	0
EnterStableSt_A	202299136	5622	0	0
PulseIsPulse_A	202299136	5622	0	0
StayInStableSt	202299136	1621547	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	70026624	52077	0	0
gen_high_event_sva.HighLevelEvent_A	38903680	35594215	0	0
gen_high_level_sva.HighLevelEvent_A	132272512	121020331	0	0
gen_low_level_sva.LowLevelEvent_A	70026624	64069587	0	0
gen_not_sticky_sva.StableStDropOut_A	178956928	4534	0	0
gen_sticky_sva.StableStDropOut_A	23342208	2538895	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	202299136	17604	0	0
T13	10770	0	0	0
T14	2845	0	0	0
T15	216312	10	0	0
T16	93700	44	0	0
T19	0	63	0	0
T20	670	0	0	0
T21	0	2	0	0
T26	496130	0	0	0
T27	2510	0	0	0
T28	3295	0	0	0
T29	5274	2	0	0
T30	4932	0	0	0
T31	5352	1	0	0
T32	31956	36	0	0
T40	230595	58	0	0
T41	2610	0	0	0
T45	0	22	0	0
T46	0	35	0	0
T48	0	30	0	0
T61	0	34	0	0
T63	0	7	0	0
T66	1976	0	0	0
T67	1688	0	0	0
T68	2524	0	0	0
T69	2040	0	0	0
T79	780	2	0	0
T80	496	0	0	0
T90	0	2	0	0
T91	0	14	0	0
T99	0	1	0	0
T100	0	1	0	0
T101	0	4	0	0
T102	0	66	0	0
T103	0	4	0	0
T104	502	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	202299136	2661970	0	0
T13	10770	0	0	0
T14	2845	0	0	0
T15	216312	600	0	0
T16	93700	1263	0	0
T19	0	4395	0	0
T20	670	0	0	0
T21	0	25566	0	0
T26	496130	0	0	0
T27	2510	0	0	0
T28	3295	0	0	0
T29	5274	17	0	0
T30	4932	0	0	0
T31	5352	20	0	0
T32	31956	1416	0	0
T40	230595	8694	0	0
T41	2610	0	0	0
T45	0	39116	0	0
T46	0	1048	0	0
T48	0	2230	0	0
T61	0	811	0	0
T63	0	249	0	0
T66	1976	0	0	0
T67	1688	0	0	0
T68	2524	0	0	0
T69	2040	0	0	0
T79	780	53	0	0
T80	496	0	0	0
T90	0	90	0	0
T91	0	415	0	0
T99	0	25900	0	0
T100	0	21	0	0
T101	0	93	0	0
T102	0	2414	0	0
T103	0	144	0	0
T104	502	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	202299136	185012046	0	0
T13	56004	14318	0	0
T14	14794	4364	0	0
T15	703014	690767	0	0
T26	2579876	2569450	0	0
T27	13052	2626	0	0
T28	17134	6708	0	0
T29	15236	4808	0	0
T30	14248	3822	0	0
T40	1199094	1187600	0	0
T41	13572	3146	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	202299136	2218	0	0
T16	23425	11	0	0
T49	0	7	0	0
T60	603	0	0	0
T61	0	4	0	0
T85	0	1	0	0
T87	745	1	0	0
T89	0	2	0	0
T91	0	7	0	0
T105	0	22	0	0
T106	0	12	0	0
T107	0	6	0	0
T108	0	12	0	0
T109	0	5	0	0
T110	0	13	0	0
T111	24266	3	0	0
T112	0	10	0	0
T113	8000	1	0	0
T114	0	3	0	0
T115	0	1	0	0
T116	0	1	0	0
T117	0	6	0	0
T118	0	2	0	0
T119	18790	0	0	0
T120	5119	0	0	0
T121	497	0	0	0
T122	422	0	0	0
T123	3117	0	0	0
T124	493	0	0	0
T125	15469	0	0	0
T126	988	0	0	0
T127	5917	0	0	0
T128	423	0	0	0
T129	404	0	0	0
T130	422	0	0	0
T131	431	0	0	0
T132	6581	0	0	0
T133	502	0	0	0
T134	534	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	202299136	1628080	0	0
T13	4308	0	0	0
T14	1138	0	0	0
T15	54078	210	0	0
T16	46850	0	0	0
T19	0	5615	0	0
T21	0	6	0	0
T26	198452	0	0	0
T27	1004	0	0	0
T28	1318	0	0	0
T29	1758	9	0	0
T30	1644	0	0	0
T31	1338	0	0	0
T32	7989	1831	0	0
T40	92238	11384	0	0
T41	1044	0	0	0
T45	0	289	0	0
T46	0	944	0	0
T48	0	530	0	0
T62	33073	0	0	0
T63	0	25	0	0
T64	0	137	0	0
T65	0	119	0	0
T66	494	0	0	0
T67	844	0	0	0
T68	1262	0	0	0
T69	1020	0	0	0
T79	0	9	0	0
T90	4870	10	0	0
T91	5616	0	0	0
T101	0	19	0	0
T102	0	2114	0	0
T103	0	8	0	0
T104	1004	0	0	0
T135	0	1682	0	0
T136	0	476	0	0
T137	0	11	0	0
T138	0	12	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	202299136	5622	0	0
T13	4308	0	0	0
T14	1138	0	0	0
T15	54078	4	0	0
T16	46850	0	0	0
T19	0	31	0	0
T21	0	1	0	0
T26	198452	0	0	0
T27	1004	0	0	0
T28	1318	0	0	0
T29	1758	1	0	0
T30	1644	0	0	0
T31	1338	0	0	0
T32	7989	18	0	0
T40	92238	29	0	0
T41	1044	0	0	0
T45	0	10	0	0
T46	0	17	0	0
T48	0	15	0	0
T62	33073	0	0	0
T63	0	3	0	0
T64	0	13	0	0
T65	0	4	0	0
T66	494	0	0	0
T67	844	0	0	0
T68	1262	0	0	0
T69	1020	0	0	0
T79	0	1	0	0
T90	4870	1	0	0
T91	5616	0	0	0
T101	0	2	0	0
T102	0	33	0	0
T103	0	2	0	0
T104	1004	0	0	0
T135	0	28	0	0
T136	0	7	0	0
T137	0	1	0	0
T138	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	202299136	173121208	0	0
T13	56004	13780	0	0
T14	14794	3384	0	0
T15	703014	673176	0	0
T26	2579876	2569450	0	0
T27	13052	2626	0	0
T28	17134	6708	0	0
T29	15236	4753	0	0
T30	14248	3822	0	0
T40	1199094	1051038	0	0
T41	13572	3146	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	202299136	173177305	0	0
T13	56004	13852	0	0
T14	14794	3404	0	0
T15	703014	673418	0	0
T26	2579876	2569476	0	0
T27	13052	2652	0	0
T28	17134	6734	0	0
T29	15236	4779	0	0
T30	14248	3848	0	0
T40	1199094	1051180	0	0
T41	13572	3172	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	202299136	9064	0	0
T13	10770	0	0	0
T14	2845	0	0	0
T15	216312	6	0	0
T16	93700	22	0	0
T19	0	32	0	0
T20	670	0	0	0
T21	0	2	0	0
T26	496130	0	0	0
T27	2510	0	0	0
T28	3295	0	0	0
T29	5274	1	0	0
T30	4932	0	0	0
T31	5352	1	0	0
T32	31956	18	0	0
T40	230595	29	0	0
T41	2610	0	0	0
T45	0	13	0	0
T46	0	18	0	0
T48	0	15	0	0
T61	0	17	0	0
T63	0	5	0	0
T66	1976	0	0	0
T67	1688	0	0	0
T68	2524	0	0	0
T69	2040	0	0	0
T79	780	1	0	0
T80	496	0	0	0
T90	0	2	0	0
T91	0	7	0	0
T99	0	1	0	0
T100	0	1	0	0
T101	0	2	0	0
T102	0	33	0	0
T103	0	2	0	0
T104	502	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	202299136	8566	0	0
T13	10770	0	0	0
T14	2845	0	0	0
T15	216312	4	0	0
T16	93700	22	0	0
T19	0	31	0	0
T20	670	0	0	0
T21	0	1	0	0
T26	496130	0	0	0
T27	2510	0	0	0
T28	3295	0	0	0
T29	5274	1	0	0
T30	4932	0	0	0
T31	5352	0	0	0
T32	31956	18	0	0
T40	230595	29	0	0
T41	2610	0	0	0
T45	0	10	0	0
T46	0	17	0	0
T48	0	15	0	0
T61	0	17	0	0
T63	0	3	0	0
T65	0	4	0	0
T66	1976	0	0	0
T67	1688	0	0	0
T68	2524	0	0	0
T69	2040	0	0	0
T79	780	1	0	0
T80	496	0	0	0
T90	0	1	0	0
T91	0	7	0	0
T101	0	2	0	0
T102	0	33	0	0
T103	0	2	0	0
T104	502	0	0	0
T137	0	1	0	0
T138	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	202299136	5622	0	0
T13	4308	0	0	0
T14	1138	0	0	0
T15	54078	4	0	0
T16	46850	0	0	0
T19	0	31	0	0
T21	0	1	0	0
T26	198452	0	0	0
T27	1004	0	0	0
T28	1318	0	0	0
T29	1758	1	0	0
T30	1644	0	0	0
T31	1338	0	0	0
T32	7989	18	0	0
T40	92238	29	0	0
T41	1044	0	0	0
T45	0	10	0	0
T46	0	17	0	0
T48	0	15	0	0
T62	33073	0	0	0
T63	0	3	0	0
T64	0	13	0	0
T65	0	4	0	0
T66	494	0	0	0
T67	844	0	0	0
T68	1262	0	0	0
T69	1020	0	0	0
T79	0	1	0	0
T90	4870	1	0	0
T91	5616	0	0	0
T101	0	2	0	0
T102	0	33	0	0
T103	0	2	0	0
T104	1004	0	0	0
T135	0	28	0	0
T136	0	7	0	0
T137	0	1	0	0
T138	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	202299136	5622	0	0
T13	4308	0	0	0
T14	1138	0	0	0
T15	54078	4	0	0
T16	46850	0	0	0
T19	0	31	0	0
T21	0	1	0	0
T26	198452	0	0	0
T27	1004	0	0	0
T28	1318	0	0	0
T29	1758	1	0	0
T30	1644	0	0	0
T31	1338	0	0	0
T32	7989	18	0	0
T40	92238	29	0	0
T41	1044	0	0	0
T45	0	10	0	0
T46	0	17	0	0
T48	0	15	0	0
T62	33073	0	0	0
T63	0	3	0	0
T64	0	13	0	0
T65	0	4	0	0
T66	494	0	0	0
T67	844	0	0	0
T68	1262	0	0	0
T69	1020	0	0	0
T79	0	1	0	0
T90	4870	1	0	0
T91	5616	0	0	0
T101	0	2	0	0
T102	0	33	0	0
T103	0	2	0	0
T104	1004	0	0	0
T135	0	28	0	0
T136	0	7	0	0
T137	0	1	0	0
T138	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	202299136	1621547	0	0
T13	4308	0	0	0
T14	1138	0	0	0
T15	54078	206	0	0
T16	46850	0	0	0
T19	0	5580	0	0
T21	0	5	0	0
T26	198452	0	0	0
T27	1004	0	0	0
T28	1318	0	0	0
T29	1758	8	0	0
T30	1644	0	0	0
T31	1338	0	0	0
T32	7989	1813	0	0
T40	92238	11345	0	0
T41	1044	0	0	0
T45	0	279	0	0
T46	0	924	0	0
T48	0	515	0	0
T62	33073	0	0	0
T63	0	22	0	0
T64	0	124	0	0
T65	0	115	0	0
T66	494	0	0	0
T67	844	0	0	0
T68	1262	0	0	0
T69	1020	0	0	0
T79	0	8	0	0
T90	4870	9	0	0
T91	5616	0	0	0
T101	0	17	0	0
T102	0	2071	0	0
T103	0	6	0	0
T104	1004	0	0	0
T135	0	1653	0	0
T136	0	469	0	0
T137	0	10	0	0
T138	0	11	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70026624	52077	0	0
T13	19386	49	0	0
T14	5121	2	0	0
T15	243351	81	0	0
T16	0	209	0	0
T26	893034	5	0	0
T27	4518	42	0	0
T28	5931	4	0	0
T29	5274	9	0	0
T30	4932	3	0	0
T31	2676	56	0	0
T32	0	194	0	0
T40	322833	194	0	0
T41	4698	39	0	0
T66	0	62	0	0
T67	0	14	0	0
T69	0	5	0	0
T70	0	5	0	0
T90	0	23	0	0
T104	0	6	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38903680	35594215	0	0
T13	10770	2770	0	0
T14	2845	845	0	0
T15	135195	132905	0	0
T26	496130	494130	0	0
T27	2510	510	0	0
T28	3295	1295	0	0
T29	2930	930	0	0
T30	2740	740	0	0
T40	230595	228440	0	0
T41	2610	610	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132272512	121020331	0	0
T13	36618	9418	0	0
T14	9673	2873	0	0
T15	459663	451877	0	0
T26	1686842	1680042	0	0
T27	8534	1734	0	0
T28	11203	4403	0	0
T29	9962	3162	0	0
T30	9316	2516	0	0
T40	784023	776696	0	0
T41	8874	2074	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70026624	64069587	0	0
T13	19386	4986	0	0
T14	5121	1521	0	0
T15	243351	239229	0	0
T26	893034	889434	0	0
T27	4518	918	0	0
T28	5931	2331	0	0
T29	5274	1674	0	0
T30	4932	1332	0	0
T40	415071	411192	0	0
T41	4698	1098	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178956928	4534	0	0
T13	2154	0	0	0
T14	569	0	0	0
T15	54078	4	0	0
T16	70275	0	0	0
T19	0	27	0	0
T21	0	1	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	1758	1	0	0
T30	1644	0	0	0
T31	2676	0	0	0
T32	15978	18	0	0
T40	46119	19	0	0
T41	522	0	0	0
T45	0	10	0	0
T46	0	14	0	0
T48	0	15	0	0
T62	33073	0	0	0
T63	0	3	0	0
T64	0	12	0	0
T65	0	4	0	0
T66	988	0	0	0
T67	1266	0	0	0
T68	1893	0	0	0
T69	1530	0	0	0
T79	0	1	0	0
T83	0	4	0	0
T90	4870	1	0	0
T91	5616	0	0	0
T101	0	2	0	0
T102	0	23	0	0
T103	0	2	0	0
T104	1004	0	0	0
T137	0	1	0	0
T138	0	1	0	0
T139	0	5	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23342208	2538895	0	0
T17	3296	517	0	0
T18	191265	126576	0	0
T19	71712	0	0	0
T20	2010	0	0	0
T21	33629	0	0	0
T44	0	638	0	0
T62	99219	0	0	0
T63	0	202360	0	0
T70	890	0	0	0
T71	1263	0	0	0
T72	0	619	0	0
T73	0	517672	0	0
T74	0	2087	0	0
T75	0	137	0	0
T76	0	919	0	0
T77	0	363	0	0
T78	1506	0	0	0
T79	2340	0	0	0
T80	1488	0	0	0
T140	0	221	0	0
T141	0	78	0	0
T142	0	248	0	0
T143	0	208	0	0
T144	491	0	0	0