Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T40,T41,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T40,T41,T13
1	0	Covered	T40,T41,T13
1	1	Covered	T40,T41,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T57,T55,T59

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T40,T41,T13	VC_COV_UNR
1	Covered	T57,T55,T59

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T57,T55,T59

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T20,T22,T54
1	0	Covered	T40,T41,T13
1	1	Covered	T57,T55,T59

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T57,T55,T59
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T57,T55,T59
0	1	Covered	T55,T188,T203
1	0	Covered	T85

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T57,T55,T59
1	-	Covered	T55,T188,T203

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4
DetectSt	168	Covered	T4
IdleSt	163	Covered	T4
StableSt	191	Covered	T4

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4
DebounceSt->IdleSt	163	Covered	T4
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T4
IdleSt->DebounceSt	148	Covered	T4
StableSt->IdleSt	206	Covered	T4

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T57,T55,T59
0	1	Covered	T57,T55,T59
0	0	Excluded	T40,T41,T13	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T57,T55,T59
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T57,T55,T59
IdleSt	0	-	-	-	-	-	-	Covered	T40,T41,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T84
DebounceSt	-	0	1	1	-	-	-	Covered	T57,T55,T59
DebounceSt	-	0	1	0	-	-	-	Covered	T166,T97
DebounceSt	-	0	0	-	-	-	-	Covered	T57,T55,T59
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T57,T55,T59
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T55,T188,T203
StableSt	-	-	-	-	-	-	0	Covered	T57,T55,T59
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7780736	85	0	0
CntIncr_A	7780736	2370	0	0
CntNoWrap_A	7780736	7116440	0	0
DetectStDropOut_A	7780736	0	0	0
DetectedOut_A	7780736	3205	0	0
DetectedPulseOut_A	7780736	41	0	0
DisabledIdleSt_A	7780736	6990588	0	0
DisabledNoDetection_A	7780736	6992841	0	0
EnterDebounceSt_A	7780736	44	0	0
EnterDetectSt_A	7780736	41	0	0
EnterStableSt_A	7780736	41	0	0
PulseIsPulse_A	7780736	41	0	0
StayInStableSt	7780736	3143	0	0
gen_high_level_sva.HighLevelEvent_A	7780736	7118843	0	0
gen_not_sticky_sva.StableStDropOut_A	7780736	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	85	0	0
T44	1139	0	0	0
T45	102206	0	0	0
T46	18603	0	0	0
T52	0	2	0	0
T55	0	4	0	0
T57	2765	2	0	0
T59	0	2	0	0
T84	0	1	0	0
T101	718	0	0	0
T172	439	0	0	0
T173	420	0	0	0
T174	411	0	0	0
T175	424	0	0	0
T188	0	4	0	0
T203	0	2	0	0
T204	0	2	0	0
T205	0	2	0	0
T206	0	2	0	0
T207	495	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	2370	0	0
T44	1139	0	0	0
T45	102206	0	0	0
T46	18603	0	0	0
T52	0	78	0	0
T55	0	118	0	0
T57	2765	97	0	0
T59	0	47	0	0
T84	0	16	0	0
T101	718	0	0	0
T172	439	0	0	0
T173	420	0	0	0
T174	411	0	0	0
T175	424	0	0	0
T188	0	116	0	0
T203	0	22	0	0
T204	0	86	0	0
T205	0	50	0	0
T206	0	55	0	0
T207	495	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7116440	0	0
T13	2154	551	0	0
T14	569	168	0	0
T15	27039	26570	0	0
T26	99226	98825	0	0
T27	502	101	0	0
T28	659	258	0	0
T29	586	185	0	0
T30	548	147	0	0
T40	46119	45682	0	0
T41	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	3205	0	0
T44	1139	0	0	0
T45	102206	0	0	0
T46	18603	0	0	0
T52	0	224	0	0
T55	0	85	0	0
T57	2765	42	0	0
T59	0	42	0	0
T101	718	0	0	0
T172	439	0	0	0
T173	420	0	0	0
T174	411	0	0	0
T175	424	0	0	0
T188	0	153	0	0
T203	0	68	0	0
T204	0	43	0	0
T205	0	38	0	0
T206	0	67	0	0
T207	495	0	0	0
T208	0	151	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	41	0	0
T44	1139	0	0	0
T45	102206	0	0	0
T46	18603	0	0	0
T52	0	1	0	0
T55	0	2	0	0
T57	2765	1	0	0
T59	0	1	0	0
T101	718	0	0	0
T172	439	0	0	0
T173	420	0	0	0
T174	411	0	0	0
T175	424	0	0	0
T188	0	2	0	0
T203	0	1	0	0
T204	0	1	0	0
T205	0	1	0	0
T206	0	1	0	0
T207	495	0	0	0
T208	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	6990588	0	0
T13	2154	551	0	0
T14	569	168	0	0
T15	27039	26570	0	0
T26	99226	98825	0	0
T27	502	101	0	0
T28	659	258	0	0
T29	586	185	0	0
T30	548	147	0	0
T40	46119	45682	0	0
T41	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	6992841	0	0
T13	2154	554	0	0
T14	569	169	0	0
T15	27039	26581	0	0
T26	99226	98826	0	0
T27	502	102	0	0
T28	659	259	0	0
T29	586	186	0	0
T30	548	148	0	0
T40	46119	45688	0	0
T41	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	44	0	0
T44	1139	0	0	0
T45	102206	0	0	0
T46	18603	0	0	0
T52	0	1	0	0
T55	0	2	0	0
T57	2765	1	0	0
T59	0	1	0	0
T84	0	1	0	0
T101	718	0	0	0
T172	439	0	0	0
T173	420	0	0	0
T174	411	0	0	0
T175	424	0	0	0
T188	0	2	0	0
T203	0	1	0	0
T204	0	1	0	0
T205	0	1	0	0
T206	0	1	0	0
T207	495	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	41	0	0
T44	1139	0	0	0
T45	102206	0	0	0
T46	18603	0	0	0
T52	0	1	0	0
T55	0	2	0	0
T57	2765	1	0	0
T59	0	1	0	0
T101	718	0	0	0
T172	439	0	0	0
T173	420	0	0	0
T174	411	0	0	0
T175	424	0	0	0
T188	0	2	0	0
T203	0	1	0	0
T204	0	1	0	0
T205	0	1	0	0
T206	0	1	0	0
T207	495	0	0	0
T208	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	41	0	0
T44	1139	0	0	0
T45	102206	0	0	0
T46	18603	0	0	0
T52	0	1	0	0
T55	0	2	0	0
T57	2765	1	0	0
T59	0	1	0	0
T101	718	0	0	0
T172	439	0	0	0
T173	420	0	0	0
T174	411	0	0	0
T175	424	0	0	0
T188	0	2	0	0
T203	0	1	0	0
T204	0	1	0	0
T205	0	1	0	0
T206	0	1	0	0
T207	495	0	0	0
T208	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	41	0	0
T44	1139	0	0	0
T45	102206	0	0	0
T46	18603	0	0	0
T52	0	1	0	0
T55	0	2	0	0
T57	2765	1	0	0
T59	0	1	0	0
T101	718	0	0	0
T172	439	0	0	0
T173	420	0	0	0
T174	411	0	0	0
T175	424	0	0	0
T188	0	2	0	0
T203	0	1	0	0
T204	0	1	0	0
T205	0	1	0	0
T206	0	1	0	0
T207	495	0	0	0
T208	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	3143	0	0
T44	1139	0	0	0
T45	102206	0	0	0
T46	18603	0	0	0
T52	0	222	0	0
T55	0	82	0	0
T57	2765	40	0	0
T59	0	40	0	0
T101	718	0	0	0
T172	439	0	0	0
T173	420	0	0	0
T174	411	0	0	0
T175	424	0	0	0
T188	0	150	0	0
T203	0	67	0	0
T204	0	41	0	0
T205	0	36	0	0
T206	0	65	0	0
T207	495	0	0	0
T208	0	149	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7118843	0	0
T13	2154	554	0	0
T14	569	169	0	0
T15	27039	26581	0	0
T26	99226	98826	0	0
T27	502	102	0	0
T28	659	259	0	0
T29	586	186	0	0
T30	548	148	0	0
T40	46119	45688	0	0
T41	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	19	0	0
T55	969	1	0	0
T142	15590	0	0	0
T166	0	1	0	0
T167	0	1	0	0
T176	0	1	0	0
T188	941	1	0	0
T203	0	1	0	0
T208	0	2	0	0
T209	0	1	0	0
T210	0	1	0	0
T211	0	2	0	0
T212	504	0	0	0
T213	499	0	0	0
T214	1475	0	0	0
T215	423	0	0	0
T216	7147	0	0	0
T217	505	0	0	0
T218	431	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T40,T41,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T40,T41,T13
1	0	Covered	T40,T41,T13
1	1	Covered	T40,T41,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T13,T14,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T40,T41,T13	VC_COV_UNR
1	Covered	T13,T14,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T13,T14,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T20
1	0	Covered	T40,T41,T13
1	1	Covered	T13,T14,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T20
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T20
0	1	Covered	T21,T57,T58
1	0	Covered	T85

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T14,T20
1	-	Covered	T21,T57,T58

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4
DetectSt	168	Covered	T4
IdleSt	163	Covered	T4
StableSt	191	Covered	T4

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4
DebounceSt->IdleSt	163	Covered	T4
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T4
IdleSt->DebounceSt	148	Covered	T4
StableSt->IdleSt	206	Covered	T4

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T13,T14,T20
0	1	Covered	T13,T14,T20
0	0	Excluded	T40,T41,T13	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T20
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T13,T14,T20
IdleSt	0	-	-	-	-	-	-	Covered	T40,T41,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T84
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T14,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T219,T176,T177
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T14,T20
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T13,T14,T20
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T21,T57,T58
StableSt	-	-	-	-	-	-	0	Covered	T13,T14,T20
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7780736	148	0	0
CntIncr_A	7780736	211310	0	0
CntNoWrap_A	7780736	7116377	0	0
DetectStDropOut_A	7780736	0	0	0
DetectedOut_A	7780736	210012	0	0
DetectedPulseOut_A	7780736	70	0	0
DisabledIdleSt_A	7780736	6507998	0	0
DisabledNoDetection_A	7780736	6510253	0	0
EnterDebounceSt_A	7780736	78	0	0
EnterDetectSt_A	7780736	70	0	0
EnterStableSt_A	7780736	70	0	0
PulseIsPulse_A	7780736	70	0	0
StayInStableSt	7780736	209907	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7780736	3018	0	0
gen_low_level_sva.LowLevelEvent_A	7780736	7118843	0	0
gen_not_sticky_sva.StableStDropOut_A	7780736	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	148	0	0
T13	2154	2	0	0
T14	569	2	0	0
T15	27039	0	0	0
T20	0	2	0	0
T21	0	2	0	0
T22	0	2	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T53	0	2	0	0
T55	0	4	0	0
T57	0	2	0	0
T58	0	4	0	0
T63	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	211310	0	0
T13	2154	32	0	0
T14	569	50	0	0
T15	27039	0	0	0
T20	0	81	0	0
T21	0	81	0	0
T22	0	17	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T53	0	89	0	0
T55	0	118	0	0
T57	0	97	0	0
T58	0	124360	0	0
T63	0	53355	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7116377	0	0
T13	2154	549	0	0
T14	569	166	0	0
T15	27039	26570	0	0
T26	99226	98825	0	0
T27	502	101	0	0
T28	659	258	0	0
T29	586	185	0	0
T30	548	147	0	0
T40	46119	45682	0	0
T41	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	210012	0	0
T13	2154	42	0	0
T14	569	109	0	0
T15	27039	0	0	0
T20	0	38	0	0
T21	0	208	0	0
T22	0	54	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T53	0	39	0	0
T55	0	236	0	0
T57	0	31	0	0
T58	0	124485	0	0
T63	0	50770	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	70	0	0
T13	2154	1	0	0
T14	569	1	0	0
T15	27039	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T22	0	1	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T53	0	1	0	0
T55	0	2	0	0
T57	0	1	0	0
T58	0	2	0	0
T63	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	6507998	0	0
T13	2154	460	0	0
T14	569	4	0	0
T15	27039	26570	0	0
T26	99226	98825	0	0
T27	502	101	0	0
T28	659	258	0	0
T29	586	185	0	0
T30	548	147	0	0
T40	46119	45682	0	0
T41	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	6510253	0	0
T13	2154	462	0	0
T14	569	4	0	0
T15	27039	26581	0	0
T26	99226	98826	0	0
T27	502	102	0	0
T28	659	259	0	0
T29	586	186	0	0
T30	548	148	0	0
T40	46119	45688	0	0
T41	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	78	0	0
T13	2154	1	0	0
T14	569	1	0	0
T15	27039	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T22	0	1	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T53	0	1	0	0
T55	0	2	0	0
T57	0	1	0	0
T58	0	2	0	0
T63	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	70	0	0
T13	2154	1	0	0
T14	569	1	0	0
T15	27039	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T22	0	1	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T53	0	1	0	0
T55	0	2	0	0
T57	0	1	0	0
T58	0	2	0	0
T63	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	70	0	0
T13	2154	1	0	0
T14	569	1	0	0
T15	27039	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T22	0	1	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T53	0	1	0	0
T55	0	2	0	0
T57	0	1	0	0
T58	0	2	0	0
T63	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	70	0	0
T13	2154	1	0	0
T14	569	1	0	0
T15	27039	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T22	0	1	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T53	0	1	0	0
T55	0	2	0	0
T57	0	1	0	0
T58	0	2	0	0
T63	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	209907	0	0
T13	2154	40	0	0
T14	569	107	0	0
T15	27039	0	0	0
T20	0	36	0	0
T21	0	207	0	0
T22	0	52	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T53	0	37	0	0
T55	0	234	0	0
T57	0	30	0	0
T58	0	124482	0	0
T63	0	50768	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	3018	0	0
T13	2154	9	0	0
T14	569	1	0	0
T15	27039	0	0	0
T26	99226	5	0	0
T27	502	4	0	0
T28	659	4	0	0
T29	586	0	0	0
T30	548	3	0	0
T31	1338	6	0	0
T41	522	7	0	0
T66	0	5	0	0
T67	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7118843	0	0
T13	2154	554	0	0
T14	569	169	0	0
T15	27039	26581	0	0
T26	99226	98826	0	0
T27	502	102	0	0
T28	659	259	0	0
T29	586	186	0	0
T30	548	148	0	0
T40	46119	45688	0	0
T41	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	34	0	0
T21	33629	1	0	0
T22	481	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T55	0	2	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T61	18429	0	0	0
T144	491	0	0	0
T171	424	0	0	0
T188	0	2	0	0
T189	491	0	0	0
T190	506	0	0	0
T191	448	0	0	0
T192	492	0	0	0
T193	2538	0	0	0
T206	0	2	0	0
T219	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T40,T41,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T40,T41,T13
1	0	Covered	T40,T41,T13
1	1	Covered	T40,T41,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T13,T22,T57

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T40,T41,T13	VC_COV_UNR
1	Covered	T13,T22,T57

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T13,T57,T58

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T22
1	0	Covered	T40,T41,T13
1	1	Covered	T13,T22,T57

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T57,T58
0	1	Covered	T95,T178,T117
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T57,T58
0	1	Covered	T58,T59,T219
1	0	Covered	T85

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T57,T58
1	-	Covered	T58,T59,T219

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4
DetectSt	168	Covered	T4
IdleSt	163	Covered	T4
StableSt	191	Covered	T4

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4
DebounceSt->IdleSt	163	Covered	T4
DetectSt->IdleSt	186	Covered	T4
DetectSt->StableSt	191	Covered	T4
IdleSt->DebounceSt	148	Covered	T4
StableSt->IdleSt	206	Covered	T4

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T13,T22,T57
0	1	Covered	T13,T22,T57
0	0	Excluded	T40,T41,T13	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T57,T58
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T13,T22,T57
IdleSt	0	-	-	-	-	-	-	Covered	T40,T41,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T84
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T57,T58
DebounceSt	-	0	1	0	-	-	-	Covered	T22,T45,T58
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T22,T57
DetectSt	-	-	-	-	1	-	-	Covered	T95,T178,T117
DetectSt	-	-	-	-	0	1	-	Covered	T13,T57,T58
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T58,T59,T219
StableSt	-	-	-	-	-	-	0	Covered	T13,T57,T58
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7780736	126	0	0
CntIncr_A	7780736	190011	0	0
CntNoWrap_A	7780736	7116399	0	0
DetectStDropOut_A	7780736	3	0	0
DetectedOut_A	7780736	70285	0	0
DetectedPulseOut_A	7780736	52	0	0
DisabledIdleSt_A	7780736	6722866	0	0
DisabledNoDetection_A	7780736	6725125	0	0
EnterDebounceSt_A	7780736	71	0	0
EnterDetectSt_A	7780736	55	0	0
EnterStableSt_A	7780736	52	0	0
PulseIsPulse_A	7780736	52	0	0
StayInStableSt	7780736	70205	0	0
gen_high_level_sva.HighLevelEvent_A	7780736	7118843	0	0
gen_not_sticky_sva.StableStDropOut_A	7780736	23	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	126	0	0
T13	2154	2	0	0
T14	569	0	0	0
T15	27039	0	0	0
T22	0	1	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T45	0	1	0	0
T57	0	2	0	0
T58	0	5	0	0
T59	0	2	0	0
T95	0	2	0	0
T121	0	2	0	0
T205	0	2	0	0
T219	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	190011	0	0
T13	2154	32	0	0
T14	569	0	0	0
T15	27039	0	0	0
T22	0	17	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T45	0	43	0	0
T57	0	97	0	0
T58	0	186540	0	0
T59	0	47	0	0
T95	0	35	0	0
T121	0	19	0	0
T205	0	50	0	0
T219	0	120	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7116399	0	0
T13	2154	549	0	0
T14	569	168	0	0
T15	27039	26570	0	0
T26	99226	98825	0	0
T27	502	101	0	0
T28	659	258	0	0
T29	586	185	0	0
T30	548	147	0	0
T40	46119	45682	0	0
T41	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	3	0	0
T95	519	1	0	0
T117	0	1	0	0
T169	5336	0	0	0
T178	8079	1	0	0
T206	25425	0	0	0
T219	925	0	0	0
T220	22284	0	0	0
T221	6749	0	0	0
T222	19409	0	0	0
T223	6808	0	0	0
T224	505	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	70285	0	0
T13	2154	55	0	0
T14	569	0	0	0
T15	27039	0	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T57	0	42	0	0
T58	0	66390	0	0
T59	0	101	0	0
T121	0	68	0	0
T132	0	300	0	0
T203	0	69	0	0
T205	0	95	0	0
T206	0	150	0	0
T219	0	15	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	52	0	0
T13	2154	1	0	0
T14	569	0	0	0
T15	27039	0	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T57	0	1	0	0
T58	0	2	0	0
T59	0	1	0	0
T121	0	1	0	0
T132	0	3	0	0
T203	0	1	0	0
T205	0	1	0	0
T206	0	3	0	0
T219	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	6722866	0	0
T13	2154	460	0	0
T14	569	4	0	0
T15	27039	26570	0	0
T26	99226	98825	0	0
T27	502	101	0	0
T28	659	258	0	0
T29	586	185	0	0
T30	548	147	0	0
T40	46119	45682	0	0
T41	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	6725125	0	0
T13	2154	462	0	0
T14	569	4	0	0
T15	27039	26581	0	0
T26	99226	98826	0	0
T27	502	102	0	0
T28	659	259	0	0
T29	586	186	0	0
T30	548	148	0	0
T40	46119	45688	0	0
T41	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	71	0	0
T13	2154	1	0	0
T14	569	0	0	0
T15	27039	0	0	0
T22	0	1	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T45	0	1	0	0
T57	0	1	0	0
T58	0	3	0	0
T59	0	1	0	0
T95	0	1	0	0
T121	0	1	0	0
T205	0	1	0	0
T219	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	55	0	0
T13	2154	1	0	0
T14	569	0	0	0
T15	27039	0	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T57	0	1	0	0
T58	0	2	0	0
T59	0	1	0	0
T95	0	1	0	0
T121	0	1	0	0
T203	0	1	0	0
T205	0	1	0	0
T206	0	3	0	0
T219	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	52	0	0
T13	2154	1	0	0
T14	569	0	0	0
T15	27039	0	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T57	0	1	0	0
T58	0	2	0	0
T59	0	1	0	0
T121	0	1	0	0
T132	0	3	0	0
T203	0	1	0	0
T205	0	1	0	0
T206	0	3	0	0
T219	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	52	0	0
T13	2154	1	0	0
T14	569	0	0	0
T15	27039	0	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T57	0	1	0	0
T58	0	2	0	0
T59	0	1	0	0
T121	0	1	0	0
T132	0	3	0	0
T203	0	1	0	0
T205	0	1	0	0
T206	0	3	0	0
T219	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	70205	0	0
T13	2154	53	0	0
T14	569	0	0	0
T15	27039	0	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T57	0	40	0	0
T58	0	66387	0	0
T59	0	100	0	0
T121	0	66	0	0
T132	0	295	0	0
T203	0	67	0	0
T205	0	93	0	0
T206	0	147	0	0
T219	0	14	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7118843	0	0
T13	2154	554	0	0
T14	569	169	0	0
T15	27039	26581	0	0
T26	99226	98826	0	0
T27	502	102	0	0
T28	659	259	0	0
T29	586	186	0	0
T30	548	148	0	0
T40	46119	45688	0	0
T41	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	23	0	0
T58	377784	1	0	0
T59	0	1	0	0
T132	0	1	0	0
T136	16731	0	0	0
T206	0	3	0	0
T209	0	1	0	0
T211	0	1	0	0
T219	0	1	0	0
T225	0	1	0	0
T226	0	1	0	0
T227	0	1	0	0
T228	426	0	0	0
T229	425	0	0	0
T230	503	0	0	0
T231	525	0	0	0
T232	402	0	0	0
T233	513	0	0	0
T234	505	0	0	0
T235	452	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T40,T41,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T40,T41,T13
1	0	Covered	T40,T41,T13
1	1	Covered	T40,T41,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T21,T54,T45

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T40,T41,T13	VC_COV_UNR
1	Covered	T21,T54,T45

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T21,T54,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T54
1	0	Covered	T40,T41,T13
1	1	Covered	T21,T54,T45

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T21,T54,T45
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T21,T54,T45
0	1	Covered	T60,T51,T188
1	0	Covered	T85

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T21,T54,T45
1	-	Covered	T60,T51,T188

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4
DetectSt	168	Covered	T4
IdleSt	163	Covered	T4
StableSt	191	Covered	T4

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4
DebounceSt->IdleSt	163	Covered	T4
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T4
IdleSt->DebounceSt	148	Covered	T4
StableSt->IdleSt	206	Covered	T4

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T21,T54,T45
0	1	Covered	T21,T54,T45
0	0	Excluded	T40,T41,T13	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T54,T45
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T21,T54,T45
IdleSt	0	-	-	-	-	-	-	Covered	T40,T41,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T84
DebounceSt	-	0	1	1	-	-	-	Covered	T21,T54,T45
DebounceSt	-	0	1	0	-	-	-	Covered	T132,T97,T236
DebounceSt	-	0	0	-	-	-	-	Covered	T21,T54,T45
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T21,T54,T45
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T60,T51,T188
StableSt	-	-	-	-	-	-	0	Covered	T21,T54,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7780736	83	0	0
CntIncr_A	7780736	2985	0	0
CntNoWrap_A	7780736	7116442	0	0
DetectStDropOut_A	7780736	0	0	0
DetectedOut_A	7780736	2294	0	0
DetectedPulseOut_A	7780736	39	0	0
DisabledIdleSt_A	7780736	7098776	0	0
DisabledNoDetection_A	7780736	7101039	0	0
EnterDebounceSt_A	7780736	44	0	0
EnterDetectSt_A	7780736	39	0	0
EnterStableSt_A	7780736	39	0	0
PulseIsPulse_A	7780736	39	0	0
StayInStableSt	7780736	2229	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7780736	6593	0	0
gen_low_level_sva.LowLevelEvent_A	7780736	7118843	0	0
gen_not_sticky_sva.StableStDropOut_A	7780736	12	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	83	0	0
T21	33629	2	0	0
T22	481	0	0	0
T45	0	2	0	0
T51	0	2	0	0
T53	0	2	0	0
T54	0	2	0	0
T55	0	2	0	0
T59	0	2	0	0
T60	0	4	0	0
T61	18429	0	0	0
T95	0	2	0	0
T144	491	0	0	0
T171	424	0	0	0
T188	0	4	0	0
T189	491	0	0	0
T190	506	0	0	0
T191	448	0	0	0
T192	492	0	0	0
T193	2538	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	2985	0	0
T21	33629	81	0	0
T22	481	0	0	0
T45	0	43	0	0
T51	0	71	0	0
T53	0	89	0	0
T54	0	37	0	0
T55	0	59	0	0
T59	0	47	0	0
T60	0	44	0	0
T61	18429	0	0	0
T95	0	35	0	0
T144	491	0	0	0
T171	424	0	0	0
T188	0	116	0	0
T189	491	0	0	0
T190	506	0	0	0
T191	448	0	0	0
T192	492	0	0	0
T193	2538	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7116442	0	0
T13	2154	551	0	0
T14	569	168	0	0
T15	27039	26570	0	0
T26	99226	98825	0	0
T27	502	101	0	0
T28	659	258	0	0
T29	586	185	0	0
T30	548	147	0	0
T40	46119	45682	0	0
T41	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	2294	0	0
T21	33629	64	0	0
T22	481	0	0	0
T45	0	51	0	0
T51	0	162	0	0
T53	0	39	0	0
T54	0	42	0	0
T55	0	45	0	0
T59	0	91	0	0
T60	0	85	0	0
T61	18429	0	0	0
T95	0	39	0	0
T144	491	0	0	0
T171	424	0	0	0
T188	0	111	0	0
T189	491	0	0	0
T190	506	0	0	0
T191	448	0	0	0
T192	492	0	0	0
T193	2538	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	39	0	0
T21	33629	1	0	0
T22	481	0	0	0
T45	0	1	0	0
T51	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T59	0	1	0	0
T60	0	2	0	0
T61	18429	0	0	0
T95	0	1	0	0
T144	491	0	0	0
T171	424	0	0	0
T188	0	2	0	0
T189	491	0	0	0
T190	506	0	0	0
T191	448	0	0	0
T192	492	0	0	0
T193	2538	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7098776	0	0
T13	2154	551	0	0
T14	569	168	0	0
T15	27039	26570	0	0
T26	99226	98825	0	0
T27	502	101	0	0
T28	659	258	0	0
T29	586	185	0	0
T30	548	147	0	0
T40	46119	45682	0	0
T41	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7101039	0	0
T13	2154	554	0	0
T14	569	169	0	0
T15	27039	26581	0	0
T26	99226	98826	0	0
T27	502	102	0	0
T28	659	259	0	0
T29	586	186	0	0
T30	548	148	0	0
T40	46119	45688	0	0
T41	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	44	0	0
T21	33629	1	0	0
T22	481	0	0	0
T45	0	1	0	0
T51	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T59	0	1	0	0
T60	0	2	0	0
T61	18429	0	0	0
T95	0	1	0	0
T144	491	0	0	0
T171	424	0	0	0
T188	0	2	0	0
T189	491	0	0	0
T190	506	0	0	0
T191	448	0	0	0
T192	492	0	0	0
T193	2538	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	39	0	0
T21	33629	1	0	0
T22	481	0	0	0
T45	0	1	0	0
T51	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T59	0	1	0	0
T60	0	2	0	0
T61	18429	0	0	0
T95	0	1	0	0
T144	491	0	0	0
T171	424	0	0	0
T188	0	2	0	0
T189	491	0	0	0
T190	506	0	0	0
T191	448	0	0	0
T192	492	0	0	0
T193	2538	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	39	0	0
T21	33629	1	0	0
T22	481	0	0	0
T45	0	1	0	0
T51	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T59	0	1	0	0
T60	0	2	0	0
T61	18429	0	0	0
T95	0	1	0	0
T144	491	0	0	0
T171	424	0	0	0
T188	0	2	0	0
T189	491	0	0	0
T190	506	0	0	0
T191	448	0	0	0
T192	492	0	0	0
T193	2538	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	39	0	0
T21	33629	1	0	0
T22	481	0	0	0
T45	0	1	0	0
T51	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T59	0	1	0	0
T60	0	2	0	0
T61	18429	0	0	0
T95	0	1	0	0
T144	491	0	0	0
T171	424	0	0	0
T188	0	2	0	0
T189	491	0	0	0
T190	506	0	0	0
T191	448	0	0	0
T192	492	0	0	0
T193	2538	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	2229	0	0
T21	33629	62	0	0
T22	481	0	0	0
T45	0	49	0	0
T51	0	161	0	0
T53	0	37	0	0
T54	0	40	0	0
T55	0	43	0	0
T59	0	89	0	0
T60	0	82	0	0
T61	18429	0	0	0
T95	0	37	0	0
T144	491	0	0	0
T171	424	0	0	0
T188	0	108	0	0
T189	491	0	0	0
T190	506	0	0	0
T191	448	0	0	0
T192	492	0	0	0
T193	2538	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	6593	0	0
T13	2154	4	0	0
T14	569	0	0	0
T15	27039	14	0	0
T16	0	33	0	0
T26	99226	0	0	0
T27	502	4	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	0	5	0	0
T32	0	26	0	0
T40	46119	25	0	0
T41	522	3	0	0
T66	0	8	0	0
T67	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7118843	0	0
T13	2154	554	0	0
T14	569	169	0	0
T15	27039	26581	0	0
T26	99226	98826	0	0
T27	502	102	0	0
T28	659	259	0	0
T29	586	186	0	0
T30	548	148	0	0
T40	46119	45688	0	0
T41	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	12	0	0
T51	5443	1	0	0
T59	2330	0	0	0
T60	603	1	0	0
T97	0	1	0	0
T117	0	1	0	0
T122	422	0	0	0
T123	3117	0	0	0
T124	493	0	0	0
T125	15469	0	0	0
T126	988	0	0	0
T176	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0
T187	0	1	0	0
T188	0	1	0	0
T209	0	1	0	0
T237	426	0	0	0
T238	494	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T40,T41,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T40,T41,T13
1	0	Covered	T40,T41,T13
1	1	Covered	T40,T41,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T14,T20,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T40,T41,T13	VC_COV_UNR
1	Covered	T14,T20,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T14,T20,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T20,T21
1	0	Covered	T40,T41,T13
1	1	Covered	T14,T20,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T20,T21
0	1	Covered	T60,T52,T239
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T20,T21
0	1	Covered	T21,T54,T55
1	0	Covered	T85

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T20,T21
1	-	Covered	T21,T54,T55

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4
DetectSt	168	Covered	T4
IdleSt	163	Covered	T4
StableSt	191	Covered	T4

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4
DebounceSt->IdleSt	163	Covered	T4
DetectSt->IdleSt	186	Covered	T4
DetectSt->StableSt	191	Covered	T4
IdleSt->DebounceSt	148	Covered	T4
StableSt->IdleSt	206	Covered	T4

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T20,T21
0	1	Covered	T14,T20,T21
0	0	Excluded	T40,T41,T13	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T20,T21
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T20,T21
IdleSt	0	-	-	-	-	-	-	Covered	T40,T41,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T84
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T20,T21
DebounceSt	-	0	1	0	-	-	-	Covered	T21,T51,T95
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T20,T21
DetectSt	-	-	-	-	1	-	-	Covered	T60,T52,T239
DetectSt	-	-	-	-	0	1	-	Covered	T14,T20,T21
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T21,T54,T55
StableSt	-	-	-	-	-	-	0	Covered	T14,T20,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7780736	144	0	0
CntIncr_A	7780736	61316	0	0
CntNoWrap_A	7780736	7116381	0	0
DetectStDropOut_A	7780736	3	0	0
DetectedOut_A	7780736	5210	0	0
DetectedPulseOut_A	7780736	65	0	0
DisabledIdleSt_A	7780736	6989545	0	0
DisabledNoDetection_A	7780736	6991798	0	0
EnterDebounceSt_A	7780736	78	0	0
EnterDetectSt_A	7780736	68	0	0
EnterStableSt_A	7780736	65	0	0
PulseIsPulse_A	7780736	65	0	0
StayInStableSt	7780736	5113	0	0
gen_high_level_sva.HighLevelEvent_A	7780736	7118843	0	0
gen_not_sticky_sva.StableStDropOut_A	7780736	32	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	144	0	0
T14	569	2	0	0
T15	27039	0	0	0
T16	23425	0	0	0
T20	0	2	0	0
T21	0	3	0	0
T22	0	2	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T54	0	2	0	0
T55	0	2	0	0
T56	0	2	0	0
T57	0	2	0	0
T60	0	4	0	0
T63	0	2	0	0
T66	494	0	0	0
T67	422	0	0	0
T68	631	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	61316	0	0
T14	569	50	0	0
T15	27039	0	0	0
T16	23425	0	0	0
T20	0	81	0	0
T21	0	162	0	0
T22	0	17	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T54	0	37	0	0
T55	0	59	0	0
T56	0	58	0	0
T57	0	97	0	0
T60	0	44	0	0
T63	0	56351	0	0
T66	494	0	0	0
T67	422	0	0	0
T68	631	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7116381	0	0
T13	2154	551	0	0
T14	569	166	0	0
T15	27039	26570	0	0
T26	99226	98825	0	0
T27	502	101	0	0
T28	659	258	0	0
T29	586	185	0	0
T30	548	147	0	0
T40	46119	45682	0	0
T41	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	3	0	0
T52	791	1	0	0
T59	2330	0	0	0
T60	603	1	0	0
T122	422	0	0	0
T123	3117	0	0	0
T124	493	0	0	0
T125	15469	0	0	0
T126	988	0	0	0
T237	426	0	0	0
T239	0	1	0	0
T240	492	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	5210	0	0
T14	569	38	0	0
T15	27039	0	0	0
T16	23425	0	0	0
T20	0	38	0	0
T21	0	71	0	0
T22	0	55	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T54	0	17	0	0
T55	0	40	0	0
T56	0	22	0	0
T57	0	170	0	0
T60	0	17	0	0
T63	0	41	0	0
T66	494	0	0	0
T67	422	0	0	0
T68	631	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	65	0	0
T14	569	1	0	0
T15	27039	0	0	0
T16	23425	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T22	0	1	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T60	0	1	0	0
T63	0	1	0	0
T66	494	0	0	0
T67	422	0	0	0
T68	631	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	6989545	0	0
T13	2154	551	0	0
T14	569	4	0	0
T15	27039	26570	0	0
T26	99226	98825	0	0
T27	502	101	0	0
T28	659	258	0	0
T29	586	185	0	0
T30	548	147	0	0
T40	46119	45682	0	0
T41	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	6991798	0	0
T13	2154	554	0	0
T14	569	4	0	0
T15	27039	26581	0	0
T26	99226	98826	0	0
T27	502	102	0	0
T28	659	259	0	0
T29	586	186	0	0
T30	548	148	0	0
T40	46119	45688	0	0
T41	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	78	0	0
T14	569	1	0	0
T15	27039	0	0	0
T16	23425	0	0	0
T20	0	1	0	0
T21	0	2	0	0
T22	0	1	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T60	0	2	0	0
T63	0	2	0	0
T66	494	0	0	0
T67	422	0	0	0
T68	631	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	68	0	0
T14	569	1	0	0
T15	27039	0	0	0
T16	23425	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T22	0	1	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T60	0	2	0	0
T63	0	1	0	0
T66	494	0	0	0
T67	422	0	0	0
T68	631	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	65	0	0
T14	569	1	0	0
T15	27039	0	0	0
T16	23425	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T22	0	1	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T60	0	1	0	0
T63	0	1	0	0
T66	494	0	0	0
T67	422	0	0	0
T68	631	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	65	0	0
T14	569	1	0	0
T15	27039	0	0	0
T16	23425	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T22	0	1	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T60	0	1	0	0
T63	0	1	0	0
T66	494	0	0	0
T67	422	0	0	0
T68	631	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	5113	0	0
T14	569	36	0	0
T15	27039	0	0	0
T16	23425	0	0	0
T20	0	36	0	0
T21	0	70	0	0
T22	0	53	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T54	0	16	0	0
T55	0	39	0	0
T56	0	21	0	0
T57	0	168	0	0
T60	0	16	0	0
T63	0	39	0	0
T66	494	0	0	0
T67	422	0	0	0
T68	631	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7118843	0	0
T13	2154	554	0	0
T14	569	169	0	0
T15	27039	26581	0	0
T26	99226	98826	0	0
T27	502	102	0	0
T28	659	259	0	0
T29	586	186	0	0
T30	548	148	0	0
T40	46119	45688	0	0
T41	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	32	0	0
T21	33629	1	0	0
T22	481	0	0	0
T51	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T60	0	1	0	0
T61	18429	0	0	0
T132	0	1	0	0
T144	491	0	0	0
T171	424	0	0	0
T188	0	1	0	0
T189	491	0	0	0
T190	506	0	0	0
T191	448	0	0	0
T192	492	0	0	0
T193	2538	0	0	0
T206	0	1	0	0
T241	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T40,T41,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T40,T41,T13
1	0	Covered	T40,T41,T13
1	1	Covered	T40,T41,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T13,T56,T51

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T40,T41,T13	VC_COV_UNR
1	Covered	T13,T56,T51

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T13,T56,T51

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T20
1	0	Covered	T40,T41,T13
1	1	Covered	T13,T56,T51

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T56,T51
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T56,T51
0	1	Covered	T51,T52,T188
1	0	Covered	T85

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T56,T51
1	-	Covered	T51,T52,T188

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4
DetectSt	168	Covered	T4
IdleSt	163	Covered	T4
StableSt	191	Covered	T4

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4
DebounceSt->IdleSt	163	Covered	T4
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T4
IdleSt->DebounceSt	148	Covered	T4
StableSt->IdleSt	206	Covered	T4

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T13,T56,T51
0	1	Covered	T13,T56,T51
0	0	Excluded	T40,T41,T13	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T56,T51
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T13,T56,T51
IdleSt	0	-	-	-	-	-	-	Covered	T40,T41,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T84
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T56,T51
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T56,T51
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T13,T56,T51
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T51,T52,T188
StableSt	-	-	-	-	-	-	0	Covered	T13,T56,T51
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7780736	73	0	0
CntIncr_A	7780736	60022	0	0
CntNoWrap_A	7780736	7116452	0	0
DetectStDropOut_A	7780736	0	0	0
DetectedOut_A	7780736	2517	0	0
DetectedPulseOut_A	7780736	36	0	0
DisabledIdleSt_A	7780736	6750099	0	0
DisabledNoDetection_A	7780736	6752358	0	0
EnterDebounceSt_A	7780736	37	0	0
EnterDetectSt_A	7780736	36	0	0
EnterStableSt_A	7780736	36	0	0
PulseIsPulse_A	7780736	36	0	0
StayInStableSt	7780736	2456	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7780736	6235	0	0
gen_low_level_sva.LowLevelEvent_A	7780736	7118843	0	0
gen_not_sticky_sva.StableStDropOut_A	7780736	10	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	73	0	0
T13	2154	2	0	0
T14	569	0	0	0
T15	27039	0	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T51	0	4	0	0
T52	0	2	0	0
T56	0	2	0	0
T84	0	1	0	0
T95	0	2	0	0
T188	0	2	0	0
T206	0	8	0	0
T219	0	2	0	0
T241	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	60022	0	0
T13	2154	32	0	0
T14	569	0	0	0
T15	27039	0	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T51	0	142	0	0
T52	0	78	0	0
T56	0	58	0	0
T84	0	15	0	0
T95	0	35	0	0
T188	0	58	0	0
T206	0	210	0	0
T219	0	60	0	0
T241	0	21	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7116452	0	0
T13	2154	549	0	0
T14	569	168	0	0
T15	27039	26570	0	0
T26	99226	98825	0	0
T27	502	101	0	0
T28	659	258	0	0
T29	586	185	0	0
T30	548	147	0	0
T40	46119	45682	0	0
T41	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	2517	0	0
T13	2154	42	0	0
T14	569	0	0	0
T15	27039	0	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T51	0	307	0	0
T52	0	44	0	0
T56	0	46	0	0
T95	0	39	0	0
T188	0	44	0	0
T204	0	43	0	0
T206	0	177	0	0
T219	0	228	0	0
T241	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	36	0	0
T13	2154	1	0	0
T14	569	0	0	0
T15	27039	0	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T51	0	2	0	0
T52	0	1	0	0
T56	0	1	0	0
T95	0	1	0	0
T188	0	1	0	0
T204	0	1	0	0
T206	0	4	0	0
T219	0	1	0	0
T241	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	6750099	0	0
T13	2154	460	0	0
T14	569	4	0	0
T15	27039	26570	0	0
T26	99226	98825	0	0
T27	502	101	0	0
T28	659	258	0	0
T29	586	185	0	0
T30	548	147	0	0
T40	46119	45682	0	0
T41	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	6752358	0	0
T13	2154	462	0	0
T14	569	4	0	0
T15	27039	26581	0	0
T26	99226	98826	0	0
T27	502	102	0	0
T28	659	259	0	0
T29	586	186	0	0
T30	548	148	0	0
T40	46119	45688	0	0
T41	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	37	0	0
T13	2154	1	0	0
T14	569	0	0	0
T15	27039	0	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T51	0	2	0	0
T52	0	1	0	0
T56	0	1	0	0
T84	0	1	0	0
T95	0	1	0	0
T188	0	1	0	0
T206	0	4	0	0
T219	0	1	0	0
T241	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	36	0	0
T13	2154	1	0	0
T14	569	0	0	0
T15	27039	0	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T51	0	2	0	0
T52	0	1	0	0
T56	0	1	0	0
T95	0	1	0	0
T188	0	1	0	0
T204	0	1	0	0
T206	0	4	0	0
T219	0	1	0	0
T241	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	36	0	0
T13	2154	1	0	0
T14	569	0	0	0
T15	27039	0	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T51	0	2	0	0
T52	0	1	0	0
T56	0	1	0	0
T95	0	1	0	0
T188	0	1	0	0
T204	0	1	0	0
T206	0	4	0	0
T219	0	1	0	0
T241	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	36	0	0
T13	2154	1	0	0
T14	569	0	0	0
T15	27039	0	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T51	0	2	0	0
T52	0	1	0	0
T56	0	1	0	0
T95	0	1	0	0
T188	0	1	0	0
T204	0	1	0	0
T206	0	4	0	0
T219	0	1	0	0
T241	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	2456	0	0
T13	2154	40	0	0
T14	569	0	0	0
T15	27039	0	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T51	0	304	0	0
T52	0	43	0	0
T56	0	44	0	0
T95	0	37	0	0
T188	0	43	0	0
T204	0	41	0	0
T206	0	170	0	0
T219	0	226	0	0
T241	0	40	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	6235	0	0
T13	2154	6	0	0
T14	569	0	0	0
T15	27039	13	0	0
T16	0	31	0	0
T26	99226	0	0	0
T27	502	6	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	0	7	0	0
T32	0	33	0	0
T40	46119	27	0	0
T41	522	5	0	0
T66	0	8	0	0
T67	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7118843	0	0
T13	2154	554	0	0
T14	569	169	0	0
T15	27039	26581	0	0
T26	99226	98826	0	0
T27	502	102	0	0
T28	659	259	0	0
T29	586	186	0	0
T30	548	148	0	0
T40	46119	45688	0	0
T41	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	10	0	0
T51	5443	1	0	0
T52	791	1	0	0
T89	0	1	0	0
T180	0	1	0	0
T181	0	1	0	0
T188	0	1	0	0
T206	0	1	0	0
T238	494	0	0	0
T240	492	0	0	0
T242	0	1	0	0
T243	0	1	0	0
T244	0	1	0	0
T245	406	0	0	0
T246	404	0	0	0
T247	724	0	0	0
T248	10540	0	0	0
T249	422	0	0	0
T250	15052	0	0	0