Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T40,T41,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T40,T41,T13
1	0	Covered	T40,T41,T13
1	1	Covered	T40,T41,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T21,T22,T57

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T40,T41,T13	VC_COV_UNR
1	Covered	T21,T22,T57

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T22,T57,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T57
1	0	Covered	T40,T41,T13
1	1	Covered	T21,T22,T57

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T22,T57,T45
0	1	Covered	T95,T94
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T22,T57,T45
0	1	Covered	T121,T60,T59
1	0	Covered	T85

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T22,T57,T45
1	-	Covered	T121,T60,T59

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4
DetectSt	168	Covered	T4
IdleSt	163	Covered	T4
StableSt	191	Covered	T4

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4
DebounceSt->IdleSt	163	Covered	T4
DetectSt->IdleSt	186	Covered	T4
DetectSt->StableSt	191	Covered	T4
IdleSt->DebounceSt	148	Covered	T4
StableSt->IdleSt	206	Covered	T4

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T21,T22,T57
0	1	Covered	T21,T22,T57
0	0	Excluded	T40,T41,T13	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T22,T57,T45
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T21,T22,T57
IdleSt	0	-	-	-	-	-	-	Covered	T40,T41,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T84
DebounceSt	-	0	1	1	-	-	-	Covered	T22,T57,T45
DebounceSt	-	0	1	0	-	-	-	Covered	T21,T97,T167
DebounceSt	-	0	0	-	-	-	-	Covered	T21,T22,T57
DetectSt	-	-	-	-	1	-	-	Covered	T95,T94
DetectSt	-	-	-	-	0	1	-	Covered	T22,T57,T45
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T121,T60,T59
StableSt	-	-	-	-	-	-	0	Covered	T22,T57,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7780736	113	0	0
CntIncr_A	7780736	3704	0	0
CntNoWrap_A	7780736	7116412	0	0
DetectStDropOut_A	7780736	2	0	0
DetectedOut_A	7780736	3579	0	0
DetectedPulseOut_A	7780736	50	0	0
DisabledIdleSt_A	7780736	7099492	0	0
DisabledNoDetection_A	7780736	7101756	0	0
EnterDebounceSt_A	7780736	62	0	0
EnterDetectSt_A	7780736	52	0	0
EnterStableSt_A	7780736	50	0	0
PulseIsPulse_A	7780736	50	0	0
StayInStableSt	7780736	3508	0	0
gen_high_level_sva.HighLevelEvent_A	7780736	7118843	0	0
gen_not_sticky_sva.StableStDropOut_A	7780736	28	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	113	0	0
T21	33629	1	0	0
T22	481	2	0	0
T45	0	2	0	0
T50	0	2	0	0
T57	0	2	0	0
T59	0	2	0	0
T60	0	2	0	0
T61	18429	0	0	0
T95	0	2	0	0
T121	0	2	0	0
T144	491	0	0	0
T168	0	2	0	0
T171	424	0	0	0
T189	491	0	0	0
T190	506	0	0	0
T191	448	0	0	0
T192	492	0	0	0
T193	2538	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	3704	0	0
T21	33629	81	0	0
T22	481	17	0	0
T45	0	43	0	0
T50	0	74	0	0
T57	0	97	0	0
T59	0	47	0	0
T60	0	22	0	0
T61	18429	0	0	0
T95	0	35	0	0
T121	0	19	0	0
T144	491	0	0	0
T168	0	15	0	0
T171	424	0	0	0
T189	491	0	0	0
T190	506	0	0	0
T191	448	0	0	0
T192	492	0	0	0
T193	2538	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7116412	0	0
T13	2154	551	0	0
T14	569	168	0	0
T15	27039	26570	0	0
T26	99226	98825	0	0
T27	502	101	0	0
T28	659	258	0	0
T29	586	185	0	0
T30	548	147	0	0
T40	46119	45682	0	0
T41	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	2	0	0
T81	28095	0	0	0
T94	35806	1	0	0
T95	519	1	0	0
T169	5336	0	0	0
T206	25425	0	0	0
T219	925	0	0	0
T220	22284	0	0	0
T221	6749	0	0	0
T222	19409	0	0	0
T223	6808	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	3579	0	0
T22	481	54	0	0
T44	1139	0	0	0
T45	102206	74	0	0
T46	18603	0	0	0
T50	0	43	0	0
T57	2765	170	0	0
T59	0	10	0	0
T60	0	18	0	0
T121	0	10	0	0
T168	0	118	0	0
T171	424	0	0	0
T172	439	0	0	0
T173	420	0	0	0
T174	411	0	0	0
T175	424	0	0	0
T206	0	165	0	0
T219	0	44	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	50	0	0
T22	481	1	0	0
T44	1139	0	0	0
T45	102206	1	0	0
T46	18603	0	0	0
T50	0	1	0	0
T57	2765	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T121	0	1	0	0
T168	0	1	0	0
T171	424	0	0	0
T172	439	0	0	0
T173	420	0	0	0
T174	411	0	0	0
T175	424	0	0	0
T206	0	3	0	0
T219	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7099492	0	0
T13	2154	551	0	0
T14	569	168	0	0
T15	27039	26570	0	0
T26	99226	98825	0	0
T27	502	101	0	0
T28	659	258	0	0
T29	586	185	0	0
T30	548	147	0	0
T40	46119	45682	0	0
T41	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7101756	0	0
T13	2154	554	0	0
T14	569	169	0	0
T15	27039	26581	0	0
T26	99226	98826	0	0
T27	502	102	0	0
T28	659	259	0	0
T29	586	186	0	0
T30	548	148	0	0
T40	46119	45688	0	0
T41	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	62	0	0
T21	33629	1	0	0
T22	481	1	0	0
T45	0	1	0	0
T50	0	1	0	0
T57	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	18429	0	0	0
T95	0	1	0	0
T121	0	1	0	0
T144	491	0	0	0
T168	0	1	0	0
T171	424	0	0	0
T189	491	0	0	0
T190	506	0	0	0
T191	448	0	0	0
T192	492	0	0	0
T193	2538	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	52	0	0
T22	481	1	0	0
T44	1139	0	0	0
T45	102206	1	0	0
T46	18603	0	0	0
T50	0	1	0	0
T57	2765	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T95	0	1	0	0
T121	0	1	0	0
T168	0	1	0	0
T171	424	0	0	0
T172	439	0	0	0
T173	420	0	0	0
T174	411	0	0	0
T175	424	0	0	0
T219	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	50	0	0
T22	481	1	0	0
T44	1139	0	0	0
T45	102206	1	0	0
T46	18603	0	0	0
T50	0	1	0	0
T57	2765	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T121	0	1	0	0
T168	0	1	0	0
T171	424	0	0	0
T172	439	0	0	0
T173	420	0	0	0
T174	411	0	0	0
T175	424	0	0	0
T206	0	3	0	0
T219	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	50	0	0
T22	481	1	0	0
T44	1139	0	0	0
T45	102206	1	0	0
T46	18603	0	0	0
T50	0	1	0	0
T57	2765	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T121	0	1	0	0
T168	0	1	0	0
T171	424	0	0	0
T172	439	0	0	0
T173	420	0	0	0
T174	411	0	0	0
T175	424	0	0	0
T206	0	3	0	0
T219	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	3508	0	0
T22	481	52	0	0
T44	1139	0	0	0
T45	102206	72	0	0
T46	18603	0	0	0
T50	0	41	0	0
T57	2765	168	0	0
T59	0	9	0	0
T60	0	17	0	0
T121	0	9	0	0
T168	0	116	0	0
T171	424	0	0	0
T172	439	0	0	0
T173	420	0	0	0
T174	411	0	0	0
T175	424	0	0	0
T206	0	161	0	0
T219	0	43	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7118843	0	0
T13	2154	554	0	0
T14	569	169	0	0
T15	27039	26581	0	0
T26	99226	98826	0	0
T27	502	102	0	0
T28	659	259	0	0
T29	586	186	0	0
T30	548	148	0	0
T40	46119	45688	0	0
T41	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	28	0	0
T59	2330	1	0	0
T60	603	1	0	0
T94	0	2	0	0
T97	0	2	0	0
T116	0	1	0	0
T121	497	1	0	0
T122	422	0	0	0
T123	3117	0	0	0
T124	493	0	0	0
T125	15469	0	0	0
T126	988	0	0	0
T132	0	1	0	0
T206	0	2	0	0
T211	0	1	0	0
T219	925	1	0	0
T237	426	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T40,T41,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T40,T41,T13
1	0	Covered	T40,T41,T13
1	1	Covered	T40,T41,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T21,T54,T55

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T40,T41,T13	VC_COV_UNR
1	Covered	T21,T54,T55

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T21,T54,T55

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T54
1	0	Covered	T40,T41,T13
1	1	Covered	T21,T54,T55

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T21,T54,T55
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T21,T54,T55
0	1	Covered	T55,T52,T204
1	0	Covered	T85

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T21,T54,T55
1	-	Covered	T55,T52,T204

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4
DetectSt	168	Covered	T4
IdleSt	163	Covered	T4
StableSt	191	Covered	T4

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4
DebounceSt->IdleSt	163	Covered	T4
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T4
IdleSt->DebounceSt	148	Covered	T4
StableSt->IdleSt	206	Covered	T4

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T21,T54,T55
0	1	Covered	T21,T54,T55
0	0	Excluded	T40,T41,T13	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T54,T55
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T21,T54,T55
IdleSt	0	-	-	-	-	-	-	Covered	T40,T41,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T84
DebounceSt	-	0	1	1	-	-	-	Covered	T21,T54,T55
DebounceSt	-	0	1	0	-	-	-	Covered	T210
DebounceSt	-	0	0	-	-	-	-	Covered	T21,T54,T55
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T21,T54,T55
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T55,T52,T204
StableSt	-	-	-	-	-	-	0	Covered	T21,T54,T55
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7780736	80	0	0
CntIncr_A	7780736	65463	0	0
CntNoWrap_A	7780736	7116445	0	0
DetectStDropOut_A	7780736	0	0	0
DetectedOut_A	7780736	3071	0	0
DetectedPulseOut_A	7780736	39	0	0
DisabledIdleSt_A	7780736	6858105	0	0
DisabledNoDetection_A	7780736	6860365	0	0
EnterDebounceSt_A	7780736	41	0	0
EnterDetectSt_A	7780736	39	0	0
EnterStableSt_A	7780736	39	0	0
PulseIsPulse_A	7780736	39	0	0
StayInStableSt	7780736	3009	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7780736	6278	0	0
gen_low_level_sva.LowLevelEvent_A	7780736	7118843	0	0
gen_not_sticky_sva.StableStDropOut_A	7780736	15	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	80	0	0
T21	33629	2	0	0
T22	481	0	0	0
T52	0	2	0	0
T54	0	2	0	0
T55	0	2	0	0
T59	0	2	0	0
T61	18429	0	0	0
T95	0	2	0	0
T121	0	2	0	0
T144	491	0	0	0
T171	424	0	0	0
T189	491	0	0	0
T190	506	0	0	0
T191	448	0	0	0
T192	492	0	0	0
T193	2538	0	0	0
T203	0	2	0	0
T206	0	4	0	0
T219	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	65463	0	0
T21	33629	81	0	0
T22	481	0	0	0
T52	0	78	0	0
T54	0	37	0	0
T55	0	59	0	0
T59	0	47	0	0
T61	18429	0	0	0
T95	0	35	0	0
T121	0	19	0	0
T144	491	0	0	0
T171	424	0	0	0
T189	491	0	0	0
T190	506	0	0	0
T191	448	0	0	0
T192	492	0	0	0
T193	2538	0	0	0
T203	0	22	0	0
T206	0	123	0	0
T219	0	60	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7116445	0	0
T13	2154	551	0	0
T14	569	168	0	0
T15	27039	26570	0	0
T26	99226	98825	0	0
T27	502	101	0	0
T28	659	258	0	0
T29	586	185	0	0
T30	548	147	0	0
T40	46119	45682	0	0
T41	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	3071	0	0
T21	33629	65	0	0
T22	481	0	0	0
T52	0	103	0	0
T54	0	41	0	0
T55	0	20	0	0
T59	0	182	0	0
T61	18429	0	0	0
T95	0	39	0	0
T121	0	39	0	0
T144	491	0	0	0
T171	424	0	0	0
T189	491	0	0	0
T190	506	0	0	0
T191	448	0	0	0
T192	492	0	0	0
T193	2538	0	0	0
T203	0	70	0	0
T206	0	239	0	0
T219	0	123	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	39	0	0
T21	33629	1	0	0
T22	481	0	0	0
T52	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T59	0	1	0	0
T61	18429	0	0	0
T95	0	1	0	0
T121	0	1	0	0
T144	491	0	0	0
T171	424	0	0	0
T189	491	0	0	0
T190	506	0	0	0
T191	448	0	0	0
T192	492	0	0	0
T193	2538	0	0	0
T203	0	1	0	0
T206	0	2	0	0
T219	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	6858105	0	0
T13	2154	551	0	0
T14	569	168	0	0
T15	27039	26570	0	0
T26	99226	98825	0	0
T27	502	101	0	0
T28	659	258	0	0
T29	586	185	0	0
T30	548	147	0	0
T40	46119	45682	0	0
T41	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	6860365	0	0
T13	2154	554	0	0
T14	569	169	0	0
T15	27039	26581	0	0
T26	99226	98826	0	0
T27	502	102	0	0
T28	659	259	0	0
T29	586	186	0	0
T30	548	148	0	0
T40	46119	45688	0	0
T41	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	41	0	0
T21	33629	1	0	0
T22	481	0	0	0
T52	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T59	0	1	0	0
T61	18429	0	0	0
T95	0	1	0	0
T121	0	1	0	0
T144	491	0	0	0
T171	424	0	0	0
T189	491	0	0	0
T190	506	0	0	0
T191	448	0	0	0
T192	492	0	0	0
T193	2538	0	0	0
T203	0	1	0	0
T206	0	2	0	0
T219	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	39	0	0
T21	33629	1	0	0
T22	481	0	0	0
T52	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T59	0	1	0	0
T61	18429	0	0	0
T95	0	1	0	0
T121	0	1	0	0
T144	491	0	0	0
T171	424	0	0	0
T189	491	0	0	0
T190	506	0	0	0
T191	448	0	0	0
T192	492	0	0	0
T193	2538	0	0	0
T203	0	1	0	0
T206	0	2	0	0
T219	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	39	0	0
T21	33629	1	0	0
T22	481	0	0	0
T52	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T59	0	1	0	0
T61	18429	0	0	0
T95	0	1	0	0
T121	0	1	0	0
T144	491	0	0	0
T171	424	0	0	0
T189	491	0	0	0
T190	506	0	0	0
T191	448	0	0	0
T192	492	0	0	0
T193	2538	0	0	0
T203	0	1	0	0
T206	0	2	0	0
T219	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	39	0	0
T21	33629	1	0	0
T22	481	0	0	0
T52	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T59	0	1	0	0
T61	18429	0	0	0
T95	0	1	0	0
T121	0	1	0	0
T144	491	0	0	0
T171	424	0	0	0
T189	491	0	0	0
T190	506	0	0	0
T191	448	0	0	0
T192	492	0	0	0
T193	2538	0	0	0
T203	0	1	0	0
T206	0	2	0	0
T219	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	3009	0	0
T21	33629	63	0	0
T22	481	0	0	0
T52	0	102	0	0
T54	0	39	0	0
T55	0	19	0	0
T59	0	180	0	0
T61	18429	0	0	0
T95	0	37	0	0
T121	0	37	0	0
T144	491	0	0	0
T171	424	0	0	0
T189	491	0	0	0
T190	506	0	0	0
T191	448	0	0	0
T192	492	0	0	0
T193	2538	0	0	0
T203	0	68	0	0
T206	0	235	0	0
T219	0	121	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	6278	0	0
T13	2154	5	0	0
T14	569	1	0	0
T15	27039	13	0	0
T16	0	23	0	0
T26	99226	0	0	0
T27	502	6	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	0	6	0	0
T32	0	24	0	0
T40	46119	28	0	0
T41	522	4	0	0
T66	0	7	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7118843	0	0
T13	2154	554	0	0
T14	569	169	0	0
T15	27039	26581	0	0
T26	99226	98826	0	0
T27	502	102	0	0
T28	659	259	0	0
T29	586	186	0	0
T30	548	148	0	0
T40	46119	45688	0	0
T41	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	15	0	0
T52	791	1	0	0
T55	969	1	0	0
T94	0	2	0	0
T152	0	1	0	0
T178	0	1	0	0
T180	0	1	0	0
T187	0	1	0	0
T204	0	1	0	0
T211	0	1	0	0
T212	504	0	0	0
T213	499	0	0	0
T214	1475	0	0	0
T215	423	0	0	0
T216	7147	0	0	0
T240	492	0	0	0
T242	0	1	0	0
T247	724	0	0	0
T248	10540	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T40,T41,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T40,T41,T13
1	0	Covered	T40,T41,T13
1	1	Covered	T40,T41,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T20,T54,T57

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T40,T41,T13	VC_COV_UNR
1	Covered	T20,T54,T57

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T20,T54,T57

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T20,T54
1	0	Covered	T40,T41,T13
1	1	Covered	T20,T54,T57

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T20,T54,T57
0	1	Covered	T206,T239
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T20,T54,T57
0	1	Covered	T45,T55,T121
1	0	Covered	T85

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T20,T54,T57
1	-	Covered	T45,T55,T121

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4
DetectSt	168	Covered	T4
IdleSt	163	Covered	T4
StableSt	191	Covered	T4

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4
DebounceSt->IdleSt	163	Covered	T4
DetectSt->IdleSt	186	Covered	T4
DetectSt->StableSt	191	Covered	T4
IdleSt->DebounceSt	148	Covered	T4
StableSt->IdleSt	206	Covered	T4

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T20,T54,T57
0	1	Covered	T20,T54,T57
0	0	Excluded	T40,T41,T13	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T54,T57
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T20,T54,T57
IdleSt	0	-	-	-	-	-	-	Covered	T40,T41,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T84
DebounceSt	-	0	1	1	-	-	-	Covered	T20,T54,T57
DebounceSt	-	0	1	0	-	-	-	Covered	T117,T180,T251
DebounceSt	-	0	0	-	-	-	-	Covered	T20,T54,T57
DetectSt	-	-	-	-	1	-	-	Covered	T206,T239
DetectSt	-	-	-	-	0	1	-	Covered	T20,T54,T57
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T45,T55,T121
StableSt	-	-	-	-	-	-	0	Covered	T20,T54,T57
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7780736	151	0	0
CntIncr_A	7780736	67183	0	0
CntNoWrap_A	7780736	7116374	0	0
DetectStDropOut_A	7780736	2	0	0
DetectedOut_A	7780736	67699	0	0
DetectedPulseOut_A	7780736	70	0	0
DisabledIdleSt_A	7780736	6964667	0	0
DisabledNoDetection_A	7780736	6966925	0	0
EnterDebounceSt_A	7780736	79	0	0
EnterDetectSt_A	7780736	72	0	0
EnterStableSt_A	7780736	70	0	0
PulseIsPulse_A	7780736	70	0	0
StayInStableSt	7780736	67597	0	0
gen_high_level_sva.HighLevelEvent_A	7780736	7118843	0	0
gen_not_sticky_sva.StableStDropOut_A	7780736	37	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	151	0	0
T20	670	2	0	0
T21	33629	0	0	0
T45	0	4	0	0
T51	0	4	0	0
T54	0	2	0	0
T55	0	4	0	0
T57	0	2	0	0
T59	0	4	0	0
T79	780	0	0	0
T80	496	0	0	0
T121	0	2	0	0
T144	491	0	0	0
T168	0	2	0	0
T189	491	0	0	0
T190	506	0	0	0
T191	448	0	0	0
T192	492	0	0	0
T193	2538	0	0	0
T241	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	67183	0	0
T20	670	81	0	0
T21	33629	0	0	0
T45	0	86	0	0
T51	0	142	0	0
T54	0	37	0	0
T55	0	118	0	0
T57	0	97	0	0
T59	0	94	0	0
T79	780	0	0	0
T80	496	0	0	0
T121	0	19	0	0
T144	491	0	0	0
T168	0	15	0	0
T189	491	0	0	0
T190	506	0	0	0
T191	448	0	0	0
T192	492	0	0	0
T193	2538	0	0	0
T241	0	21	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7116374	0	0
T13	2154	551	0	0
T14	569	168	0	0
T15	27039	26570	0	0
T26	99226	98825	0	0
T27	502	101	0	0
T28	659	258	0	0
T29	586	185	0	0
T30	548	147	0	0
T40	46119	45682	0	0
T41	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	2	0	0
T169	5336	0	0	0
T206	25425	1	0	0
T223	6808	0	0	0
T239	36849	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	67699	0	0
T20	670	39	0	0
T21	33629	0	0	0
T45	0	164	0	0
T51	0	193	0	0
T54	0	42	0	0
T55	0	79	0	0
T57	0	43	0	0
T59	0	52	0	0
T79	780	0	0	0
T80	496	0	0	0
T121	0	11	0	0
T144	491	0	0	0
T168	0	1	0	0
T189	491	0	0	0
T190	506	0	0	0
T191	448	0	0	0
T192	492	0	0	0
T193	2538	0	0	0
T241	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	70	0	0
T20	670	1	0	0
T21	33629	0	0	0
T45	0	2	0	0
T51	0	2	0	0
T54	0	1	0	0
T55	0	2	0	0
T57	0	1	0	0
T59	0	2	0	0
T79	780	0	0	0
T80	496	0	0	0
T121	0	1	0	0
T144	491	0	0	0
T168	0	1	0	0
T189	491	0	0	0
T190	506	0	0	0
T191	448	0	0	0
T192	492	0	0	0
T193	2538	0	0	0
T241	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	6964667	0	0
T13	2154	551	0	0
T14	569	4	0	0
T15	27039	26570	0	0
T26	99226	98825	0	0
T27	502	101	0	0
T28	659	258	0	0
T29	586	185	0	0
T30	548	147	0	0
T40	46119	45682	0	0
T41	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	6966925	0	0
T13	2154	554	0	0
T14	569	4	0	0
T15	27039	26581	0	0
T26	99226	98826	0	0
T27	502	102	0	0
T28	659	259	0	0
T29	586	186	0	0
T30	548	148	0	0
T40	46119	45688	0	0
T41	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	79	0	0
T20	670	1	0	0
T21	33629	0	0	0
T45	0	2	0	0
T51	0	2	0	0
T54	0	1	0	0
T55	0	2	0	0
T57	0	1	0	0
T59	0	2	0	0
T79	780	0	0	0
T80	496	0	0	0
T121	0	1	0	0
T144	491	0	0	0
T168	0	1	0	0
T189	491	0	0	0
T190	506	0	0	0
T191	448	0	0	0
T192	492	0	0	0
T193	2538	0	0	0
T241	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	72	0	0
T20	670	1	0	0
T21	33629	0	0	0
T45	0	2	0	0
T51	0	2	0	0
T54	0	1	0	0
T55	0	2	0	0
T57	0	1	0	0
T59	0	2	0	0
T79	780	0	0	0
T80	496	0	0	0
T121	0	1	0	0
T144	491	0	0	0
T168	0	1	0	0
T189	491	0	0	0
T190	506	0	0	0
T191	448	0	0	0
T192	492	0	0	0
T193	2538	0	0	0
T241	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	70	0	0
T20	670	1	0	0
T21	33629	0	0	0
T45	0	2	0	0
T51	0	2	0	0
T54	0	1	0	0
T55	0	2	0	0
T57	0	1	0	0
T59	0	2	0	0
T79	780	0	0	0
T80	496	0	0	0
T121	0	1	0	0
T144	491	0	0	0
T168	0	1	0	0
T189	491	0	0	0
T190	506	0	0	0
T191	448	0	0	0
T192	492	0	0	0
T193	2538	0	0	0
T241	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	70	0	0
T20	670	1	0	0
T21	33629	0	0	0
T45	0	2	0	0
T51	0	2	0	0
T54	0	1	0	0
T55	0	2	0	0
T57	0	1	0	0
T59	0	2	0	0
T79	780	0	0	0
T80	496	0	0	0
T121	0	1	0	0
T144	491	0	0	0
T168	0	1	0	0
T189	491	0	0	0
T190	506	0	0	0
T191	448	0	0	0
T192	492	0	0	0
T193	2538	0	0	0
T241	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	67597	0	0
T20	670	37	0	0
T21	33629	0	0	0
T45	0	161	0	0
T51	0	191	0	0
T54	0	40	0	0
T55	0	77	0	0
T57	0	41	0	0
T59	0	49	0	0
T79	780	0	0	0
T80	496	0	0	0
T121	0	10	0	0
T144	491	0	0	0
T189	491	0	0	0
T190	506	0	0	0
T191	448	0	0	0
T192	492	0	0	0
T193	2538	0	0	0
T206	0	132	0	0
T241	0	40	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7118843	0	0
T13	2154	554	0	0
T14	569	169	0	0
T15	27039	26581	0	0
T26	99226	98826	0	0
T27	502	102	0	0
T28	659	259	0	0
T29	586	186	0	0
T30	548	148	0	0
T40	46119	45688	0	0
T41	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	37	0	0
T44	1139	0	0	0
T45	102206	1	0	0
T46	18603	0	0	0
T51	0	2	0	0
T55	0	2	0	0
T59	0	1	0	0
T101	718	0	0	0
T121	0	1	0	0
T165	0	2	0	0
T168	0	1	0	0
T172	439	0	0	0
T173	420	0	0	0
T174	411	0	0	0
T175	424	0	0	0
T203	0	1	0	0
T204	0	1	0	0
T206	0	1	0	0
T207	495	0	0	0
T252	1333	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T40,T41,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T40,T41,T13
1	0	Covered	T40,T41,T13
1	1	Covered	T40,T41,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T13,T21,T53

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T40,T41,T13	VC_COV_UNR
1	Covered	T13,T21,T53

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T13,T21,T53

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T20,T21
1	0	Covered	T40,T41,T13
1	1	Covered	T13,T21,T53

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T21,T53
0	1	Covered	T253
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T21,T53
0	1	Covered	T21,T55,T51
1	0	Covered	T85

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T21,T53
1	-	Covered	T21,T55,T51

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4
DetectSt	168	Covered	T4
IdleSt	163	Covered	T4
StableSt	191	Covered	T4

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4
DebounceSt->IdleSt	163	Covered	T4
DetectSt->IdleSt	186	Covered	T4
DetectSt->StableSt	191	Covered	T4
IdleSt->DebounceSt	148	Covered	T4
StableSt->IdleSt	206	Covered	T4

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T13,T21,T53
0	1	Covered	T13,T21,T53
0	0	Excluded	T40,T41,T13	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T21,T53
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T13,T21,T53
IdleSt	0	-	-	-	-	-	-	Covered	T40,T41,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T84
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T21,T53
DebounceSt	-	0	1	0	-	-	-	Covered	T52,T180
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T21,T53
DetectSt	-	-	-	-	1	-	-	Covered	T253
DetectSt	-	-	-	-	0	1	-	Covered	T13,T21,T53
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T21,T55,T51
StableSt	-	-	-	-	-	-	0	Covered	T13,T21,T53
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7780736	107	0	0
CntIncr_A	7780736	65636	0	0
CntNoWrap_A	7780736	7116418	0	0
DetectStDropOut_A	7780736	1	0	0
DetectedOut_A	7780736	3399	0	0
DetectedPulseOut_A	7780736	51	0	0
DisabledIdleSt_A	7780736	6747224	0	0
DisabledNoDetection_A	7780736	6749474	0	0
EnterDebounceSt_A	7780736	56	0	0
EnterDetectSt_A	7780736	52	0	0
EnterStableSt_A	7780736	51	0	0
PulseIsPulse_A	7780736	51	0	0
StayInStableSt	7780736	3319	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7780736	6296	0	0
gen_low_level_sva.LowLevelEvent_A	7780736	7118843	0	0
gen_not_sticky_sva.StableStDropOut_A	7780736	21	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	107	0	0
T13	2154	2	0	0
T14	569	0	0	0
T15	27039	0	0	0
T21	0	2	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T51	0	4	0	0
T52	0	1	0	0
T53	0	2	0	0
T55	0	4	0	0
T63	0	2	0	0
T188	0	4	0	0
T205	0	2	0	0
T219	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	65636	0	0
T13	2154	32	0	0
T14	569	0	0	0
T15	27039	0	0	0
T21	0	81	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T51	0	142	0	0
T52	0	78	0	0
T53	0	89	0	0
T55	0	118	0	0
T63	0	53355	0	0
T188	0	116	0	0
T205	0	50	0	0
T219	0	120	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7116418	0	0
T13	2154	549	0	0
T14	569	168	0	0
T15	27039	26570	0	0
T26	99226	98825	0	0
T27	502	101	0	0
T28	659	258	0	0
T29	586	185	0	0
T30	548	147	0	0
T40	46119	45682	0	0
T41	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	1	0	0
T253	36218	1	0	0
T254	493	0	0	0
T255	5566	0	0	0
T256	766	0	0	0
T257	28356	0	0	0
T258	423	0	0	0
T259	493	0	0	0
T260	505	0	0	0
T261	407	0	0	0
T262	668	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	3399	0	0
T13	2154	42	0	0
T14	569	0	0	0
T15	27039	0	0	0
T21	0	42	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T51	0	71	0	0
T53	0	40	0	0
T55	0	145	0	0
T63	0	41	0	0
T188	0	113	0	0
T205	0	37	0	0
T206	0	249	0	0
T219	0	53	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	51	0	0
T13	2154	1	0	0
T14	569	0	0	0
T15	27039	0	0	0
T21	0	1	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T51	0	2	0	0
T53	0	1	0	0
T55	0	2	0	0
T63	0	1	0	0
T188	0	2	0	0
T205	0	1	0	0
T206	0	3	0	0
T219	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	6747224	0	0
T13	2154	460	0	0
T14	569	168	0	0
T15	27039	26570	0	0
T26	99226	98825	0	0
T27	502	101	0	0
T28	659	258	0	0
T29	586	185	0	0
T30	548	147	0	0
T40	46119	45682	0	0
T41	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	6749474	0	0
T13	2154	462	0	0
T14	569	169	0	0
T15	27039	26581	0	0
T26	99226	98826	0	0
T27	502	102	0	0
T28	659	259	0	0
T29	586	186	0	0
T30	548	148	0	0
T40	46119	45688	0	0
T41	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	56	0	0
T13	2154	1	0	0
T14	569	0	0	0
T15	27039	0	0	0
T21	0	1	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T51	0	2	0	0
T52	0	1	0	0
T53	0	1	0	0
T55	0	2	0	0
T63	0	1	0	0
T188	0	2	0	0
T205	0	1	0	0
T219	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	52	0	0
T13	2154	1	0	0
T14	569	0	0	0
T15	27039	0	0	0
T21	0	1	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T51	0	2	0	0
T53	0	1	0	0
T55	0	2	0	0
T63	0	1	0	0
T188	0	2	0	0
T205	0	1	0	0
T206	0	3	0	0
T219	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	51	0	0
T13	2154	1	0	0
T14	569	0	0	0
T15	27039	0	0	0
T21	0	1	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T51	0	2	0	0
T53	0	1	0	0
T55	0	2	0	0
T63	0	1	0	0
T188	0	2	0	0
T205	0	1	0	0
T206	0	3	0	0
T219	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	51	0	0
T13	2154	1	0	0
T14	569	0	0	0
T15	27039	0	0	0
T21	0	1	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T51	0	2	0	0
T53	0	1	0	0
T55	0	2	0	0
T63	0	1	0	0
T188	0	2	0	0
T205	0	1	0	0
T206	0	3	0	0
T219	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	3319	0	0
T13	2154	40	0	0
T14	569	0	0	0
T15	27039	0	0	0
T21	0	41	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T51	0	68	0	0
T53	0	38	0	0
T55	0	142	0	0
T63	0	39	0	0
T188	0	110	0	0
T205	0	35	0	0
T206	0	243	0	0
T219	0	50	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	6296	0	0
T13	2154	5	0	0
T14	569	0	0	0
T15	27039	8	0	0
T16	0	29	0	0
T26	99226	0	0	0
T27	502	6	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	0	8	0	0
T32	0	30	0	0
T40	46119	30	0	0
T41	522	3	0	0
T66	0	9	0	0
T67	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7118843	0	0
T13	2154	554	0	0
T14	569	169	0	0
T15	27039	26581	0	0
T26	99226	98826	0	0
T27	502	102	0	0
T28	659	259	0	0
T29	586	186	0	0
T30	548	148	0	0
T40	46119	45688	0	0
T41	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	21	0	0
T21	33629	1	0	0
T22	481	0	0	0
T51	0	1	0	0
T55	0	1	0	0
T61	18429	0	0	0
T144	491	0	0	0
T152	0	1	0	0
T165	0	1	0	0
T171	424	0	0	0
T176	0	1	0	0
T187	0	1	0	0
T188	0	1	0	0
T189	491	0	0	0
T190	506	0	0	0
T191	448	0	0	0
T192	492	0	0	0
T193	2538	0	0	0
T209	0	1	0	0
T219	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T40,T41,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T40,T41,T13
1	0	Covered	T40,T41,T13
1	1	Covered	T40,T41,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T20,T22,T54

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T40,T41,T13	VC_COV_UNR
1	Covered	T20,T22,T54

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T20,T22,T54

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T20,T22
1	0	Covered	T40,T41,T13
1	1	Covered	T20,T22,T54

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T20,T22,T54
0	1	Covered	T52,T94
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T20,T22,T54
0	1	Covered	T45,T50,T51
1	0	Covered	T85

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T20,T22,T54
1	-	Covered	T45,T50,T51

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4
DetectSt	168	Covered	T4
IdleSt	163	Covered	T4
StableSt	191	Covered	T4

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4
DebounceSt->IdleSt	163	Covered	T4
DetectSt->IdleSt	186	Covered	T4
DetectSt->StableSt	191	Covered	T4
IdleSt->DebounceSt	148	Covered	T4
StableSt->IdleSt	206	Covered	T4

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T20,T22,T54
0	1	Covered	T20,T22,T54
0	0	Excluded	T40,T41,T13	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T22,T54
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T20,T22,T54
IdleSt	0	-	-	-	-	-	-	Covered	T40,T41,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T84
DebounceSt	-	0	1	1	-	-	-	Covered	T20,T22,T54
DebounceSt	-	0	1	0	-	-	-	Covered	T51,T52,T187
DebounceSt	-	0	0	-	-	-	-	Covered	T20,T22,T54
DetectSt	-	-	-	-	1	-	-	Covered	T52,T94
DetectSt	-	-	-	-	0	1	-	Covered	T20,T22,T54
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T45,T50,T51
StableSt	-	-	-	-	-	-	0	Covered	T20,T22,T54
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7780736	149	0	0
CntIncr_A	7780736	128680	0	0
CntNoWrap_A	7780736	7116376	0	0
DetectStDropOut_A	7780736	3	0	0
DetectedOut_A	7780736	5716	0	0
DetectedPulseOut_A	7780736	68	0	0
DisabledIdleSt_A	7780736	6588453	0	0
DisabledNoDetection_A	7780736	6590710	0	0
EnterDebounceSt_A	7780736	79	0	0
EnterDetectSt_A	7780736	71	0	0
EnterStableSt_A	7780736	68	0	0
PulseIsPulse_A	7780736	68	0	0
StayInStableSt	7780736	5619	0	0
gen_high_level_sva.HighLevelEvent_A	7780736	7118843	0	0
gen_not_sticky_sva.StableStDropOut_A	7780736	38	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	149	0	0
T20	670	2	0	0
T21	33629	0	0	0
T22	0	2	0	0
T45	0	4	0	0
T50	0	2	0	0
T51	0	5	0	0
T54	0	2	0	0
T56	0	2	0	0
T58	0	2	0	0
T79	780	0	0	0
T80	496	0	0	0
T121	0	2	0	0
T144	491	0	0	0
T186	0	2	0	0
T189	491	0	0	0
T190	506	0	0	0
T191	448	0	0	0
T192	492	0	0	0
T193	2538	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	128680	0	0
T20	670	81	0	0
T21	33629	0	0	0
T22	0	17	0	0
T45	0	86	0	0
T50	0	74	0	0
T51	0	213	0	0
T54	0	37	0	0
T56	0	58	0	0
T58	0	62180	0	0
T79	780	0	0	0
T80	496	0	0	0
T121	0	19	0	0
T144	491	0	0	0
T186	0	94	0	0
T189	491	0	0	0
T190	506	0	0	0
T191	448	0	0	0
T192	492	0	0	0
T193	2538	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7116376	0	0
T13	2154	551	0	0
T14	569	168	0	0
T15	27039	26570	0	0
T26	99226	98825	0	0
T27	502	101	0	0
T28	659	258	0	0
T29	586	185	0	0
T30	548	147	0	0
T40	46119	45682	0	0
T41	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	3	0	0
T52	791	1	0	0
T94	0	2	0	0
T240	492	0	0	0
T247	724	0	0	0
T248	10540	0	0	0
T249	422	0	0	0
T250	15052	0	0	0
T263	23602	0	0	0
T264	404	0	0	0
T265	506	0	0	0
T266	555	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	5716	0	0
T20	670	38	0	0
T21	33629	0	0	0
T22	0	54	0	0
T45	0	91	0	0
T50	0	41	0	0
T51	0	171	0	0
T54	0	96	0	0
T56	0	127	0	0
T58	0	44	0	0
T79	780	0	0	0
T80	496	0	0	0
T121	0	69	0	0
T144	491	0	0	0
T186	0	170	0	0
T189	491	0	0	0
T190	506	0	0	0
T191	448	0	0	0
T192	492	0	0	0
T193	2538	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	68	0	0
T20	670	1	0	0
T21	33629	0	0	0
T22	0	1	0	0
T45	0	2	0	0
T50	0	1	0	0
T51	0	2	0	0
T54	0	1	0	0
T56	0	1	0	0
T58	0	1	0	0
T79	780	0	0	0
T80	496	0	0	0
T121	0	1	0	0
T144	491	0	0	0
T186	0	1	0	0
T189	491	0	0	0
T190	506	0	0	0
T191	448	0	0	0
T192	492	0	0	0
T193	2538	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	6588453	0	0
T13	2154	460	0	0
T14	569	168	0	0
T15	27039	26570	0	0
T26	99226	98825	0	0
T27	502	101	0	0
T28	659	258	0	0
T29	586	185	0	0
T30	548	147	0	0
T40	46119	45682	0	0
T41	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	6590710	0	0
T13	2154	462	0	0
T14	569	169	0	0
T15	27039	26581	0	0
T26	99226	98826	0	0
T27	502	102	0	0
T28	659	259	0	0
T29	586	186	0	0
T30	548	148	0	0
T40	46119	45688	0	0
T41	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	79	0	0
T20	670	1	0	0
T21	33629	0	0	0
T22	0	1	0	0
T45	0	2	0	0
T50	0	1	0	0
T51	0	3	0	0
T54	0	1	0	0
T56	0	1	0	0
T58	0	1	0	0
T79	780	0	0	0
T80	496	0	0	0
T121	0	1	0	0
T144	491	0	0	0
T186	0	1	0	0
T189	491	0	0	0
T190	506	0	0	0
T191	448	0	0	0
T192	492	0	0	0
T193	2538	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	71	0	0
T20	670	1	0	0
T21	33629	0	0	0
T22	0	1	0	0
T45	0	2	0	0
T50	0	1	0	0
T51	0	2	0	0
T54	0	1	0	0
T56	0	1	0	0
T58	0	1	0	0
T79	780	0	0	0
T80	496	0	0	0
T121	0	1	0	0
T144	491	0	0	0
T186	0	1	0	0
T189	491	0	0	0
T190	506	0	0	0
T191	448	0	0	0
T192	492	0	0	0
T193	2538	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	68	0	0
T20	670	1	0	0
T21	33629	0	0	0
T22	0	1	0	0
T45	0	2	0	0
T50	0	1	0	0
T51	0	2	0	0
T54	0	1	0	0
T56	0	1	0	0
T58	0	1	0	0
T79	780	0	0	0
T80	496	0	0	0
T121	0	1	0	0
T144	491	0	0	0
T186	0	1	0	0
T189	491	0	0	0
T190	506	0	0	0
T191	448	0	0	0
T192	492	0	0	0
T193	2538	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	68	0	0
T20	670	1	0	0
T21	33629	0	0	0
T22	0	1	0	0
T45	0	2	0	0
T50	0	1	0	0
T51	0	2	0	0
T54	0	1	0	0
T56	0	1	0	0
T58	0	1	0	0
T79	780	0	0	0
T80	496	0	0	0
T121	0	1	0	0
T144	491	0	0	0
T186	0	1	0	0
T189	491	0	0	0
T190	506	0	0	0
T191	448	0	0	0
T192	492	0	0	0
T193	2538	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	5619	0	0
T20	670	36	0	0
T21	33629	0	0	0
T22	0	52	0	0
T45	0	88	0	0
T50	0	40	0	0
T51	0	168	0	0
T54	0	94	0	0
T56	0	125	0	0
T58	0	42	0	0
T79	780	0	0	0
T80	496	0	0	0
T121	0	67	0	0
T144	491	0	0	0
T186	0	168	0	0
T189	491	0	0	0
T190	506	0	0	0
T191	448	0	0	0
T192	492	0	0	0
T193	2538	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7118843	0	0
T13	2154	554	0	0
T14	569	169	0	0
T15	27039	26581	0	0
T26	99226	98826	0	0
T27	502	102	0	0
T28	659	259	0	0
T29	586	186	0	0
T30	548	148	0	0
T40	46119	45688	0	0
T41	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	38	0	0
T44	1139	0	0	0
T45	102206	1	0	0
T46	18603	0	0	0
T50	0	1	0	0
T51	0	1	0	0
T101	718	0	0	0
T132	0	1	0	0
T172	439	0	0	0
T173	420	0	0	0
T174	411	0	0	0
T175	424	0	0	0
T203	0	1	0	0
T205	0	1	0	0
T206	0	1	0	0
T207	495	0	0	0
T208	0	2	0	0
T209	0	1	0	0
T219	0	1	0	0
T252	1333	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T40,T41,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T40,T41,T13
1	0	Covered	T40,T41,T13
1	1	Covered	T40,T41,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T45,T50,T51

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T40,T41,T13	VC_COV_UNR
1	Covered	T45,T50,T51

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T50,T51,T52

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T54
1	0	Covered	T40,T41,T13
1	1	Covered	T45,T50,T51

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T50,T51,T52
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T50,T51,T52
0	1	Covered	T51,T52,T219
1	0	Covered	T85

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T50,T51,T52
1	-	Covered	T51,T52,T219

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4
DetectSt	168	Covered	T4
IdleSt	163	Covered	T4
StableSt	191	Covered	T4

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4
DebounceSt->IdleSt	163	Covered	T4
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T4
IdleSt->DebounceSt	148	Covered	T4
StableSt->IdleSt	206	Covered	T4

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T45,T50,T51
0	1	Covered	T45,T50,T51
0	0	Excluded	T40,T41,T13	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T50,T51,T52
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T45,T50,T51
IdleSt	0	-	-	-	-	-	-	Covered	T40,T41,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T84
DebounceSt	-	0	1	1	-	-	-	Covered	T50,T51,T52
DebounceSt	-	0	1	0	-	-	-	Covered	T45,T177
DebounceSt	-	0	0	-	-	-	-	Covered	T45,T50,T51
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T50,T51,T52
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T51,T52,T219
StableSt	-	-	-	-	-	-	0	Covered	T50,T51,T52
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7780736	101	0	0
CntIncr_A	7780736	94486	0	0
CntNoWrap_A	7780736	7116424	0	0
DetectStDropOut_A	7780736	0	0	0
DetectedOut_A	7780736	32750	0	0
DetectedPulseOut_A	7780736	49	0	0
DisabledIdleSt_A	7780736	6755010	0	0
DisabledNoDetection_A	7780736	6757275	0	0
EnterDebounceSt_A	7780736	52	0	0
EnterDetectSt_A	7780736	49	0	0
EnterStableSt_A	7780736	49	0	0
PulseIsPulse_A	7780736	49	0	0
StayInStableSt	7780736	32675	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7780736	6979	0	0
gen_low_level_sva.LowLevelEvent_A	7780736	7118843	0	0
gen_not_sticky_sva.StableStDropOut_A	7780736	22	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	101	0	0
T44	1139	0	0	0
T45	102206	1	0	0
T46	18603	0	0	0
T50	0	2	0	0
T51	0	4	0	0
T52	0	4	0	0
T84	0	1	0	0
T101	718	0	0	0
T172	439	0	0	0
T173	420	0	0	0
T174	411	0	0	0
T175	424	0	0	0
T188	0	2	0	0
T203	0	2	0	0
T205	0	2	0	0
T206	0	2	0	0
T207	495	0	0	0
T219	0	2	0	0
T252	1333	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	94486	0	0
T44	1139	0	0	0
T45	102206	43	0	0
T46	18603	0	0	0
T50	0	74	0	0
T51	0	142	0	0
T52	0	156	0	0
T84	0	15	0	0
T101	718	0	0	0
T172	439	0	0	0
T173	420	0	0	0
T174	411	0	0	0
T175	424	0	0	0
T188	0	58	0	0
T203	0	22	0	0
T205	0	50	0	0
T206	0	32	0	0
T207	495	0	0	0
T219	0	60	0	0
T252	1333	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7116424	0	0
T13	2154	551	0	0
T14	569	168	0	0
T15	27039	26570	0	0
T26	99226	98825	0	0
T27	502	101	0	0
T28	659	258	0	0
T29	586	185	0	0
T30	548	147	0	0
T40	46119	45682	0	0
T41	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	32750	0	0
T50	643	43	0	0
T51	0	84	0	0
T52	0	85	0	0
T56	25287	0	0	0
T132	0	96	0	0
T186	2665	0	0	0
T188	0	45	0	0
T203	0	3	0	0
T204	0	106	0	0
T205	0	38	0	0
T206	0	78	0	0
T219	0	119	0	0
T267	403	0	0	0
T268	8424	0	0	0
T269	403	0	0	0
T270	31350	0	0	0
T271	404	0	0	0
T272	508	0	0	0
T273	503	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	49	0	0
T50	643	1	0	0
T51	0	2	0	0
T52	0	2	0	0
T56	25287	0	0	0
T132	0	1	0	0
T186	2665	0	0	0
T188	0	1	0	0
T203	0	1	0	0
T204	0	1	0	0
T205	0	1	0	0
T206	0	1	0	0
T219	0	1	0	0
T267	403	0	0	0
T268	8424	0	0	0
T269	403	0	0	0
T270	31350	0	0	0
T271	404	0	0	0
T272	508	0	0	0
T273	503	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	6755010	0	0
T13	2154	551	0	0
T14	569	168	0	0
T15	27039	26570	0	0
T26	99226	98825	0	0
T27	502	101	0	0
T28	659	258	0	0
T29	586	185	0	0
T30	548	147	0	0
T40	46119	45682	0	0
T41	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	6757275	0	0
T13	2154	554	0	0
T14	569	169	0	0
T15	27039	26581	0	0
T26	99226	98826	0	0
T27	502	102	0	0
T28	659	259	0	0
T29	586	186	0	0
T30	548	148	0	0
T40	46119	45688	0	0
T41	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	52	0	0
T44	1139	0	0	0
T45	102206	1	0	0
T46	18603	0	0	0
T50	0	1	0	0
T51	0	2	0	0
T52	0	2	0	0
T84	0	1	0	0
T101	718	0	0	0
T172	439	0	0	0
T173	420	0	0	0
T174	411	0	0	0
T175	424	0	0	0
T188	0	1	0	0
T203	0	1	0	0
T205	0	1	0	0
T206	0	1	0	0
T207	495	0	0	0
T219	0	1	0	0
T252	1333	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	49	0	0
T50	643	1	0	0
T51	0	2	0	0
T52	0	2	0	0
T56	25287	0	0	0
T132	0	1	0	0
T186	2665	0	0	0
T188	0	1	0	0
T203	0	1	0	0
T204	0	1	0	0
T205	0	1	0	0
T206	0	1	0	0
T219	0	1	0	0
T267	403	0	0	0
T268	8424	0	0	0
T269	403	0	0	0
T270	31350	0	0	0
T271	404	0	0	0
T272	508	0	0	0
T273	503	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	49	0	0
T50	643	1	0	0
T51	0	2	0	0
T52	0	2	0	0
T56	25287	0	0	0
T132	0	1	0	0
T186	2665	0	0	0
T188	0	1	0	0
T203	0	1	0	0
T204	0	1	0	0
T205	0	1	0	0
T206	0	1	0	0
T219	0	1	0	0
T267	403	0	0	0
T268	8424	0	0	0
T269	403	0	0	0
T270	31350	0	0	0
T271	404	0	0	0
T272	508	0	0	0
T273	503	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	49	0	0
T50	643	1	0	0
T51	0	2	0	0
T52	0	2	0	0
T56	25287	0	0	0
T132	0	1	0	0
T186	2665	0	0	0
T188	0	1	0	0
T203	0	1	0	0
T204	0	1	0	0
T205	0	1	0	0
T206	0	1	0	0
T219	0	1	0	0
T267	403	0	0	0
T268	8424	0	0	0
T269	403	0	0	0
T270	31350	0	0	0
T271	404	0	0	0
T272	508	0	0	0
T273	503	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	32675	0	0
T50	643	41	0	0
T51	0	82	0	0
T52	0	82	0	0
T56	25287	0	0	0
T132	0	95	0	0
T186	2665	0	0	0
T188	0	43	0	0
T203	0	2	0	0
T204	0	105	0	0
T205	0	36	0	0
T206	0	76	0	0
T219	0	118	0	0
T267	403	0	0	0
T268	8424	0	0	0
T269	403	0	0	0
T270	31350	0	0	0
T271	404	0	0	0
T272	508	0	0	0
T273	503	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	6979	0	0
T13	2154	5	0	0
T14	569	0	0	0
T15	27039	11	0	0
T16	0	31	0	0
T26	99226	0	0	0
T27	502	4	0	0
T28	659	0	0	0
T29	586	3	0	0
T30	548	0	0	0
T31	0	6	0	0
T32	0	27	0	0
T40	46119	28	0	0
T41	522	4	0	0
T66	0	7	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7118843	0	0
T13	2154	554	0	0
T14	569	169	0	0
T15	27039	26581	0	0
T26	99226	98826	0	0
T27	502	102	0	0
T28	659	259	0	0
T29	586	186	0	0
T30	548	148	0	0
T40	46119	45688	0	0
T41	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	22	0	0
T51	5443	2	0	0
T52	791	1	0	0
T132	0	1	0	0
T152	0	1	0	0
T176	0	2	0	0
T203	0	1	0	0
T204	0	1	0	0
T210	0	1	0	0
T219	0	1	0	0
T225	0	1	0	0
T238	494	0	0	0
T240	492	0	0	0
T245	406	0	0	0
T246	404	0	0	0
T247	724	0	0	0
T248	10540	0	0	0
T249	422	0	0	0
T250	15052	0	0	0