Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T40,T32,T16
1	Covered	T40,T41,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T40,T32,T16

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T40,T32,T16

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T40,T32,T16

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T40,T32,T16
1	0	Covered	T40,T16,T19
1	1	Covered	T40,T32,T16

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T40,T32,T16
0	1	Covered	T16,T91,T61
1	0	Covered	T16,T61,T49

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T40,T32,T19
0	1	Covered	T40,T32,T19
1	0	Covered	T64

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T40,T32,T19
1	-	Covered	T40,T32,T19

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4
DetectSt	168	Covered	T4
IdleSt	163	Covered	T4
StableSt	191	Covered	T4

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4
DebounceSt->IdleSt	163	Covered	T4
DetectSt->IdleSt	186	Covered	T4
DetectSt->StableSt	191	Covered	T4
IdleSt->DebounceSt	148	Covered	T4
StableSt->IdleSt	206	Covered	T4

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T40,T32,T16
0	1	Covered	T40,T32,T16
0	0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T40,T32,T16
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T40,T32,T16
IdleSt	0	-	-	-	-	-	-	Covered	T40,T32,T16
DebounceSt	-	1	-	-	-	-	-	Covered	T84,T85
DebounceSt	-	0	1	1	-	-	-	Covered	T40,T32,T16
DebounceSt	-	0	1	0	-	-	-	Covered	T84,T274,T85
DebounceSt	-	0	0	-	-	-	-	Covered	T40,T32,T16
DetectSt	-	-	-	-	1	-	-	Covered	T16,T91,T61
DetectSt	-	-	-	-	0	1	-	Covered	T40,T32,T19
DetectSt	-	-	-	-	0	0	-	Covered	T40,T32,T16
StableSt	-	-	-	-	-	-	1	Covered	T40,T32,T19
StableSt	-	-	-	-	-	-	0	Covered	T40,T32,T19
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7780736	3158	0	0
CntIncr_A	7780736	111852	0	0
CntNoWrap_A	7780736	7113367	0	0
DetectStDropOut_A	7780736	487	0	0
DetectedOut_A	7780736	84857	0	0
DetectedPulseOut_A	7780736	911	0	0
DisabledIdleSt_A	7780736	6621916	0	0
DisabledNoDetection_A	7780736	6624025	0	0
EnterDebounceSt_A	7780736	1585	0	0
EnterDetectSt_A	7780736	1573	0	0
EnterStableSt_A	7780736	911	0	0
PulseIsPulse_A	7780736	911	0	0
StayInStableSt	7780736	83831	0	0
gen_high_event_sva.HighLevelEvent_A	7780736	7118843	0	0
gen_high_level_sva.HighLevelEvent_A	7780736	7118843	0	0
gen_not_sticky_sva.StableStDropOut_A	7780736	795	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	3158	0	0
T13	2154	0	0	0
T14	569	0	0	0
T15	27039	0	0	0
T16	0	44	0	0
T19	0	56	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T32	0	30	0	0
T40	46119	48	0	0
T41	522	0	0	0
T46	0	30	0	0
T49	0	24	0	0
T61	0	34	0	0
T91	0	14	0	0
T102	0	56	0	0
T105	0	44	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	111852	0	0
T13	2154	0	0	0
T14	569	0	0	0
T15	27039	0	0	0
T16	0	1263	0	0
T19	0	3808	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T32	0	1140	0	0
T40	46119	7104	0	0
T41	522	0	0	0
T46	0	855	0	0
T49	0	612	0	0
T61	0	811	0	0
T91	0	415	0	0
T102	0	2044	0	0
T105	0	1035	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7113367	0	0
T13	2154	551	0	0
T14	569	168	0	0
T15	27039	26570	0	0
T26	99226	98825	0	0
T27	502	101	0	0
T28	659	258	0	0
T29	586	185	0	0
T30	548	147	0	0
T40	46119	45634	0	0
T41	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	487	0	0
T16	23425	11	0	0
T22	481	0	0	0
T49	0	7	0	0
T61	18429	4	0	0
T67	422	0	0	0
T68	631	0	0	0
T69	510	0	0	0
T90	4870	0	0	0
T91	5616	7	0	0
T104	502	0	0	0
T105	0	22	0	0
T106	0	12	0	0
T107	0	6	0	0
T108	0	12	0	0
T109	0	5	0	0
T110	0	13	0	0
T171	424	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	84857	0	0
T13	2154	0	0	0
T14	569	0	0	0
T15	27039	0	0	0
T19	0	5482	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T32	0	1526	0	0
T40	46119	11115	0	0
T41	522	0	0	0
T46	0	859	0	0
T64	0	137	0	0
T102	0	1916	0	0
T135	0	1682	0	0
T136	0	476	0	0
T275	0	213	0	0
T276	0	1517	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	911	0	0
T13	2154	0	0	0
T14	569	0	0	0
T15	27039	0	0	0
T19	0	28	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T32	0	15	0	0
T40	46119	24	0	0
T41	522	0	0	0
T46	0	15	0	0
T64	0	13	0	0
T102	0	28	0	0
T135	0	28	0	0
T136	0	7	0	0
T275	0	12	0	0
T276	0	14	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	6621916	0	0
T13	2154	551	0	0
T14	569	168	0	0
T15	27039	26570	0	0
T26	99226	98825	0	0
T27	502	101	0	0
T28	659	258	0	0
T29	586	185	0	0
T30	548	147	0	0
T40	46119	12873	0	0
T41	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	6624025	0	0
T13	2154	554	0	0
T14	569	169	0	0
T15	27039	26581	0	0
T26	99226	98826	0	0
T27	502	102	0	0
T28	659	259	0	0
T29	586	186	0	0
T30	548	148	0	0
T40	46119	12873	0	0
T41	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	1585	0	0
T13	2154	0	0	0
T14	569	0	0	0
T15	27039	0	0	0
T16	0	22	0	0
T19	0	28	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T32	0	15	0	0
T40	46119	24	0	0
T41	522	0	0	0
T46	0	15	0	0
T49	0	12	0	0
T61	0	17	0	0
T91	0	7	0	0
T102	0	28	0	0
T105	0	22	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	1573	0	0
T13	2154	0	0	0
T14	569	0	0	0
T15	27039	0	0	0
T16	0	22	0	0
T19	0	28	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T32	0	15	0	0
T40	46119	24	0	0
T41	522	0	0	0
T46	0	15	0	0
T49	0	12	0	0
T61	0	17	0	0
T91	0	7	0	0
T102	0	28	0	0
T105	0	22	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	911	0	0
T13	2154	0	0	0
T14	569	0	0	0
T15	27039	0	0	0
T19	0	28	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T32	0	15	0	0
T40	46119	24	0	0
T41	522	0	0	0
T46	0	15	0	0
T64	0	13	0	0
T102	0	28	0	0
T135	0	28	0	0
T136	0	7	0	0
T275	0	12	0	0
T276	0	14	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	911	0	0
T13	2154	0	0	0
T14	569	0	0	0
T15	27039	0	0	0
T19	0	28	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T32	0	15	0	0
T40	46119	24	0	0
T41	522	0	0	0
T46	0	15	0	0
T64	0	13	0	0
T102	0	28	0	0
T135	0	28	0	0
T136	0	7	0	0
T275	0	12	0	0
T276	0	14	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	83831	0	0
T13	2154	0	0	0
T14	569	0	0	0
T15	27039	0	0	0
T19	0	5451	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T32	0	1511	0	0
T40	46119	11086	0	0
T41	522	0	0	0
T46	0	841	0	0
T64	0	124	0	0
T102	0	1883	0	0
T135	0	1653	0	0
T136	0	469	0	0
T275	0	201	0	0
T276	0	1503	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7118843	0	0
T13	2154	554	0	0
T14	569	169	0	0
T15	27039	26581	0	0
T26	99226	98826	0	0
T27	502	102	0	0
T28	659	259	0	0
T29	586	186	0	0
T30	548	148	0	0
T40	46119	45688	0	0
T41	522	122	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7118843	0	0
T13	2154	554	0	0
T14	569	169	0	0
T15	27039	26581	0	0
T26	99226	98826	0	0
T27	502	102	0	0
T28	659	259	0	0
T29	586	186	0	0
T30	548	148	0	0
T40	46119	45688	0	0
T41	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	795	0	0
T13	2154	0	0	0
T14	569	0	0	0
T15	27039	0	0	0
T19	0	25	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T32	0	15	0	0
T40	46119	19	0	0
T41	522	0	0	0
T46	0	12	0	0
T64	0	12	0	0
T102	0	23	0	0
T135	0	27	0	0
T136	0	7	0	0
T275	0	12	0	0
T276	0	14	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T40,T15,T31
1	Covered	T40,T41,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T40,T15,T31
1	0	Covered	T40,T41,T13
1	1	Covered	T40,T41,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T40,T15,T31

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T40,T41,T13	VC_COV_UNR
1	Covered	T40,T15,T31

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T40,T15,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T40,T15,T31
1	0	Covered	T40,T13,T15
1	1	Covered	T40,T15,T31

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T40,T15,T32
0	1	Covered	T111,T112,T113
1	0	Covered	T84,T85

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T40,T15,T32
0	1	Covered	T15,T32,T19
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T40,T15,T32
1	-	Covered	T15,T32,T19

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4
DetectSt	168	Covered	T4
IdleSt	163	Covered	T4
StableSt	191	Covered	T4

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4
DebounceSt->IdleSt	163	Covered	T4
DetectSt->IdleSt	186	Covered	T4
DetectSt->StableSt	191	Covered	T4
IdleSt->DebounceSt	148	Covered	T4
StableSt->IdleSt	206	Covered	T4

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T40,T15,T31
0	1	Covered	T40,T15,T31
0	0	Excluded	T40,T41,T13	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T40,T15,T32
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T40,T15,T31
IdleSt	0	-	-	-	-	-	-	Covered	T40,T41,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T84,T85
DebounceSt	-	0	1	1	-	-	-	Covered	T40,T15,T32
DebounceSt	-	0	1	0	-	-	-	Covered	T15,T31,T19
DebounceSt	-	0	0	-	-	-	-	Covered	T40,T15,T31
DetectSt	-	-	-	-	1	-	-	Covered	T111,T112,T84
DetectSt	-	-	-	-	0	1	-	Covered	T40,T15,T32
DetectSt	-	-	-	-	0	0	-	Covered	T40,T15,T32
StableSt	-	-	-	-	-	-	1	Covered	T15,T32,T19
StableSt	-	-	-	-	-	-	0	Covered	T40,T15,T32
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7780736	907	0	0
CntIncr_A	7780736	46886	0	0
CntNoWrap_A	7780736	7115618	0	0
DetectStDropOut_A	7780736	40	0	0
DetectedOut_A	7780736	14365	0	0
DetectedPulseOut_A	7780736	368	0	0
DisabledIdleSt_A	7780736	6762791	0	0
DisabledNoDetection_A	7780736	6764424	0	0
EnterDebounceSt_A	7780736	498	0	0
EnterDetectSt_A	7780736	413	0	0
EnterStableSt_A	7780736	368	0	0
PulseIsPulse_A	7780736	368	0	0
StayInStableSt	7780736	13969	0	0
gen_high_level_sva.HighLevelEvent_A	7780736	7118843	0	0
gen_not_sticky_sva.StableStDropOut_A	7780736	339	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	907	0	0
T13	2154	0	0	0
T14	569	0	0	0
T15	27039	10	0	0
T19	0	7	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	0	1	0	0
T32	0	6	0	0
T40	46119	10	0	0
T41	522	0	0	0
T45	0	9	0	0
T46	0	5	0	0
T48	0	30	0	0
T63	0	3	0	0
T102	0	10	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	46886	0	0
T13	2154	0	0	0
T14	569	0	0	0
T15	27039	600	0	0
T19	0	587	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	0	20	0	0
T32	0	276	0	0
T40	46119	1590	0	0
T41	522	0	0	0
T45	0	406	0	0
T46	0	193	0	0
T48	0	2230	0	0
T63	0	112	0	0
T102	0	370	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7115618	0	0
T13	2154	551	0	0
T14	569	168	0	0
T15	27039	26560	0	0
T26	99226	98825	0	0
T27	502	101	0	0
T28	659	258	0	0
T29	586	185	0	0
T30	548	147	0	0
T40	46119	45672	0	0
T41	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	40	0	0
T60	603	0	0	0
T85	0	1	0	0
T89	0	2	0	0
T111	24266	3	0	0
T112	0	10	0	0
T113	0	1	0	0
T114	0	3	0	0
T115	0	1	0	0
T116	0	1	0	0
T117	0	6	0	0
T118	0	2	0	0
T119	18790	0	0	0
T120	5119	0	0	0
T121	497	0	0	0
T122	422	0	0	0
T123	3117	0	0	0
T124	493	0	0	0
T125	15469	0	0	0
T126	988	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	14365	0	0
T13	2154	0	0	0
T14	569	0	0	0
T15	27039	210	0	0
T19	0	133	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T32	0	305	0	0
T40	46119	269	0	0
T41	522	0	0	0
T45	0	248	0	0
T46	0	85	0	0
T48	0	530	0	0
T63	0	3	0	0
T65	0	119	0	0
T102	0	198	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	368	0	0
T13	2154	0	0	0
T14	569	0	0	0
T15	27039	4	0	0
T19	0	3	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T32	0	3	0	0
T40	46119	5	0	0
T41	522	0	0	0
T45	0	4	0	0
T46	0	2	0	0
T48	0	15	0	0
T63	0	1	0	0
T65	0	4	0	0
T102	0	5	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	6762791	0	0
T13	2154	551	0	0
T14	569	168	0	0
T15	27039	22159	0	0
T26	99226	98825	0	0
T27	502	101	0	0
T28	659	258	0	0
T29	586	185	0	0
T30	548	147	0	0
T40	46119	34572	0	0
T41	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	6764424	0	0
T13	2154	554	0	0
T14	569	169	0	0
T15	27039	22159	0	0
T26	99226	98826	0	0
T27	502	102	0	0
T28	659	259	0	0
T29	586	186	0	0
T30	548	148	0	0
T40	46119	34573	0	0
T41	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	498	0	0
T13	2154	0	0	0
T14	569	0	0	0
T15	27039	6	0	0
T19	0	4	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	0	1	0	0
T32	0	3	0	0
T40	46119	5	0	0
T41	522	0	0	0
T45	0	5	0	0
T46	0	3	0	0
T48	0	15	0	0
T63	0	3	0	0
T102	0	5	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	413	0	0
T13	2154	0	0	0
T14	569	0	0	0
T15	27039	4	0	0
T19	0	3	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T32	0	3	0	0
T40	46119	5	0	0
T41	522	0	0	0
T45	0	4	0	0
T46	0	2	0	0
T48	0	15	0	0
T63	0	1	0	0
T65	0	4	0	0
T102	0	5	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	368	0	0
T13	2154	0	0	0
T14	569	0	0	0
T15	27039	4	0	0
T19	0	3	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T32	0	3	0	0
T40	46119	5	0	0
T41	522	0	0	0
T45	0	4	0	0
T46	0	2	0	0
T48	0	15	0	0
T63	0	1	0	0
T65	0	4	0	0
T102	0	5	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	368	0	0
T13	2154	0	0	0
T14	569	0	0	0
T15	27039	4	0	0
T19	0	3	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T32	0	3	0	0
T40	46119	5	0	0
T41	522	0	0	0
T45	0	4	0	0
T46	0	2	0	0
T48	0	15	0	0
T63	0	1	0	0
T65	0	4	0	0
T102	0	5	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	13969	0	0
T13	2154	0	0	0
T14	569	0	0	0
T15	27039	206	0	0
T19	0	129	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T32	0	302	0	0
T40	46119	259	0	0
T41	522	0	0	0
T45	0	244	0	0
T46	0	83	0	0
T48	0	515	0	0
T63	0	2	0	0
T65	0	115	0	0
T102	0	188	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7118843	0	0
T13	2154	554	0	0
T14	569	169	0	0
T15	27039	26581	0	0
T26	99226	98826	0	0
T27	502	102	0	0
T28	659	259	0	0
T29	586	186	0	0
T30	548	148	0	0
T40	46119	45688	0	0
T41	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	339	0	0
T15	27039	4	0	0
T16	23425	0	0	0
T19	0	2	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	3	0	0
T45	0	4	0	0
T46	0	2	0	0
T48	0	15	0	0
T63	0	1	0	0
T65	0	4	0	0
T66	494	0	0	0
T67	422	0	0	0
T68	631	0	0	0
T69	510	0	0	0
T83	0	4	0	0
T139	0	5	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T40,T32,T16
1	Covered	T40,T41,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T40,T32,T16

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T40,T32,T16

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T40,T32,T16

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T40,T32,T16
1	0	Covered	T40,T32,T16
1	1	Covered	T40,T32,T16

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T40,T32,T16
0	1	Covered	T32,T91,T49
1	0	Covered	T32,T49,T102

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T40,T16,T19
0	1	Covered	T40,T16,T19
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T40,T16,T19
1	-	Covered	T40,T16,T19

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4
DetectSt	168	Covered	T4
IdleSt	163	Covered	T4
StableSt	191	Covered	T4

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4
DebounceSt->IdleSt	163	Covered	T4
DetectSt->IdleSt	186	Covered	T4
DetectSt->StableSt	191	Covered	T4
IdleSt->DebounceSt	148	Covered	T4
StableSt->IdleSt	206	Covered	T4

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T40,T32,T16
0	1	Covered	T40,T32,T16
0	0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T40,T32,T16
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T40,T32,T16
IdleSt	0	-	-	-	-	-	-	Covered	T40,T32,T16
DebounceSt	-	1	-	-	-	-	-	Covered	T84,T85
DebounceSt	-	0	1	1	-	-	-	Covered	T40,T32,T16
DebounceSt	-	0	1	0	-	-	-	Covered	T84,T274,T85
DebounceSt	-	0	0	-	-	-	-	Covered	T40,T32,T16
DetectSt	-	-	-	-	1	-	-	Covered	T32,T91,T49
DetectSt	-	-	-	-	0	1	-	Covered	T40,T16,T19
DetectSt	-	-	-	-	0	0	-	Covered	T40,T32,T16
StableSt	-	-	-	-	-	-	1	Covered	T40,T16,T19
StableSt	-	-	-	-	-	-	0	Covered	T40,T16,T19
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7780736	2996	0	0
CntIncr_A	7780736	106691	0	0
CntNoWrap_A	7780736	7113529	0	0
DetectStDropOut_A	7780736	514	0	0
DetectedOut_A	7780736	62373	0	0
DetectedPulseOut_A	7780736	772	0	0
DisabledIdleSt_A	7780736	6641492	0	0
DisabledNoDetection_A	7780736	6643638	0	0
EnterDebounceSt_A	7780736	1504	0	0
EnterDetectSt_A	7780736	1492	0	0
EnterStableSt_A	7780736	772	0	0
PulseIsPulse_A	7780736	772	0	0
StayInStableSt	7780736	61522	0	0
gen_high_event_sva.HighLevelEvent_A	7780736	7118843	0	0
gen_high_level_sva.HighLevelEvent_A	7780736	7118843	0	0
gen_not_sticky_sva.StableStDropOut_A	7780736	693	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	2996	0	0
T13	2154	0	0	0
T14	569	0	0	0
T15	27039	0	0	0
T16	0	6	0	0
T19	0	30	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T32	0	12	0	0
T40	46119	26	0	0
T41	522	0	0	0
T46	0	36	0	0
T49	0	66	0	0
T61	0	16	0	0
T91	0	56	0	0
T102	0	50	0	0
T105	0	16	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	106691	0	0
T13	2154	0	0	0
T14	569	0	0	0
T15	27039	0	0	0
T16	0	135	0	0
T19	0	2130	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T32	0	461	0	0
T40	46119	5889	0	0
T41	522	0	0	0
T46	0	828	0	0
T49	0	1703	0	0
T61	0	216	0	0
T91	0	1685	0	0
T102	0	1921	0	0
T105	0	370	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7113529	0	0
T13	2154	551	0	0
T14	569	168	0	0
T15	27039	26570	0	0
T26	99226	98825	0	0
T27	502	101	0	0
T28	659	258	0	0
T29	586	185	0	0
T30	548	147	0	0
T40	46119	45656	0	0
T41	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	514	0	0
T16	23425	0	0	0
T32	7989	3	0	0
T49	27552	16	0	0
T64	0	20	0	0
T66	494	0	0	0
T67	422	0	0	0
T68	631	0	0	0
T69	510	0	0	0
T90	4870	0	0	0
T91	5616	28	0	0
T102	0	9	0	0
T104	502	0	0	0
T105	0	8	0	0
T106	0	8	0	0
T108	0	13	0	0
T109	0	16	0	0
T277	0	14	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	62373	0	0
T13	2154	0	0	0
T14	569	0	0	0
T15	27039	0	0	0
T16	0	178	0	0
T19	0	2475	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T40	46119	1335	0	0
T41	522	0	0	0
T46	0	1736	0	0
T61	0	177	0	0
T110	0	2114	0	0
T135	0	212	0	0
T136	0	3526	0	0
T275	0	2055	0	0
T276	0	242	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	772	0	0
T13	2154	0	0	0
T14	569	0	0	0
T15	27039	0	0	0
T16	0	3	0	0
T19	0	15	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T40	46119	13	0	0
T41	522	0	0	0
T46	0	18	0	0
T61	0	8	0	0
T110	0	23	0	0
T135	0	7	0	0
T136	0	26	0	0
T275	0	24	0	0
T276	0	9	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	6641492	0	0
T13	2154	551	0	0
T14	569	168	0	0
T15	27039	26570	0	0
T26	99226	98825	0	0
T27	502	101	0	0
T28	659	258	0	0
T29	586	185	0	0
T30	548	147	0	0
T40	46119	17762	0	0
T41	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	6643638	0	0
T13	2154	554	0	0
T14	569	169	0	0
T15	27039	26581	0	0
T26	99226	98826	0	0
T27	502	102	0	0
T28	659	259	0	0
T29	586	186	0	0
T30	548	148	0	0
T40	46119	17767	0	0
T41	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	1504	0	0
T13	2154	0	0	0
T14	569	0	0	0
T15	27039	0	0	0
T16	0	3	0	0
T19	0	15	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T32	0	6	0	0
T40	46119	13	0	0
T41	522	0	0	0
T46	0	18	0	0
T49	0	33	0	0
T61	0	8	0	0
T91	0	28	0	0
T102	0	25	0	0
T105	0	8	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	1492	0	0
T13	2154	0	0	0
T14	569	0	0	0
T15	27039	0	0	0
T16	0	3	0	0
T19	0	15	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T32	0	6	0	0
T40	46119	13	0	0
T41	522	0	0	0
T46	0	18	0	0
T49	0	33	0	0
T61	0	8	0	0
T91	0	28	0	0
T102	0	25	0	0
T105	0	8	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	772	0	0
T13	2154	0	0	0
T14	569	0	0	0
T15	27039	0	0	0
T16	0	3	0	0
T19	0	15	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T40	46119	13	0	0
T41	522	0	0	0
T46	0	18	0	0
T61	0	8	0	0
T110	0	23	0	0
T135	0	7	0	0
T136	0	26	0	0
T275	0	24	0	0
T276	0	9	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	772	0	0
T13	2154	0	0	0
T14	569	0	0	0
T15	27039	0	0	0
T16	0	3	0	0
T19	0	15	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T40	46119	13	0	0
T41	522	0	0	0
T46	0	18	0	0
T61	0	8	0	0
T110	0	23	0	0
T135	0	7	0	0
T136	0	26	0	0
T275	0	24	0	0
T276	0	9	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	61522	0	0
T13	2154	0	0	0
T14	569	0	0	0
T15	27039	0	0	0
T16	0	175	0	0
T19	0	2458	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T40	46119	1322	0	0
T41	522	0	0	0
T46	0	1715	0	0
T61	0	169	0	0
T110	0	2089	0	0
T135	0	205	0	0
T136	0	3497	0	0
T275	0	2029	0	0
T276	0	233	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7118843	0	0
T13	2154	554	0	0
T14	569	169	0	0
T15	27039	26581	0	0
T26	99226	98826	0	0
T27	502	102	0	0
T28	659	259	0	0
T29	586	186	0	0
T30	548	148	0	0
T40	46119	45688	0	0
T41	522	122	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7118843	0	0
T13	2154	554	0	0
T14	569	169	0	0
T15	27039	26581	0	0
T26	99226	98826	0	0
T27	502	102	0	0
T28	659	259	0	0
T29	586	186	0	0
T30	548	148	0	0
T40	46119	45688	0	0
T41	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	693	0	0
T13	2154	0	0	0
T14	569	0	0	0
T15	27039	0	0	0
T16	0	3	0	0
T19	0	13	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T40	46119	13	0	0
T41	522	0	0	0
T46	0	15	0	0
T61	0	8	0	0
T110	0	21	0	0
T135	0	7	0	0
T136	0	23	0	0
T275	0	22	0	0
T276	0	9	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T40,T15,T32
1	Covered	T40,T41,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T40,T15,T32
1	0	Covered	T40,T41,T13
1	1	Covered	T40,T41,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T15,T16,T62

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T40,T41,T13	VC_COV_UNR
1	Covered	T15,T16,T62

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T15,T16,T62

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T40,T15,T16
1	0	Covered	T40,T13,T15
1	1	Covered	T15,T16,T62

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T62
0	1	Covered	T15,T48,T83
1	0	Covered	T84,T85

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T62,T19
0	1	Covered	T16,T62,T19
1	0	Covered	T86

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T16,T62,T19
1	-	Covered	T16,T62,T19

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4
DetectSt	168	Covered	T4
IdleSt	163	Covered	T4
StableSt	191	Covered	T4

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4
DebounceSt->IdleSt	163	Covered	T4
DetectSt->IdleSt	186	Covered	T4
DetectSt->StableSt	191	Covered	T4
IdleSt->DebounceSt	148	Covered	T4
StableSt->IdleSt	206	Covered	T4

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T15,T16,T62
0	1	Covered	T15,T16,T62
0	0	Excluded	T40,T41,T13	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T62
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T15,T16,T62
IdleSt	0	-	-	-	-	-	-	Covered	T40,T41,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T84,T85
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T16,T62
DebounceSt	-	0	1	0	-	-	-	Covered	T15,T62,T65
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T16,T62
DetectSt	-	-	-	-	1	-	-	Covered	T15,T48,T83
DetectSt	-	-	-	-	0	1	-	Covered	T16,T62,T19
DetectSt	-	-	-	-	0	0	-	Covered	T15,T16,T62
StableSt	-	-	-	-	-	-	1	Covered	T16,T62,T19
StableSt	-	-	-	-	-	-	0	Covered	T16,T62,T19
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7780736	718	0	0
CntIncr_A	7780736	44107	0	0
CntNoWrap_A	7780736	7115807	0	0
DetectStDropOut_A	7780736	90	0	0
DetectedOut_A	7780736	11085	0	0
DetectedPulseOut_A	7780736	244	0	0
DisabledIdleSt_A	7780736	6782264	0	0
DisabledNoDetection_A	7780736	6783993	0	0
EnterDebounceSt_A	7780736	382	0	0
EnterDetectSt_A	7780736	339	0	0
EnterStableSt_A	7780736	244	0	0
PulseIsPulse_A	7780736	244	0	0
StayInStableSt	7780736	10819	0	0
gen_high_level_sva.HighLevelEvent_A	7780736	7118843	0	0
gen_not_sticky_sva.StableStDropOut_A	7780736	219	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	718	0	0
T15	27039	9	0	0
T16	23425	2	0	0
T19	0	4	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T45	0	8	0	0
T46	0	6	0	0
T48	0	8	0	0
T62	0	11	0	0
T65	0	5	0	0
T66	494	0	0	0
T67	422	0	0	0
T68	631	0	0	0
T69	510	0	0	0
T83	0	22	0	0
T139	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	44107	0	0
T15	27039	726	0	0
T16	23425	53	0	0
T19	0	320	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T45	0	394	0	0
T46	0	165	0	0
T48	0	855	0	0
T62	0	746	0	0
T63	0	67	0	0
T65	0	421	0	0
T66	494	0	0	0
T67	422	0	0	0
T68	631	0	0	0
T69	510	0	0	0
T83	0	1500	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7115807	0	0
T13	2154	551	0	0
T14	569	168	0	0
T15	27039	26561	0	0
T26	99226	98825	0	0
T27	502	101	0	0
T28	659	258	0	0
T29	586	185	0	0
T30	548	147	0	0
T40	46119	45682	0	0
T41	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	90	0	0
T15	27039	4	0	0
T16	23425	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T47	0	2	0	0
T48	0	1	0	0
T66	494	0	0	0
T67	422	0	0	0
T68	631	0	0	0
T69	510	0	0	0
T83	0	11	0	0
T97	0	1	0	0
T111	0	4	0	0
T206	0	3	0	0
T278	0	1	0	0
T279	0	10	0	0
T280	0	9	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	11085	0	0
T16	23425	68	0	0
T19	23904	82	0	0
T45	0	182	0	0
T46	0	200	0	0
T47	0	261	0	0
T48	0	23	0	0
T62	33073	90	0	0
T65	0	10	0	0
T67	422	0	0	0
T68	631	0	0	0
T69	510	0	0	0
T71	421	0	0	0
T90	4870	0	0	0
T91	5616	0	0	0
T104	502	0	0	0
T136	0	211	0	0
T139	0	102	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	244	0	0
T16	23425	1	0	0
T19	23904	2	0	0
T45	0	4	0	0
T46	0	3	0	0
T47	0	5	0	0
T48	0	3	0	0
T62	33073	5	0	0
T65	0	2	0	0
T67	422	0	0	0
T68	631	0	0	0
T69	510	0	0	0
T71	421	0	0	0
T90	4870	0	0	0
T91	5616	0	0	0
T104	502	0	0	0
T136	0	3	0	0
T139	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	6782264	0	0
T13	2154	551	0	0
T14	569	168	0	0
T15	27039	22159	0	0
T26	99226	98825	0	0
T27	502	101	0	0
T28	659	258	0	0
T29	586	185	0	0
T30	548	147	0	0
T40	46119	44347	0	0
T41	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	6783993	0	0
T13	2154	554	0	0
T14	569	169	0	0
T15	27039	22159	0	0
T26	99226	98826	0	0
T27	502	102	0	0
T28	659	259	0	0
T29	586	186	0	0
T30	548	148	0	0
T40	46119	44353	0	0
T41	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	382	0	0
T15	27039	5	0	0
T16	23425	1	0	0
T19	0	2	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T45	0	4	0	0
T46	0	3	0	0
T48	0	4	0	0
T62	0	6	0	0
T63	0	1	0	0
T65	0	3	0	0
T66	494	0	0	0
T67	422	0	0	0
T68	631	0	0	0
T69	510	0	0	0
T83	0	11	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	339	0	0
T15	27039	4	0	0
T16	23425	1	0	0
T19	0	2	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T45	0	4	0	0
T46	0	3	0	0
T48	0	4	0	0
T62	0	5	0	0
T65	0	2	0	0
T66	494	0	0	0
T67	422	0	0	0
T68	631	0	0	0
T69	510	0	0	0
T83	0	11	0	0
T139	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	244	0	0
T16	23425	1	0	0
T19	23904	2	0	0
T45	0	4	0	0
T46	0	3	0	0
T47	0	5	0	0
T48	0	3	0	0
T62	33073	5	0	0
T65	0	2	0	0
T67	422	0	0	0
T68	631	0	0	0
T69	510	0	0	0
T71	421	0	0	0
T90	4870	0	0	0
T91	5616	0	0	0
T104	502	0	0	0
T136	0	3	0	0
T139	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	244	0	0
T16	23425	1	0	0
T19	23904	2	0	0
T45	0	4	0	0
T46	0	3	0	0
T47	0	5	0	0
T48	0	3	0	0
T62	33073	5	0	0
T65	0	2	0	0
T67	422	0	0	0
T68	631	0	0	0
T69	510	0	0	0
T71	421	0	0	0
T90	4870	0	0	0
T91	5616	0	0	0
T104	502	0	0	0
T136	0	3	0	0
T139	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	10819	0	0
T16	23425	67	0	0
T19	23904	80	0	0
T45	0	178	0	0
T46	0	194	0	0
T47	0	256	0	0
T48	0	20	0	0
T62	33073	85	0	0
T65	0	8	0	0
T67	422	0	0	0
T68	631	0	0	0
T69	510	0	0	0
T71	421	0	0	0
T90	4870	0	0	0
T91	5616	0	0	0
T104	502	0	0	0
T136	0	206	0	0
T139	0	100	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7118843	0	0
T13	2154	554	0	0
T14	569	169	0	0
T15	27039	26581	0	0
T26	99226	98826	0	0
T27	502	102	0	0
T28	659	259	0	0
T29	586	186	0	0
T30	548	148	0	0
T40	46119	45688	0	0
T41	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	219	0	0
T16	23425	1	0	0
T19	23904	2	0	0
T45	0	4	0	0
T47	0	5	0	0
T48	0	3	0	0
T62	33073	5	0	0
T65	0	2	0	0
T67	422	0	0	0
T68	631	0	0	0
T69	510	0	0	0
T71	421	0	0	0
T90	4870	0	0	0
T91	5616	0	0	0
T104	502	0	0	0
T119	0	6	0	0
T136	0	1	0	0
T139	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T40,T32,T16
1	Covered	T40,T41,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T40,T32,T16

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T40,T32,T16

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T40,T32,T16

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T40,T32,T16
1	0	Covered	T40,T32,T16
1	1	Covered	T40,T32,T16

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T40,T32,T16
0	1	Covered	T32,T91,T105
1	0	Covered	T32,T19,T110

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T40,T16,T61
0	1	Covered	T40,T16,T61
1	0	Covered	T92,T85

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T40,T16,T61
1	-	Covered	T40,T16,T61

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4
DetectSt	168	Covered	T4
IdleSt	163	Covered	T4
StableSt	191	Covered	T4

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4
DebounceSt->IdleSt	163	Covered	T4
DetectSt->IdleSt	186	Covered	T4
DetectSt->StableSt	191	Covered	T4
IdleSt->DebounceSt	148	Covered	T4
StableSt->IdleSt	206	Covered	T4

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T40,T32,T16
0	1	Covered	T40,T32,T16
0	0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T40,T32,T16
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T40,T32,T16
IdleSt	0	-	-	-	-	-	-	Covered	T40,T32,T16
DebounceSt	-	1	-	-	-	-	-	Covered	T84,T85
DebounceSt	-	0	1	1	-	-	-	Covered	T40,T32,T16
DebounceSt	-	0	1	0	-	-	-	Covered	T84,T274,T85
DebounceSt	-	0	0	-	-	-	-	Covered	T40,T32,T16
DetectSt	-	-	-	-	1	-	-	Covered	T32,T91,T19
DetectSt	-	-	-	-	0	1	-	Covered	T40,T16,T61
DetectSt	-	-	-	-	0	0	-	Covered	T40,T32,T16
StableSt	-	-	-	-	-	-	1	Covered	T40,T16,T61
StableSt	-	-	-	-	-	-	0	Covered	T40,T16,T61
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7780736	3092	0	0
CntIncr_A	7780736	113675	0	0
CntNoWrap_A	7780736	7113433	0	0
DetectStDropOut_A	7780736	509	0	0
DetectedOut_A	7780736	68100	0	0
DetectedPulseOut_A	7780736	851	0	0
DisabledIdleSt_A	7780736	6631204	0	0
DisabledNoDetection_A	7780736	6633322	0	0
EnterDebounceSt_A	7780736	1552	0	0
EnterDetectSt_A	7780736	1540	0	0
EnterStableSt_A	7780736	851	0	0
PulseIsPulse_A	7780736	851	0	0
StayInStableSt	7780736	67143	0	0
gen_high_event_sva.HighLevelEvent_A	7780736	7118843	0	0
gen_high_level_sva.HighLevelEvent_A	7780736	7118843	0	0
gen_not_sticky_sva.StableStDropOut_A	7780736	741	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	3092	0	0
T13	2154	0	0	0
T14	569	0	0	0
T15	27039	0	0	0
T16	0	22	0	0
T19	0	20	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T32	0	54	0	0
T40	46119	26	0	0
T41	522	0	0	0
T46	0	30	0	0
T49	0	12	0	0
T61	0	54	0	0
T91	0	34	0	0
T102	0	22	0	0
T105	0	26	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	113675	0	0
T13	2154	0	0	0
T14	569	0	0	0
T15	27039	0	0	0
T16	0	473	0	0
T19	0	2491	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T32	0	2097	0	0
T40	46119	3848	0	0
T41	522	0	0	0
T46	0	1005	0	0
T49	0	198	0	0
T61	0	648	0	0
T91	0	1012	0	0
T102	0	693	0	0
T105	0	605	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7113433	0	0
T13	2154	551	0	0
T14	569	168	0	0
T15	27039	26570	0	0
T26	99226	98825	0	0
T27	502	101	0	0
T28	659	258	0	0
T29	586	185	0	0
T30	548	147	0	0
T40	46119	45656	0	0
T41	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	509	0	0
T16	23425	0	0	0
T32	7989	12	0	0
T66	494	0	0	0
T67	422	0	0	0
T68	631	0	0	0
T69	510	0	0	0
T90	4870	0	0	0
T91	5616	17	0	0
T104	502	0	0	0
T105	4968	13	0	0
T106	0	19	0	0
T108	0	13	0	0
T109	0	24	0	0
T110	0	14	0	0
T120	0	13	0	0
T125	0	9	0	0
T281	0	32	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	68100	0	0
T13	2154	0	0	0
T14	569	0	0	0
T15	27039	0	0	0
T16	0	1784	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T40	46119	3376	0	0
T41	522	0	0	0
T46	0	709	0	0
T49	0	737	0	0
T61	0	1912	0	0
T64	0	1733	0	0
T102	0	870	0	0
T107	0	1338	0	0
T135	0	365	0	0
T277	0	1646	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	851	0	0
T13	2154	0	0	0
T14	569	0	0	0
T15	27039	0	0	0
T16	0	11	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T40	46119	13	0	0
T41	522	0	0	0
T46	0	15	0	0
T49	0	6	0	0
T61	0	27	0	0
T64	0	3	0	0
T102	0	11	0	0
T107	0	27	0	0
T135	0	15	0	0
T277	0	11	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	6631204	0	0
T13	2154	551	0	0
T14	569	168	0	0
T15	27039	26570	0	0
T26	99226	98825	0	0
T27	502	101	0	0
T28	659	258	0	0
T29	586	185	0	0
T30	548	147	0	0
T40	46119	17762	0	0
T41	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	6633322	0	0
T13	2154	554	0	0
T14	569	169	0	0
T15	27039	26581	0	0
T26	99226	98826	0	0
T27	502	102	0	0
T28	659	259	0	0
T29	586	186	0	0
T30	548	148	0	0
T40	46119	17767	0	0
T41	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	1552	0	0
T13	2154	0	0	0
T14	569	0	0	0
T15	27039	0	0	0
T16	0	11	0	0
T19	0	10	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T32	0	27	0	0
T40	46119	13	0	0
T41	522	0	0	0
T46	0	15	0	0
T49	0	6	0	0
T61	0	27	0	0
T91	0	17	0	0
T102	0	11	0	0
T105	0	13	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	1540	0	0
T13	2154	0	0	0
T14	569	0	0	0
T15	27039	0	0	0
T16	0	11	0	0
T19	0	10	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T32	0	27	0	0
T40	46119	13	0	0
T41	522	0	0	0
T46	0	15	0	0
T49	0	6	0	0
T61	0	27	0	0
T91	0	17	0	0
T102	0	11	0	0
T105	0	13	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	851	0	0
T13	2154	0	0	0
T14	569	0	0	0
T15	27039	0	0	0
T16	0	11	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T40	46119	13	0	0
T41	522	0	0	0
T46	0	15	0	0
T49	0	6	0	0
T61	0	27	0	0
T64	0	3	0	0
T102	0	11	0	0
T107	0	27	0	0
T135	0	15	0	0
T277	0	11	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	851	0	0
T13	2154	0	0	0
T14	569	0	0	0
T15	27039	0	0	0
T16	0	11	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T40	46119	13	0	0
T41	522	0	0	0
T46	0	15	0	0
T49	0	6	0	0
T61	0	27	0	0
T64	0	3	0	0
T102	0	11	0	0
T107	0	27	0	0
T135	0	15	0	0
T277	0	11	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	67143	0	0
T13	2154	0	0	0
T14	569	0	0	0
T15	27039	0	0	0
T16	0	1765	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T40	46119	3363	0	0
T41	522	0	0	0
T46	0	691	0	0
T49	0	727	0	0
T61	0	1879	0	0
T64	0	1729	0	0
T102	0	857	0	0
T107	0	1310	0	0
T135	0	350	0	0
T277	0	1632	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7118843	0	0
T13	2154	554	0	0
T14	569	169	0	0
T15	27039	26581	0	0
T26	99226	98826	0	0
T27	502	102	0	0
T28	659	259	0	0
T29	586	186	0	0
T30	548	148	0	0
T40	46119	45688	0	0
T41	522	122	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7118843	0	0
T13	2154	554	0	0
T14	569	169	0	0
T15	27039	26581	0	0
T26	99226	98826	0	0
T27	502	102	0	0
T28	659	259	0	0
T29	586	186	0	0
T30	548	148	0	0
T40	46119	45688	0	0
T41	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	741	0	0
T13	2154	0	0	0
T14	569	0	0	0
T15	27039	0	0	0
T16	0	3	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T40	46119	13	0	0
T41	522	0	0	0
T46	0	12	0	0
T49	0	2	0	0
T61	0	21	0	0
T64	0	2	0	0
T102	0	9	0	0
T107	0	26	0	0
T135	0	15	0	0
T277	0	8	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T40,T15,T32
1	Covered	T40,T41,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T40,T15,T32
1	0	Covered	T40,T41,T13
1	1	Covered	T40,T41,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T15,T16,T62

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T40,T41,T13	VC_COV_UNR
1	Covered	T15,T16,T62

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T15,T16,T62

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T40,T15,T16
1	0	Covered	T40,T13,T15
1	1	Covered	T15,T16,T62

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T62
0	1	Covered	T48,T47,T119
1	0	Covered	T84,T85

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T62
0	1	Covered	T15,T62,T45
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T15,T16,T62
1	-	Covered	T15,T62,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4
DetectSt	168	Covered	T4
IdleSt	163	Covered	T4
StableSt	191	Covered	T4

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4
DebounceSt->IdleSt	163	Covered	T4
DetectSt->IdleSt	186	Covered	T4
DetectSt->StableSt	191	Covered	T4
IdleSt->DebounceSt	148	Covered	T4
StableSt->IdleSt	206	Covered	T4

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T15,T16,T62
0	1	Covered	T15,T16,T62
0	0	Excluded	T40,T41,T13	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T62
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T15,T16,T62
IdleSt	0	-	-	-	-	-	-	Covered	T40,T41,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T84,T85
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T16,T62
DebounceSt	-	0	1	0	-	-	-	Covered	T15,T65,T83
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T16,T62
DetectSt	-	-	-	-	1	-	-	Covered	T48,T47,T119
DetectSt	-	-	-	-	0	1	-	Covered	T15,T16,T62
DetectSt	-	-	-	-	0	0	-	Covered	T15,T16,T62
StableSt	-	-	-	-	-	-	1	Covered	T15,T62,T45
StableSt	-	-	-	-	-	-	0	Covered	T15,T16,T62
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7780736	815	0	0
CntIncr_A	7780736	43720	0	0
CntNoWrap_A	7780736	7115710	0	0
DetectStDropOut_A	7780736	49	0	0
DetectedOut_A	7780736	14853	0	0
DetectedPulseOut_A	7780736	329	0	0
DisabledIdleSt_A	7780736	6786982	0	0
DisabledNoDetection_A	7780736	6788691	0	0
EnterDebounceSt_A	7780736	435	0	0
EnterDetectSt_A	7780736	382	0	0
EnterStableSt_A	7780736	329	0	0
PulseIsPulse_A	7780736	329	0	0
StayInStableSt	7780736	14464	0	0
gen_high_level_sva.HighLevelEvent_A	7780736	7118843	0	0
gen_not_sticky_sva.StableStDropOut_A	7780736	265	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	815	0	0
T15	27039	19	0	0
T16	23425	16	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T45	0	12	0	0
T46	0	4	0	0
T48	0	32	0	0
T49	0	8	0	0
T61	0	12	0	0
T62	0	6	0	0
T64	0	2	0	0
T66	494	0	0	0
T67	422	0	0	0
T68	631	0	0	0
T69	510	0	0	0
T102	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	43720	0	0
T15	27039	1425	0	0
T16	23425	384	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T45	0	564	0	0
T46	0	102	0	0
T48	0	2524	0	0
T49	0	252	0	0
T61	0	240	0	0
T62	0	411	0	0
T63	0	67	0	0
T66	494	0	0	0
T67	422	0	0	0
T68	631	0	0	0
T69	510	0	0	0
T102	0	58	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7115710	0	0
T13	2154	551	0	0
T14	569	168	0	0
T15	27039	26551	0	0
T26	99226	98825	0	0
T27	502	101	0	0
T28	659	258	0	0
T29	586	185	0	0
T30	548	147	0	0
T40	46119	45682	0	0
T41	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	49	0	0
T47	0	5	0	0
T48	50635	8	0	0
T64	20794	0	0	0
T65	15427	0	0	0
T83	18456	0	0	0
T85	0	1	0	0
T89	0	1	0	0
T102	18370	0	0	0
T105	4968	0	0	0
T119	0	6	0	0
T135	10692	0	0	0
T270	0	8	0	0
T282	0	1	0	0
T283	0	4	0	0
T284	0	2	0	0
T285	0	5	0	0
T286	523	0	0	0
T287	490	0	0	0
T288	502	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	14853	0	0
T15	27039	103	0	0
T16	23425	579	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T45	0	477	0	0
T46	0	143	0	0
T48	0	485	0	0
T49	0	139	0	0
T61	0	195	0	0
T62	0	52	0	0
T64	0	51	0	0
T66	494	0	0	0
T67	422	0	0	0
T68	631	0	0	0
T69	510	0	0	0
T102	0	56	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	329	0	0
T15	27039	9	0	0
T16	23425	8	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T45	0	6	0	0
T46	0	2	0	0
T48	0	8	0	0
T49	0	4	0	0
T61	0	6	0	0
T62	0	3	0	0
T64	0	1	0	0
T66	494	0	0	0
T67	422	0	0	0
T68	631	0	0	0
T69	510	0	0	0
T102	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	6786982	0	0
T13	2154	551	0	0
T14	569	168	0	0
T15	27039	22159	0	0
T26	99226	98825	0	0
T27	502	101	0	0
T28	659	258	0	0
T29	586	185	0	0
T30	548	147	0	0
T40	46119	42306	0	0
T41	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	6788691	0	0
T13	2154	554	0	0
T14	569	169	0	0
T15	27039	22159	0	0
T26	99226	98826	0	0
T27	502	102	0	0
T28	659	259	0	0
T29	586	186	0	0
T30	548	148	0	0
T40	46119	42312	0	0
T41	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	435	0	0
T15	27039	10	0	0
T16	23425	8	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T45	0	6	0	0
T46	0	2	0	0
T48	0	16	0	0
T49	0	4	0	0
T61	0	6	0	0
T62	0	3	0	0
T63	0	1	0	0
T66	494	0	0	0
T67	422	0	0	0
T68	631	0	0	0
T69	510	0	0	0
T102	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	382	0	0
T15	27039	9	0	0
T16	23425	8	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T45	0	6	0	0
T46	0	2	0	0
T48	0	16	0	0
T49	0	4	0	0
T61	0	6	0	0
T62	0	3	0	0
T64	0	1	0	0
T66	494	0	0	0
T67	422	0	0	0
T68	631	0	0	0
T69	510	0	0	0
T102	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	329	0	0
T15	27039	9	0	0
T16	23425	8	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T45	0	6	0	0
T46	0	2	0	0
T48	0	8	0	0
T49	0	4	0	0
T61	0	6	0	0
T62	0	3	0	0
T64	0	1	0	0
T66	494	0	0	0
T67	422	0	0	0
T68	631	0	0	0
T69	510	0	0	0
T102	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	329	0	0
T15	27039	9	0	0
T16	23425	8	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T45	0	6	0	0
T46	0	2	0	0
T48	0	8	0	0
T49	0	4	0	0
T61	0	6	0	0
T62	0	3	0	0
T64	0	1	0	0
T66	494	0	0	0
T67	422	0	0	0
T68	631	0	0	0
T69	510	0	0	0
T102	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	14464	0	0
T15	27039	94	0	0
T16	23425	563	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T45	0	471	0	0
T46	0	141	0	0
T48	0	477	0	0
T49	0	132	0	0
T61	0	183	0	0
T62	0	49	0	0
T64	0	50	0	0
T66	494	0	0	0
T67	422	0	0	0
T68	631	0	0	0
T69	510	0	0	0
T102	0	54	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7118843	0	0
T13	2154	554	0	0
T14	569	169	0	0
T15	27039	26581	0	0
T26	99226	98826	0	0
T27	502	102	0	0
T28	659	259	0	0
T29	586	186	0	0
T30	548	148	0	0
T40	46119	45688	0	0
T41	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	265	0	0
T15	27039	9	0	0
T16	23425	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T45	0	6	0	0
T46	0	2	0	0
T48	0	8	0	0
T49	0	1	0	0
T62	0	3	0	0
T64	0	1	0	0
T65	0	4	0	0
T66	494	0	0	0
T67	422	0	0	0
T68	631	0	0	0
T69	510	0	0	0
T83	0	3	0	0
T277	0	3	0	0