Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T40,T32,T16
1	Covered	T40,T41,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T40,T32,T16

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T40,T32,T16

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T40,T32,T16

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T40,T32,T16
1	0	Covered	T40,T32,T16
1	1	Covered	T40,T32,T16

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T40,T32,T16
0	1	Covered	T32,T16,T91
1	0	Covered	T32,T16,T102

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T40,T19,T61
0	1	Covered	T40,T19,T61
1	0	Covered	T289

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T40,T19,T61
1	-	Covered	T40,T19,T61

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4
DetectSt	168	Covered	T4
IdleSt	163	Covered	T4
StableSt	191	Covered	T4

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4
DebounceSt->IdleSt	163	Covered	T4
DetectSt->IdleSt	186	Covered	T4
DetectSt->StableSt	191	Covered	T4
IdleSt->DebounceSt	148	Covered	T4
StableSt->IdleSt	206	Covered	T4

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T40,T32,T16
0	1	Covered	T40,T32,T16
0	0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T40,T32,T16
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T40,T32,T16
IdleSt	0	-	-	-	-	-	-	Covered	T40,T32,T16
DebounceSt	-	1	-	-	-	-	-	Covered	T84,T85
DebounceSt	-	0	1	1	-	-	-	Covered	T40,T32,T16
DebounceSt	-	0	1	0	-	-	-	Covered	T84,T274,T85
DebounceSt	-	0	0	-	-	-	-	Covered	T40,T32,T16
DetectSt	-	-	-	-	1	-	-	Covered	T32,T16,T91
DetectSt	-	-	-	-	0	1	-	Covered	T40,T19,T61
DetectSt	-	-	-	-	0	0	-	Covered	T40,T32,T16
StableSt	-	-	-	-	-	-	1	Covered	T40,T19,T61
StableSt	-	-	-	-	-	-	0	Covered	T40,T19,T61
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7780736	2877	0	0
CntIncr_A	7780736	100578	0	0
CntNoWrap_A	7780736	7113648	0	0
DetectStDropOut_A	7780736	427	0	0
DetectedOut_A	7780736	71785	0	0
DetectedPulseOut_A	7780736	860	0	0
DisabledIdleSt_A	7780736	6631148	0	0
DisabledNoDetection_A	7780736	6633270	0	0
EnterDebounceSt_A	7780736	1444	0	0
EnterDetectSt_A	7780736	1434	0	0
EnterStableSt_A	7780736	860	0	0
PulseIsPulse_A	7780736	860	0	0
StayInStableSt	7780736	70823	0	0
gen_high_event_sva.HighLevelEvent_A	7780736	7118843	0	0
gen_high_level_sva.HighLevelEvent_A	7780736	7118843	0	0
gen_not_sticky_sva.StableStDropOut_A	7780736	755	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	2877	0	0
T13	2154	0	0	0
T14	569	0	0	0
T15	27039	0	0	0
T16	0	50	0	0
T19	0	10	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T32	0	54	0	0
T40	46119	22	0	0
T41	522	0	0	0
T46	0	30	0	0
T49	0	34	0	0
T61	0	24	0	0
T91	0	16	0	0
T102	0	56	0	0
T105	0	34	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	100578	0	0
T13	2154	0	0	0
T14	569	0	0	0
T15	27039	0	0	0
T16	0	1433	0	0
T19	0	770	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T32	0	2097	0	0
T40	46119	3300	0	0
T41	522	0	0	0
T46	0	975	0	0
T49	0	459	0	0
T61	0	300	0	0
T91	0	477	0	0
T102	0	2155	0	0
T105	0	791	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7113648	0	0
T13	2154	551	0	0
T14	569	168	0	0
T15	27039	26570	0	0
T26	99226	98825	0	0
T27	502	101	0	0
T28	659	258	0	0
T29	586	185	0	0
T30	548	147	0	0
T40	46119	45660	0	0
T41	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	427	0	0
T16	23425	19	0	0
T32	7989	12	0	0
T64	0	6	0	0
T66	494	0	0	0
T67	422	0	0	0
T68	631	0	0	0
T69	510	0	0	0
T90	4870	0	0	0
T91	5616	8	0	0
T104	502	0	0	0
T105	4968	17	0	0
T106	0	8	0	0
T108	0	13	0	0
T109	0	29	0	0
T120	0	21	0	0
T281	0	26	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	71785	0	0
T13	2154	0	0	0
T14	569	0	0	0
T15	27039	0	0	0
T19	0	695	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T40	46119	3564	0	0
T41	522	0	0	0
T46	0	1375	0	0
T49	0	2539	0	0
T61	0	746	0	0
T107	0	440	0	0
T135	0	214	0	0
T136	0	527	0	0
T275	0	688	0	0
T277	0	67	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	860	0	0
T13	2154	0	0	0
T14	569	0	0	0
T15	27039	0	0	0
T19	0	5	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T40	46119	11	0	0
T41	522	0	0	0
T46	0	15	0	0
T49	0	17	0	0
T61	0	12	0	0
T107	0	13	0	0
T135	0	6	0	0
T136	0	10	0	0
T275	0	14	0	0
T277	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	6631148	0	0
T13	2154	551	0	0
T14	569	168	0	0
T15	27039	26570	0	0
T26	99226	98825	0	0
T27	502	101	0	0
T28	659	258	0	0
T29	586	185	0	0
T30	548	147	0	0
T40	46119	17022	0	0
T41	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	6633270	0	0
T13	2154	554	0	0
T14	569	169	0	0
T15	27039	26581	0	0
T26	99226	98826	0	0
T27	502	102	0	0
T28	659	259	0	0
T29	586	186	0	0
T30	548	148	0	0
T40	46119	17027	0	0
T41	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	1444	0	0
T13	2154	0	0	0
T14	569	0	0	0
T15	27039	0	0	0
T16	0	25	0	0
T19	0	5	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T32	0	27	0	0
T40	46119	11	0	0
T41	522	0	0	0
T46	0	15	0	0
T49	0	17	0	0
T61	0	12	0	0
T91	0	8	0	0
T102	0	28	0	0
T105	0	17	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	1434	0	0
T13	2154	0	0	0
T14	569	0	0	0
T15	27039	0	0	0
T16	0	25	0	0
T19	0	5	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T32	0	27	0	0
T40	46119	11	0	0
T41	522	0	0	0
T46	0	15	0	0
T49	0	17	0	0
T61	0	12	0	0
T91	0	8	0	0
T102	0	28	0	0
T105	0	17	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	860	0	0
T13	2154	0	0	0
T14	569	0	0	0
T15	27039	0	0	0
T19	0	5	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T40	46119	11	0	0
T41	522	0	0	0
T46	0	15	0	0
T49	0	17	0	0
T61	0	12	0	0
T107	0	13	0	0
T135	0	6	0	0
T136	0	10	0	0
T275	0	14	0	0
T277	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	860	0	0
T13	2154	0	0	0
T14	569	0	0	0
T15	27039	0	0	0
T19	0	5	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T40	46119	11	0	0
T41	522	0	0	0
T46	0	15	0	0
T49	0	17	0	0
T61	0	12	0	0
T107	0	13	0	0
T135	0	6	0	0
T136	0	10	0	0
T275	0	14	0	0
T277	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	70823	0	0
T13	2154	0	0	0
T14	569	0	0	0
T15	27039	0	0	0
T19	0	689	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T40	46119	3553	0	0
T41	522	0	0	0
T46	0	1358	0	0
T49	0	2512	0	0
T61	0	731	0	0
T107	0	426	0	0
T135	0	208	0	0
T136	0	517	0	0
T275	0	674	0	0
T277	0	64	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7118843	0	0
T13	2154	554	0	0
T14	569	169	0	0
T15	27039	26581	0	0
T26	99226	98826	0	0
T27	502	102	0	0
T28	659	259	0	0
T29	586	186	0	0
T30	548	148	0	0
T40	46119	45688	0	0
T41	522	122	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7118843	0	0
T13	2154	554	0	0
T14	569	169	0	0
T15	27039	26581	0	0
T26	99226	98826	0	0
T27	502	102	0	0
T28	659	259	0	0
T29	586	186	0	0
T30	548	148	0	0
T40	46119	45688	0	0
T41	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	755	0	0
T13	2154	0	0	0
T14	569	0	0	0
T15	27039	0	0	0
T19	0	4	0	0
T26	99226	0	0	0
T27	502	0	0	0
T28	659	0	0	0
T29	586	0	0	0
T30	548	0	0	0
T40	46119	11	0	0
T41	522	0	0	0
T46	0	13	0	0
T49	0	7	0	0
T61	0	9	0	0
T107	0	12	0	0
T135	0	6	0	0
T136	0	10	0	0
T275	0	14	0	0
T277	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T40,T15,T32
1	Covered	T40,T41,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T40,T15,T32
1	0	Covered	T40,T41,T13
1	1	Covered	T40,T41,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T15,T62,T19

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T40,T41,T13	VC_COV_UNR
1	Covered	T15,T62,T19

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T40,T41,T13
1	Covered	T15,T62,T19

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T40,T15,T62
1	0	Covered	T40,T13,T15
1	1	Covered	T15,T62,T19

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T62,T19
0	1	Covered	T45,T47,T282
1	0	Covered	T84,T85

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T62,T19
0	1	Covered	T15,T62,T19
1	0	Covered	T46

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T15,T62,T19
1	-	Covered	T15,T62,T19

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4
DetectSt	168	Covered	T4
IdleSt	163	Covered	T4
StableSt	191	Covered	T4

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4
DebounceSt->IdleSt	163	Covered	T4
DetectSt->IdleSt	186	Covered	T4
DetectSt->StableSt	191	Covered	T4
IdleSt->DebounceSt	148	Covered	T4
StableSt->IdleSt	206	Covered	T4

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T15,T62,T19
0	1	Covered	T15,T62,T19
0	0	Excluded	T40,T41,T13	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T62,T19
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T15,T62,T19
IdleSt	0	-	-	-	-	-	-	Covered	T40,T41,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T84,T85
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T62,T19
DebounceSt	-	0	1	0	-	-	-	Covered	T15,T62,T65
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T62,T19
DetectSt	-	-	-	-	1	-	-	Covered	T45,T47,T84
DetectSt	-	-	-	-	0	1	-	Covered	T15,T62,T19
DetectSt	-	-	-	-	0	0	-	Covered	T15,T62,T19
StableSt	-	-	-	-	-	-	1	Covered	T15,T62,T19
StableSt	-	-	-	-	-	-	0	Covered	T15,T62,T19
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T13
0	Covered	T40,T41,T13

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7780736	721	0	0
CntIncr_A	7780736	40384	0	0
CntNoWrap_A	7780736	7115804	0	0
DetectStDropOut_A	7780736	35	0	0
DetectedOut_A	7780736	13881	0	0
DetectedPulseOut_A	7780736	305	0	0
DisabledIdleSt_A	7780736	6768304	0	0
DisabledNoDetection_A	7780736	6770006	0	0
EnterDebounceSt_A	7780736	379	0	0
EnterDetectSt_A	7780736	344	0	0
EnterStableSt_A	7780736	305	0	0
PulseIsPulse_A	7780736	305	0	0
StayInStableSt	7780736	13551	0	0
gen_high_level_sva.HighLevelEvent_A	7780736	7118843	0	0
gen_not_sticky_sva.StableStDropOut_A	7780736	277	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	721	0	0
T15	27039	15	0	0
T16	23425	0	0	0
T19	0	2	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T45	0	4	0	0
T46	0	4	0	0
T48	0	16	0	0
T49	0	14	0	0
T61	0	2	0	0
T62	0	24	0	0
T65	0	6	0	0
T66	494	0	0	0
T67	422	0	0	0
T68	631	0	0	0
T69	510	0	0	0
T139	0	16	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	40384	0	0
T15	27039	1015	0	0
T16	23425	0	0	0
T19	0	154	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T45	0	209	0	0
T46	0	164	0	0
T48	0	1140	0	0
T49	0	462	0	0
T61	0	23	0	0
T62	0	1442	0	0
T63	0	68	0	0
T65	0	332	0	0
T66	494	0	0	0
T67	422	0	0	0
T68	631	0	0	0
T69	510	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7115804	0	0
T13	2154	551	0	0
T14	569	168	0	0
T15	27039	26555	0	0
T26	99226	98825	0	0
T27	502	101	0	0
T28	659	258	0	0
T29	586	185	0	0
T30	548	147	0	0
T40	46119	45682	0	0
T41	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	35	0	0
T44	1139	0	0	0
T45	102206	1	0	0
T46	18603	0	0	0
T47	0	5	0	0
T101	718	0	0	0
T157	0	1	0	0
T172	439	0	0	0
T173	420	0	0	0
T174	411	0	0	0
T175	424	0	0	0
T207	495	0	0	0
T252	1333	0	0	0
T282	0	2	0	0
T285	0	4	0	0
T290	0	4	0	0
T291	0	14	0	0
T292	0	1	0	0
T293	0	2	0	0
T294	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	13881	0	0
T15	27039	194	0	0
T16	23425	0	0	0
T19	0	48	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T45	0	78	0	0
T46	0	84	0	0
T48	0	237	0	0
T49	0	230	0	0
T61	0	49	0	0
T62	0	383	0	0
T65	0	174	0	0
T66	494	0	0	0
T67	422	0	0	0
T68	631	0	0	0
T69	510	0	0	0
T139	0	600	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	305	0	0
T15	27039	7	0	0
T16	23425	0	0	0
T19	0	1	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T45	0	1	0	0
T46	0	2	0	0
T48	0	8	0	0
T49	0	7	0	0
T61	0	1	0	0
T62	0	11	0	0
T65	0	2	0	0
T66	494	0	0	0
T67	422	0	0	0
T68	631	0	0	0
T69	510	0	0	0
T139	0	8	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	6768304	0	0
T13	2154	551	0	0
T14	569	168	0	0
T15	27039	22159	0	0
T26	99226	98825	0	0
T27	502	101	0	0
T28	659	258	0	0
T29	586	185	0	0
T30	548	147	0	0
T40	46119	42118	0	0
T41	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	6770006	0	0
T13	2154	554	0	0
T14	569	169	0	0
T15	27039	22159	0	0
T26	99226	98826	0	0
T27	502	102	0	0
T28	659	259	0	0
T29	586	186	0	0
T30	548	148	0	0
T40	46119	42124	0	0
T41	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	379	0	0
T15	27039	8	0	0
T16	23425	0	0	0
T19	0	1	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T45	0	2	0	0
T46	0	2	0	0
T48	0	8	0	0
T49	0	7	0	0
T61	0	1	0	0
T62	0	13	0	0
T63	0	1	0	0
T65	0	4	0	0
T66	494	0	0	0
T67	422	0	0	0
T68	631	0	0	0
T69	510	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	344	0	0
T15	27039	7	0	0
T16	23425	0	0	0
T19	0	1	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T45	0	2	0	0
T46	0	2	0	0
T48	0	8	0	0
T49	0	7	0	0
T61	0	1	0	0
T62	0	11	0	0
T65	0	2	0	0
T66	494	0	0	0
T67	422	0	0	0
T68	631	0	0	0
T69	510	0	0	0
T139	0	8	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	305	0	0
T15	27039	7	0	0
T16	23425	0	0	0
T19	0	1	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T45	0	1	0	0
T46	0	2	0	0
T48	0	8	0	0
T49	0	7	0	0
T61	0	1	0	0
T62	0	11	0	0
T65	0	2	0	0
T66	494	0	0	0
T67	422	0	0	0
T68	631	0	0	0
T69	510	0	0	0
T139	0	8	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	305	0	0
T15	27039	7	0	0
T16	23425	0	0	0
T19	0	1	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T45	0	1	0	0
T46	0	2	0	0
T48	0	8	0	0
T49	0	7	0	0
T61	0	1	0	0
T62	0	11	0	0
T65	0	2	0	0
T66	494	0	0	0
T67	422	0	0	0
T68	631	0	0	0
T69	510	0	0	0
T139	0	8	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	13551	0	0
T15	27039	187	0	0
T16	23425	0	0	0
T19	0	47	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T45	0	77	0	0
T46	0	82	0	0
T48	0	229	0	0
T49	0	223	0	0
T61	0	47	0	0
T62	0	372	0	0
T65	0	172	0	0
T66	494	0	0	0
T67	422	0	0	0
T68	631	0	0	0
T69	510	0	0	0
T139	0	592	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	7118843	0	0
T13	2154	554	0	0
T14	569	169	0	0
T15	27039	26581	0	0
T26	99226	98826	0	0
T27	502	102	0	0
T28	659	259	0	0
T29	586	186	0	0
T30	548	148	0	0
T40	46119	45688	0	0
T41	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7780736	277	0	0
T15	27039	7	0	0
T16	23425	0	0	0
T19	0	1	0	0
T29	586	0	0	0
T30	548	0	0	0
T31	1338	0	0	0
T32	7989	0	0	0
T45	0	1	0	0
T47	0	4	0	0
T48	0	8	0	0
T49	0	7	0	0
T62	0	11	0	0
T65	0	2	0	0
T66	494	0	0	0
T67	422	0	0	0
T68	631	0	0	0
T69	510	0	0	0
T107	0	1	0	0
T139	0	8	0	0